From 442674cedced4d4852025a7399b4526e6f170207 Mon Sep 17 00:00:00 2001
From: CGH0S7 <776459475@qq.com>
Date: Mon, 27 Apr 2026 14:50:59 +0800
Subject: [PATCH] Fix direct sync_cache accesses bypassing use_transfer_cache()
 guard

Seven Parallel::*_cached() calls in RestrictProlong and
RestrictProlong_aux were missed during the transfer-cache refactoring
(commits 9cd3741..8d28c29). When BSSN_USE_TRANSFER_CACHE=0, all
sync_cache pointers are NULL, so dereferencing sync_cache_*[lev]
triggers SIGSEGV.

Replace them with the equivalent wrapper methods (sync_evolution,
restrict_evolution, outbdlow2hi_evolution) that check
use_transfer_cache() and fall back to uncached direct calls.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
---
 AMSS_NCKU_source/bssn_class.C | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/AMSS_NCKU_source/bssn_class.C b/AMSS_NCKU_source/bssn_class.C
index 23a074c..64675b5 100644
--- a/AMSS_NCKU_source/bssn_class.C
+++ b/AMSS_NCKU_source/bssn_class.C
@@ -6294,7 +6294,7 @@ void bssn_class::RestrictProlong(int lev, int YN, bool BB,
 #endif
     }
 
-    Parallel::Sync_cached(GH->PatL[lev], SL, Symmetry, sync_cache_rp_fine[lev]);
+    sync_evolution(lev, SL, sync_cache_rp_fine);
 
 #if (PSTR == 1 || PSTR == 2)
 //    a_stream.clear();
@@ -6433,17 +6433,17 @@ void bssn_class::RestrictProlong_aux(int lev, int YN, bool BB,
       }
 
 #if (RPB == 0)
-      Parallel::Restrict_cached(GH->PatL[lev - 1], GH->PatL[lev], SL, SynchList_pre, Symmetry, sync_cache_restrict[lev]);
+      restrict_evolution(lev, SL, SynchList_pre);
 #elif (RPB == 1)
       //       Parallel::Restrict_bam(GH->PatL[lev-1],GH->PatL[lev],SL,SynchList_pre,Symmetry);
       Parallel::Restrict_bam(GH->PatL[lev - 1], GH->PatL[lev], SL, SynchList_pre, GH->rsul[lev], Symmetry);
 #endif
 
-      Parallel::Sync_cached(GH->PatL[lev - 1], SynchList_pre, Symmetry, sync_cache_rp_coarse[lev]);
+      sync_evolution(lev - 1, SynchList_pre, sync_cache_rp_coarse);
 
 #if (RPB == 0)
 #if (MIXOUTB == 0)
-      Parallel::OutBdLow2Hi_cached(GH->PatL[lev - 1], GH->PatL[lev], SynchList_pre, SL, Symmetry, sync_cache_outbd[lev]);
+      outbdlow2hi_evolution(lev, SynchList_pre, SL);
 #elif (MIXOUTB == 1)
       Parallel::OutBdLow2Himix(GH->PatL[lev - 1], GH->PatL[lev], SynchList_pre, SL, Symmetry);
 #endif
@@ -6455,17 +6455,17 @@ void bssn_class::RestrictProlong_aux(int lev, int YN, bool BB,
     else // no time refinement levels and for all same time levels
     {
 #if (RPB == 0)
-      Parallel::Restrict_cached(GH->PatL[lev - 1], GH->PatL[lev], SL, SL, Symmetry, sync_cache_restrict[lev]);
+      restrict_evolution(lev, SL, SL);
 #elif (RPB == 1)
       //       Parallel::Restrict_bam(GH->PatL[lev-1],GH->PatL[lev],SL,SL,Symmetry);
       Parallel::Restrict_bam(GH->PatL[lev - 1], GH->PatL[lev], SL, SL, GH->rsul[lev], Symmetry);
 #endif
 
-      Parallel::Sync_cached(GH->PatL[lev - 1], SL, Symmetry, sync_cache_rp_coarse[lev]);
+      sync_evolution(lev - 1, SL, sync_cache_rp_coarse);
 
 #if (RPB == 0)
 #if (MIXOUTB == 0)
-      Parallel::OutBdLow2Hi_cached(GH->PatL[lev - 1], GH->PatL[lev], SL, SL, Symmetry, sync_cache_outbd[lev]);
+      outbdlow2hi_evolution(lev, SL, SL);
 #elif (MIXOUTB == 1)
       Parallel::OutBdLow2Himix(GH->PatL[lev - 1], GH->PatL[lev], SL, SL, Symmetry);
 #endif