prepare y86lab

This commit is contained in:
2025-03-21 09:24:48 +08:00
parent 7496b7cb1b
commit 559bba9c22
4 changed files with 173 additions and 0 deletions

11
y86lab/test.toy Normal file
View File

@ -0,0 +1,11 @@
000 031000
001 032001
002 033001
003 051002
004 052003
005 034101
006 064002
007 114009
008 100003
009 021011
010 000000

5
y86lab/test.toy2 Normal file
View File

@ -0,0 +1,5 @@
000 mov3 1 12
001 mov3 2 13
002 add 1 2
003 out 1
004 halt

77
y86lab/toy.py Normal file
View File

@ -0,0 +1,77 @@
mem = [0]*1000
reg = [0]*10
iReg = 0
pReg = 0
def loadProgram(file):
global mem, reg, iReg, pReg
fil = open(file,'r')
first = True
lineno = 0
while True:
line = fil.readline()
lineno += 1
if line == '':
break
fids = line.split()
try:
address = int(fids[0])
instruc = int(fids[1])
if first:
pReg = address
first = False
mem[address] = instruc
except:
print(f'File {file} line {lineno} has error')
pass
fil.close
def cycle():
global mem, reg, iReg, pReg
iReg = mem[pReg]
pReg = pReg + 1
opcode = (iReg//10000)
r = (iReg//1000) % 10
addr = (iReg) % 1000
if opcode == 0:
return False
elif opcode == 1: # mov1 Rx Ay
reg[r] = mem[addr]
elif opcode == 2: # mov2 Ay Rx
mem[addr] = reg[r]
elif opcode == 3: # mov3 Rx n
reg[r] = addr
elif opcode == 4: # mov4 Rx (Ry)
reg[r] = mem[reg[addr]]
elif opcode == 5: # add Rx Ry
reg[r] = reg[r] + reg[addr]
elif opcode == 6: # sub Rx Ry
reg[r] = reg[r] - reg[addr]
elif opcode == 7: # mul Rx Ry
reg[r] = reg[r] * reg[addr]
elif opcode == 8: # div Rx Ry
reg[r] = reg[r] // reg[addr]
elif opcode == 10: # jmp Ax
pReg = addr
elif opcode == 11: # jz Rx Ay
if reg[r] == 0:
pReg = addr
else:
print(f'Unknow opcode {opcode}')
return True
def run(file):
global mem, reg, iReg, pReg
loadProgram(file)
while True:
if not cycle():
break
run('D:/python/test.toy')

80
y86lab/toy2.py Normal file
View File

@ -0,0 +1,80 @@
mem = [''] * 1000
reg = [0] * 10
pReg = 0
iReg = ''
def loadProgram(file):
global pReg, iReg, reg, mem
fil = open(file, 'r')
first = True
while True:
line = fil.readline()
if line == '':
break
fids = line.split()
address = int(fids[0])
instruc = fids[1]
for fld in fids[2: len(fids)]:
instruc = instruc + ' ' + fld
mem[address] = instruc
if first:
pReg = address
first = False
fil.close()
def cycle():
global pReg, iReg, reg, mem
# 取指令
iReg = mem[pReg]
pReg = pReg + 1
# 译码
flds = iReg.split()
opcode = flds[0].lower() # 操作码
if len(flds) > 1:
op1 = int(flds[1]) # 操作数1
if len(flds) > 2:
op2 = int(flds[2]) # 操作数2
# 执行和写结果
if opcode == 'mov1':
reg[op1] = mem[op2]
elif opcode == 'mov2':
mem[op1] = reg[op2]
elif opcode == 'mov3':
reg[op1] = op2
elif opcode == 'add':
reg[op1] = reg[op1] + reg[op2]
elif opcode == 'sub':
reg[op1] = reg[op1] - reg[op2]
elif opcode == 'mul':
reg[op1] = reg[op1] * reg[op2]
elif opcode == 'div':
reg[op1] = reg[op1] // reg[op2]
elif opcode == 'jmp':
pReg = op1
elif opcode == 'jz':
if reg[op1] == 0:
pReg = op2
elif opcode == 'in':
reg[op1] = int(input('input:'))
elif opcode == 'out':
print('output:', reg[op1])
elif opcode == 'halt':
return False
else:
print(f'Unknown opcode {opcode}')
return True
def run(file):
global pReg, iReg, reg, mem
loadProgram(file)
while True:
hasNextInstruc = cycle()
if hasNextInstruc == False:
break
run('D:/python/test.toy2')