update PAPI support. other process and child process monitoring.
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@ -33,6 +33,7 @@
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#define LAPIC_ID 0x020
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#define LAPIC_TIMER 0x320
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#define LAPIC_LVTPC 0x340
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#define LAPIC_TIMER_INITIAL 0x380
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#define LAPIC_TIMER_CURRENT 0x390
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#define LAPIC_TIMER_DIVIDE 0x3e0
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@ -42,6 +43,7 @@
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#define LAPIC_ICR2 0x310
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#define LAPIC_ESR 0x280
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#define LOCAL_TIMER_VECTOR 0xef
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#define LOCAL_PERF_VECTOR 0xf0
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#define APIC_INT_LEVELTRIG 0x08000
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#define APIC_INT_ASSERT 0x04000
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@ -420,6 +422,7 @@ init_lapic()
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}
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lapic_write(LAPIC_SPURIOUS, 0x1ff);
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lapic_write(LAPIC_LVTPC, LOCAL_PERF_VECTOR);
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}
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void print_msr(int idx)
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@ -873,6 +876,15 @@ void handle_interrupt(int vector, struct x86_user_context *regs)
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ihk_mc_spinlock_unlock(&v->runq_lock, irqstate);
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dkprintf("timer[%lu]: CPU_FLAG_NEED_RESCHED \n", rdtsc());
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}
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else if (vector == LOCAL_PERF_VECTOR) {
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unsigned long value;
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value = rdmsr(MSR_PERF_GLOBAL_STATUS);
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wrmsr(MSR_PERF_GLOBAL_OVF_CTRL, value);
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wrmsr(MSR_PERF_GLOBAL_OVF_CTRL, 0);
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//TODO: counter overflow signal
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//set_signal(0x1d, regs, NULL); // SIGIO
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}
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else if (vector >= IHK_TLB_FLUSH_IRQ_VECTOR_START &&
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vector < IHK_TLB_FLUSH_IRQ_VECTOR_END) {
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@ -14,18 +14,24 @@
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#include <registers.h>
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extern unsigned int *x86_march_perfmap;
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static unsigned long pmc_status = 0x0;
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#define X86_CR4_PCE 0x00000100
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void x86_init_perfctr(void)
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{
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unsigned long reg;
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unsigned long value = 0;
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/* Allow PMC to be read from user space */
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asm volatile("movq %%cr4, %0" : "=r"(reg));
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reg |= X86_CR4_PCE;
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asm volatile("movq %0, %%cr4" : : "r"(reg));
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/* Enable PMC Control */
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value = rdmsr(MSR_PERF_GLOBAL_CTRL);
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value |= X86_IA32_PERF_COUNTERS_MASK;
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value |= X86_IA32_FIXED_PERF_COUNTERS_MASK;
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wrmsr(MSR_PERF_GLOBAL_CTRL, value);
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}
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static int set_perfctr_x86_direct(int counter, int mode, unsigned int value)
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@ -287,7 +293,7 @@ unsigned long ihk_mc_perfctr_read_msr(int counter)
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return retval;
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}
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int ihk_mc_perfctr_alloc_counter()
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int ihk_mc_perfctr_alloc_counter(unsigned long pmc_status)
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{
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int i = 0;
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int ret = -1;
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@ -307,15 +313,3 @@ int ihk_mc_perfctr_alloc_counter()
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return ret;
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}
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void ihk_mc_perfctr_release_counter(int counter)
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{
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unsigned long value = 0;
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value = rdmsr(MSR_PERF_GLOBAL_CTRL);
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value &= ~(1UL << counter);
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pmc_status &= ~(1UL << counter);
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wrmsr(MSR_PERF_GLOBAL_CTRL, 0);
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}
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