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make syscall_enter arch-dependent

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Change-Id: I4317f3443902620ef5b3807ced05c80fa5eebbec
Fujitsu: POSTK_DEBUG_ARCH_DEP_90
Refs: #1357
This commit is contained in:
Ken Sato
2019-09-09 15:37:09 +09:00
committed by Masamichi Takagi
parent fd38ab6fd0
commit 1492f16d67
6 changed files with 232 additions and 4 deletions
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88
test/issues/1357/x86_64_result.log Normal file
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*** C1357T01 start *******************************
ptrace01 1 TPASS : Test Passed
ptrace01 2 TPASS : Test Passed
*** C1357T01 PASSED (2)
*** C1357T02 start *******************************
ptrace02 1 TPASS : Test Passed
ptrace02 2 TPASS : Test Passed
*** C1357T02 PASSED (2)
*** C1357T03 start *******************************
ptrace03 1 TCONF : ptrace03.c:137: this kernel allows to trace init
ptrace03 2 TPASS : Test Passed
ptrace03 3 TPASS : Test Passed
*** C1357T03 PASSED (2)
*** C1357T04 start *******************************
ptrace04 1 TCONF : ptrace04.c:105: test not supported for your arch (yet)
ptrace04 2 TCONF : ptrace04.c:105: Remaining cases not appropriate for configuration
*** C1357T04 PASSED (0)
*** C1357T05 start *******************************
ptrace05 0 TINFO : [child] Sending kill(.., 0)
ptrace05 1 TPASS : kill(.., 0) exited with 0, as expected.
ptrace05 2 TPASS : Stopped as expected
ptrace05 3 TPASS : Stopped as expected
ptrace05 4 TPASS : Stopped as expected
ptrace05 5 TPASS : Stopped as expected
ptrace05 6 TPASS : Stopped as expected
ptrace05 7 TPASS : Stopped as expected
ptrace05 8 TPASS : Stopped as expected
ptrace05 9 TPASS : Stopped as expected
ptrace05 10 TPASS : Killed with SIGKILL, as expected.
ptrace05 11 TPASS : Stopped as expected
ptrace05 12 TPASS : Stopped as expected
ptrace05 13 TPASS : Stopped as expected
ptrace05 14 TPASS : Stopped as expected
ptrace05 15 TPASS : Stopped as expected
ptrace05 16 TPASS : Stopped as expected
ptrace05 17 TPASS : Stopped as expected
ptrace05 18 TPASS : Stopped as expected
ptrace05 19 TPASS : Stopped as expected
ptrace05 20 TPASS : Stopped as expected
ptrace05 21 TPASS : Stopped as expected
ptrace05 22 TPASS : Stopped as expected
ptrace05 23 TPASS : Stopped as expected
ptrace05 24 TPASS : Stopped as expected
ptrace05 25 TPASS : Stopped as expected
ptrace05 26 TPASS : Stopped as expected
ptrace05 27 TPASS : Stopped as expected
ptrace05 28 TPASS : Stopped as expected
ptrace05 29 TPASS : Stopped as expected
ptrace05 30 TPASS : Stopped as expected
ptrace05 31 TPASS : Stopped as expected
ptrace05 32 TPASS : Stopped as expected
ptrace05 33 TPASS : Stopped as expected
ptrace05 34 TPASS : Stopped as expected
ptrace05 35 TPASS : Stopped as expected
ptrace05 36 TPASS : Stopped as expected
ptrace05 37 TPASS : Stopped as expected
ptrace05 38 TPASS : Stopped as expected
ptrace05 39 TPASS : Stopped as expected
ptrace05 40 TPASS : Stopped as expected
ptrace05 41 TPASS : Stopped as expected
ptrace05 42 TPASS : Stopped as expected
ptrace05 43 TPASS : Stopped as expected
ptrace05 44 TPASS : Stopped as expected
ptrace05 45 TPASS : Stopped as expected
ptrace05 46 TPASS : Stopped as expected
ptrace05 47 TPASS : Stopped as expected
ptrace05 48 TPASS : Stopped as expected
ptrace05 49 TPASS : Stopped as expected
ptrace05 50 TPASS : Stopped as expected
ptrace05 51 TPASS : Stopped as expected
ptrace05 52 TPASS : Stopped as expected
ptrace05 53 TPASS : Stopped as expected
ptrace05 54 TPASS : Stopped as expected
ptrace05 55 TPASS : Stopped as expected
ptrace05 56 TPASS : Stopped as expected
ptrace05 57 TPASS : Stopped as expected
ptrace05 58 TPASS : Stopped as expected
ptrace05 59 TPASS : Stopped as expected
ptrace05 60 TPASS : Stopped as expected
ptrace05 61 TPASS : Stopped as expected
ptrace05 62 TPASS : Stopped as expected
ptrace05 63 TPASS : Stopped as expected
*** C1357T05 PASSED (63)