flush instruction cache at context switch time if necessary

Change-Id: Ic09415ea772a9de6dca43a98168a8346ca86d3e7

arch/arm64/kernel/cpu.c

@@ -1772,4 +1772,9 @@ int smp_call_func(cpu_set_t *__cpu_set, smp_func_t __func, void *__arg)
 	return -1;
 }
 
+void arch_flush_icache_all(void)
+{
+	asm("ic	ialluis");
+	dsb(ish);
+}
 /*** end of file ***/

arch/arm64/kernel/include/arch/cpu.h

@@ -102,4 +102,6 @@ static inline void cpu_disable_nmi(void)
 
 #endif	/* __ASSEMBLY__ */
 
+void arch_flush_icache_all(void);
+
 #endif /* !__HEADER_ARM64_ARCH_CPU_H */

arch/arm64/kernel/memory.c

@@ -3199,6 +3199,7 @@ void load_page_table(struct page_table *pt)
 {
 	if (pt == NULL) {
 		// load page table for idle(EL1) process.
+		switch_mm(init_pt);
 		return;
 	}
 	// load page table for user(EL0) thread.

arch/x86_64/kernel/cpu.c

@@ -1821,6 +1821,10 @@ ihk_mc_init_user_tlsbase(ihk_mc_user_context_t *ctx,
 	do_arch_prctl(ARCH_SET_FS, tls_base_addr);
 }
 
+void arch_flush_icache_all(void)
+{
+	return;
+}
 
 /*@
   @ assigns \nothing;

arch/x86_64/kernel/include/arch/cpu.h

@@ -47,5 +47,6 @@ static inline unsigned long read_tsc(void)
 	WRITE_ONCE(*p, v);					\
 })
 
+void arch_flush_icache_all(void);
 
 #endif /* ARCH_CPU_H */