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Fix ThunderX2 write-combined PTE flag insanity

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Change-Id: I59999a680b556acf3e22ac516f4758e3aee7f355
This commit is contained in:
Balazs Gerofi
2019-01-28 11:06:30 +09:00
committed by Dominique Martinet
parent 649059f2d2
commit 6ed2e5ffc1
4 changed files with 92 additions and 12 deletions
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9
executer/kernel/mcctrl/arch/arm64/archdeps.c
View File

@ -304,12 +304,3 @@ out:
error, rva, rpa, pgsize);
return error;
}
#ifdef POSTK_DEBUG_ARCH_DEP_12
#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC)
static inline bool pte_is_write_combined(pte_t pte)
{
return ((pte_val(pte) & PTE_ATTRINDX_MASK) == PFN_WRITE_COMBINED);
}
#endif /* POSTK_DEBUG_ARCH_DEP_12 */

17
executer/kernel/mcctrl/arch/arm64/include/archdeps.h
View File

@ -10,10 +10,25 @@ extern int translate_rva_to_rpa(ihk_os_t os, unsigned long rpt, unsigned long rv
unsigned long *rpap, unsigned long *pgsizep);
#ifdef POSTK_DEBUG_ARCH_DEP_12
#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC)
#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC)
static inline bool pte_is_write_combined(pte_t pte)
{
#if defined(MIDR_CPU_MODEL_MASK)
/*
* Fix up arm64 braindamage of using NORMAL_NC for write
* combining when Device GRE exists specifically for the
* purpose. Needed on ThunderX2.
*/
switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
#if defined(ARM_CPU_IMP_BRCM) && defined(BRCM_CPU_PART_VULCAN)
case MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN):
#endif
case MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2):
return ((pte_val(pte) & PTE_ATTRINDX_MASK) ==
PTE_ATTRINDX(MT_DEVICE_GRE));
}
#endif
return ((pte_val(pte) & PTE_ATTRINDX_MASK) == PFN_WRITE_COMBINED);
}
#endif /* POSTK_DEBUG_ARCH_DEP_12 */