update PAPI support.
This commit is contained in:
Ken Sato
@ -14,6 +14,7 @@
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#include <registers.h>
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extern unsigned int *x86_march_perfmap;
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static unsigned long pmc_status = 0x0;
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#define X86_CR4_PCE 0x00000100
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@ -33,20 +34,51 @@ static int set_perfctr_x86_direct(int counter, int mode, unsigned int value)
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return -EINVAL;
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}
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if (mode & PERFCTR_USER_MODE) {
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// clear mode flags
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value &= ~(3 << 16);
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// set mode flags
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if(mode & PERFCTR_USER_MODE) {
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value |= 1 << 16;
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}
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if (mode & PERFCTR_KERNEL_MODE) {
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}
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if(mode & PERFCTR_KERNEL_MODE) {
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value |= 1 << 17;
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}
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}
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// wrmsr(MSR_PERF_GLOBAL_CTRL, 0);
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value |= (1 << 22) | (1 << 18); /* EN */
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value |= (1 << 20); /* Enable overflow interrupt */
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wrmsr(MSR_IA32_PERFEVTSEL0 + counter, value);
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kprintf("wrmsr: %d <= %x\n", MSR_PERF_GLOBAL_CTRL, 0);
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//kprintf("wrmsr: %d <= %x\n", MSR_PERF_GLOBAL_CTRL, 0);
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kprintf("wrmsr: %d <= %x\n", MSR_IA32_PERFEVTSEL0 + counter, value);
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return 0;
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}
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static int set_pmc_x86_direct(int counter, unsigned long val)
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{
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unsigned long cnt_bit = 0;
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if (counter < 0) {
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return -EINVAL;
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}
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cnt_bit = 1UL << counter;
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if ( cnt_bit & X86_IA32_PERF_COUNTERS_MASK ) {
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// set generic pmc
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wrmsr(MSR_IA32_PMC0 + counter, val);
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}
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else if ( cnt_bit & X86_IA32_FIXED_PERF_COUNTERS_MASK ) {
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// set fixed pmc
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wrmsr(MSR_IA32_FIXED_CTR0 + counter - X86_IA32_BASE_FIXED_PERF_COUNTERS, val);
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}
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else {
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return -EINVAL;
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}
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return 0;
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}
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@ -57,6 +89,37 @@ static int set_perfctr_x86(int counter, int event, int mask, int inv, int count,
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CVAL2(event, mask, inv, count));
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}
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static int set_fixed_counter(int counter, int mode)
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{
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unsigned long value = 0;
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unsigned int ctr_mask = 0x7;
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int counter_idx = counter - X86_IA32_BASE_FIXED_PERF_COUNTERS ;
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unsigned int set_val = 0;
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if (counter_idx < 0 || counter_idx >= X86_IA32_NUM_FIXED_PERF_COUNTERS) {
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return -EINVAL;
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}
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// clear specified fixed counter info
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value = rdmsr(MSR_PERF_FIXED_CTRL);
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ctr_mask <<= counter_idx * 4;
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value &= ~ctr_mask;
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if (mode & PERFCTR_USER_MODE) {
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set_val |= 1 << 1;
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}
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if (mode & PERFCTR_KERNEL_MODE) {
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set_val |= 1;
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}
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set_val <<= counter_idx * 4;
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value |= set_val;
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wrmsr(MSR_PERF_FIXED_CTRL, value);
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return 0;
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}
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int ihk_mc_perfctr_init_raw(int counter, unsigned int code, int mode)
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{
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if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
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@ -86,14 +149,15 @@ extern void x86_march_perfctr_start(unsigned long counter_mask);
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int ihk_mc_perfctr_start(unsigned long counter_mask)
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{
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unsigned int value = 0;
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unsigned long value = 0;
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unsigned long mask = X86_IA32_PERF_COUNTERS_MASK | X86_IA32_FIXED_PERF_COUNTERS_MASK;
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#ifdef HAVE_MARCH_PERFCTR_START
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x86_march_perfctr_start(counter_mask);
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#endif
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counter_mask &= ((1 << X86_IA32_NUM_PERF_COUNTERS) - 1);
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counter_mask &= mask;
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value = rdmsr(MSR_PERF_GLOBAL_CTRL);
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value |= counter_mask;
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value |= counter_mask;
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wrmsr(MSR_PERF_GLOBAL_CTRL, value);
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return 0;
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@ -101,9 +165,10 @@ int ihk_mc_perfctr_start(unsigned long counter_mask)
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int ihk_mc_perfctr_stop(unsigned long counter_mask)
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{
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unsigned int value;
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unsigned long value;
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unsigned long mask = X86_IA32_PERF_COUNTERS_MASK | X86_IA32_FIXED_PERF_COUNTERS_MASK;
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counter_mask &= ((1 << X86_IA32_NUM_PERF_COUNTERS) - 1);
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counter_mask &= mask;
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value = rdmsr(MSR_PERF_GLOBAL_CTRL);
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value &= ~counter_mask;
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wrmsr(MSR_PERF_GLOBAL_CTRL, value);
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@ -111,17 +176,48 @@ int ihk_mc_perfctr_stop(unsigned long counter_mask)
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return 0;
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}
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int ihk_mc_perfctr_reset(int counter)
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// init for fixed counter
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int ihk_mc_perfctr_fixed_init(int counter, int mode)
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{
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if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
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unsigned long value = 0;
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unsigned int ctr_mask = 0x7;
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int counter_idx = counter - X86_IA32_BASE_FIXED_PERF_COUNTERS ;
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unsigned int set_val = 0;
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if (counter_idx < 0 || counter_idx >= X86_IA32_NUM_FIXED_PERF_COUNTERS) {
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return -EINVAL;
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}
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wrmsr(MSR_IA32_PMC0 + counter, 0);
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// clear specified fixed counter info
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value = rdmsr(MSR_PERF_FIXED_CTRL);
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ctr_mask <<= counter_idx * 4;
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value &= ~ctr_mask;
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if (mode & PERFCTR_USER_MODE) {
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set_val |= 1 << 1;
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}
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if (mode & PERFCTR_KERNEL_MODE) {
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set_val |= 1;
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}
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set_val <<= counter_idx * 4;
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value |= set_val;
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wrmsr(MSR_PERF_FIXED_CTRL, value);
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return 0;
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}
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int ihk_mc_perfctr_reset(int counter)
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{
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return set_pmc_x86_direct(counter, 0);
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}
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int ihk_mc_perfctr_set(int counter, unsigned long val)
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{
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return set_pmc_x86_direct(counter, val);
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}
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int ihk_mc_perfctr_read_mask(unsigned long counter_mask, unsigned long *value)
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{
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int i, j;
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@ -137,10 +233,89 @@ int ihk_mc_perfctr_read_mask(unsigned long counter_mask, unsigned long *value)
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unsigned long ihk_mc_perfctr_read(int counter)
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{
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if (counter < 0 || counter >= X86_IA32_NUM_PERF_COUNTERS) {
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unsigned long retval = 0;
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unsigned long cnt_bit = 0;
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if (counter < 0) {
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return -EINVAL;
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}
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return rdpmc(counter);
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cnt_bit = 1UL << counter;
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if ( cnt_bit & X86_IA32_PERF_COUNTERS_MASK ) {
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// read generic pmc
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retval = rdpmc(counter);
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}
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else if ( cnt_bit & X86_IA32_FIXED_PERF_COUNTERS_MASK ) {
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// read fixed pmc
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retval = rdpmc((1 << 30) + (counter - X86_IA32_BASE_FIXED_PERF_COUNTERS));
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}
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else {
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retval = -EINVAL;
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}
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return retval;
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}
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// read by rdmsr
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unsigned long ihk_mc_perfctr_read_msr(int counter)
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{
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unsigned int idx = 0;
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unsigned long retval = 0;
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unsigned long cnt_bit = 0;
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if (counter < 0) {
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return -EINVAL;
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}
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cnt_bit = 1UL << counter;
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if ( cnt_bit & X86_IA32_PERF_COUNTERS_MASK ) {
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// read generic pmc
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idx = MSR_IA32_PMC0 + counter;
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retval = (unsigned long) rdmsr(idx);
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}
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else if ( cnt_bit & X86_IA32_FIXED_PERF_COUNTERS_MASK ) {
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// read fixed pmc
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idx = MSR_IA32_FIXED_CTR0 + counter;
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retval = (unsigned long) rdmsr(idx);
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}
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else {
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retval = -EINVAL;
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}
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return retval;
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}
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int ihk_mc_perfctr_alloc_counter()
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{
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int i = 0;
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int ret = -1;
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// find avail generic counter
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for(i = 0; i < X86_IA32_NUM_PERF_COUNTERS; i++) {
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if(!(pmc_status & (1 << i))) {
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ret = i;
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pmc_status |= (1 << i);
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break;
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}
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}
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if(ret < 0){
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return ret;
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}
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return ret;
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}
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void ihk_mc_perfctr_release_counter(int counter)
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{
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unsigned long value = 0;
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value = rdmsr(MSR_PERF_GLOBAL_CTRL);
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value &= ~(1UL << counter);
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pmc_status &= ~(1UL << counter);
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wrmsr(MSR_PERF_GLOBAL_CTRL, 0);
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}
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