test: perf_event: add log of ThunderX2 machine (apollo)

Change-Id: I27aa1e30abdf4ed640a80b4016bcf108262ce9e3

test/perf_event/result_apollo.log

@@ -0,0 +1,171 @@
+=========================
+aarch64
+=========================
+
+apollo
+----------------
+$ sh go_perf_test.sh
+mcstop+release.sh ... done
+mcreboot.sh -c 8-55 -m 4096M -q 60 ... done
+[PERF_TYPE_HARDWARE all space]
+CPU_CYCLES             : 207857323
+INSTRUCTIONS           : 303335083
+CACHE_REFERENCES       : 115303907
+CACHE_MISSES           : 2004054
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 3648
+BUS_CYCLES             : 0
+STALLED_CYCLES_FRONTEND: 287002
+STALLED_CYCLES_BACKEND : 60981248
+REF_CPU_CYCLES         : -1
+[HW_CACHE no exclude]
+L1D _OP_READ    _ACCESS: 115303282
+L1D _OP_READ    _MISS  : 2004061
+L1D _OP_WRITE   _ACCESS: 115304087
+L1D _OP_WRITE   _MISS  : 2004036
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 75853278
+L1I _OP_READ    _MISS  : 442
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: 85882503
+DTLB_OP_READ    _MISS  : 44
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: 75897737
+ITLB_OP_READ    _MISS  : 16
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 38712401
+BPU _OP_READ    _MISS  : 3293
+BPU _OP_WRITE   _ACCESS: 38712143
+BPU _OP_WRITE   _MISS  : 3289
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude user space]
+CPU_CYCLES             : 201548255
+INSTRUCTIONS           : 2273169
+CACHE_REFERENCES       : 62893
+CACHE_MISSES           : 403
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 84
+BUS_CYCLES             : 0
+STALLED_CYCLES_FRONTEND: 97163
+STALLED_CYCLES_BACKEND : 3205813
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude user space]
+L1D _OP_READ    _ACCESS: 61400
+L1D _OP_READ    _MISS  : 402
+L1D _OP_WRITE   _ACCESS: 61527
+L1D _OP_WRITE   _MISS  : 402
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 614769
+L1I _OP_READ    _MISS  : 348
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: 573586
+DTLB_OP_READ    _MISS  : 22
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: 633350
+ITLB_OP_READ    _MISS  : 7
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 577839
+BPU _OP_READ    _MISS  : 87
+BPU _OP_WRITE   _ACCESS: 578121
+BPU _OP_WRITE   _MISS  : 91
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1
+[HARDWARE exclude kernel space]
+CPU_CYCLES             : 201493602
+INSTRUCTIONS           : 301061158
+CACHE_REFERENCES       : 115239019
+CACHE_MISSES           : 2003646
+BRANCH_INSTRUCTIONS    : -1
+BRANCH_MISSES          : 3148
+BUS_CYCLES             : 0
+STALLED_CYCLES_FRONTEND: 179232
+STALLED_CYCLES_BACKEND : 57792516
+REF_CPU_CYCLES         : -1
+[HW_CACHE exclude kernel space]
+L1D _OP_READ    _ACCESS: 115244922
+L1D _OP_READ    _MISS  : 2003646
+L1D _OP_WRITE   _ACCESS: 115241293
+L1D _OP_WRITE   _MISS  : 2003645
+L1D _OP_PREFETCH_ACCESS: -1
+L1D _OP_PREFETCH_MISS  : -1
+L1I _OP_READ    _ACCESS: 75231894
+L1I _OP_READ    _MISS  : 106
+L1I _OP_WRITE   _ACCESS: -1
+L1I _OP_WRITE   _MISS  : -1
+L1I _OP_PREFETCH_ACCESS: -1
+L1I _OP_PREFETCH_MISS  : -1
+LL  _OP_READ    _ACCESS: -1
+LL  _OP_READ    _MISS  : -1
+LL  _OP_WRITE   _ACCESS: -1
+LL  _OP_WRITE   _MISS  : -1
+LL  _OP_PREFETCH_ACCESS: -1
+LL  _OP_PREFETCH_MISS  : -1
+DTLB_OP_READ    _ACCESS: 85310865
+DTLB_OP_READ    _MISS  : 28
+DTLB_OP_WRITE   _ACCESS: -1
+DTLB_OP_WRITE   _MISS  : -1
+DTLB_OP_PREFETCH_ACCESS: -1
+DTLB_OP_PREFETCH_MISS  : -1
+ITLB_OP_READ    _ACCESS: 75263501
+ITLB_OP_READ    _MISS  : 8
+ITLB_OP_WRITE   _ACCESS: -1
+ITLB_OP_WRITE   _MISS  : -1
+ITLB_OP_PREFETCH_ACCESS: -1
+ITLB_OP_PREFETCH_MISS  : -1
+BPU _OP_READ    _ACCESS: 38134160
+BPU _OP_READ    _MISS  : 3193
+BPU _OP_WRITE   _ACCESS: 38135039
+BPU _OP_WRITE   _MISS  : 3119
+BPU _OP_PREFETCH_ACCESS: -1
+BPU _OP_PREFETCH_MISS  : -1
+NODE_OP_READ    _ACCESS: -1
+NODE_OP_READ    _MISS  : -1
+NODE_OP_WRITE   _ACCESS: -1
+NODE_OP_WRITE   _MISS  : -1
+NODE_OP_PREFETCH_ACCESS: -1
+NODE_OP_PREFETCH_MISS  : -1