add arm64 support
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
This commit is contained in:
Takayuki Okamoto
558
arch/arm64/kernel/entry.S
Normal file
558
arch/arm64/kernel/entry.S
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@ -0,0 +1,558 @@
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/* entry.S COPYRIGHT FUJITSU LIMITED 2015-2017 */
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#include <linkage.h>
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#include <assembler.h>
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#include <asm-offsets.h>
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#include <esr.h>
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#include <thread_info.h>
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/*
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* Bad Abort numbers
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*-----------------
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*/
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#define BAD_SYNC 0
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#define BAD_IRQ 1
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#define BAD_FIQ 2
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#define BAD_ERROR 3
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.macro kernel_entry, el, regsize = 64
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sub sp, sp, #S_FRAME_SIZE
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.if \regsize == 32
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mov w0, w0 // zero upper 32 bits of x0
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.endif
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stp x0, x1, [sp, #16 * 0]
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stp x2, x3, [sp, #16 * 1]
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stp x4, x5, [sp, #16 * 2]
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stp x6, x7, [sp, #16 * 3]
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stp x8, x9, [sp, #16 * 4]
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stp x10, x11, [sp, #16 * 5]
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stp x12, x13, [sp, #16 * 6]
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stp x14, x15, [sp, #16 * 7]
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stp x16, x17, [sp, #16 * 8]
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stp x18, x19, [sp, #16 * 9]
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stp x20, x21, [sp, #16 * 10]
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stp x22, x23, [sp, #16 * 11]
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stp x24, x25, [sp, #16 * 12]
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stp x26, x27, [sp, #16 * 13]
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stp x28, x29, [sp, #16 * 14]
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.if \el == 0
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mrs x21, sp_el0
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get_thread_info tsk // Ensure MDSCR_EL1.SS is clear,
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ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
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disable_step_tsk x19, x20 // exceptions when scheduling.
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.else
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add x21, sp, #S_FRAME_SIZE
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.endif
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mrs x22, elr_el1
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mrs x23, spsr_el1
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#if defined(CONFIG_HAS_NMI)
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mrs_s x20, ICC_PMR_EL1 // Get PMR
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and x20, x20, #ICC_PMR_EL1_G_BIT // Extract mask bit
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lsl x20, x20, #PSR_G_PMR_G_SHIFT // Shift to a PSTATE RES0 bit
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eor x20, x20, #PSR_G_BIT // Invert bit
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orr x23, x20, x23 // Store PMR within PSTATE
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mov x20, #ICC_PMR_EL1_MASKED
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msr_s ICC_PMR_EL1, x20 // Mask normal interrupts at PMR
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#endif /* defined(CONFIG_HAS_NMI) */
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stp lr, x21, [sp, #S_LR]
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stp x22, x23, [sp, #S_PC]
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/*
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* Set syscallno to -1 by default (overridden later if real syscall).
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*/
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.if \el == 0
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mvn x21, xzr
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str x21, [sp, #S_SYSCALLNO]
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.endif
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/*
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* Registers that may be useful after this macro is invoked:
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*
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* x21 - aborted SP
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* x22 - aborted PC
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* x23 - aborted PSTATE
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*/
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.endm
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.macro kernel_exit, el, need_enable_step = 0
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.if \el == 0
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mov x0, #0
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mov x1, sp
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mov x2, #0
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bl check_signal // check whether the signal is delivered
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bl check_need_resched // or reschedule is needed.
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mov x0, #0
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mov x1, sp
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mov x2, #0
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bl check_signal_irq_disabled // check whether the signal is delivered(for kernel_exit)
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.endif
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disable_irq x1 // disable interrupts
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.if \need_enable_step == 1
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ldr x1, [tsk, #TI_FLAGS]
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enable_step_tsk x1, x2
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.endif
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disable_nmi
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ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
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.if \el == 0
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// ct_user_enter // McKernel, disable (debugcode?)
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ldr x23, [sp, #S_SP] // load return stack pointer
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msr sp_el0, x23
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.endif
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#if defined(CONFIG_HAS_NMI)
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and x20, x22, #PSR_G_BIT // Get stolen PSTATE bit
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and x22, x22, #~PSR_G_BIT // Clear stolen bit
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lsr x20, x20, #PSR_G_PMR_G_SHIFT // Shift back to PMR mask
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eor x20, x20, #ICC_PMR_EL1_UNMASKED // x20 gets 0xf0 or 0xb0
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msr_s ICC_PMR_EL1, x20 // Write to PMR
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#endif /* defined(CONFIG_HAS_NMI) */
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msr elr_el1, x21 // set up the return data
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msr spsr_el1, x22
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ldp x0, x1, [sp, #16 * 0]
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ldp x2, x3, [sp, #16 * 1]
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ldp x4, x5, [sp, #16 * 2]
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ldp x6, x7, [sp, #16 * 3]
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ldp x8, x9, [sp, #16 * 4]
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ldp x10, x11, [sp, #16 * 5]
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ldp x12, x13, [sp, #16 * 6]
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ldp x14, x15, [sp, #16 * 7]
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ldp x16, x17, [sp, #16 * 8]
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ldp x18, x19, [sp, #16 * 9]
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ldp x20, x21, [sp, #16 * 10]
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ldp x22, x23, [sp, #16 * 11]
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ldp x24, x25, [sp, #16 * 12]
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ldp x26, x27, [sp, #16 * 13]
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ldp x28, x29, [sp, #16 * 14]
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ldr lr, [sp, #S_LR]
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add sp, sp, #S_FRAME_SIZE // restore sp
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eret // return to kernel
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.endm
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.macro get_thread_info, rd
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mov \rd, sp
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and \rd, \rd, #~(KERNEL_STACK_SIZE - 1) // top of stack
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.endm
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - x0 to x6.
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*
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* x7 is reserved for the system call number in 32-bit mode.
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*/
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sc_nr .req x25 // number of system calls
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scno .req x26 // syscall number
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stbl .req x27 // syscall table pointer
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tsk .req x28 // current thread_info
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/*
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* Interrupt handling.
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*/
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.macro irq_handler
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adrp x1, handle_arch_irq
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ldr x1, [x1, #:lo12:handle_arch_irq]
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mov x0, sp
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blr x1
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.endm
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.text
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/*
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* Exception vectors.
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*/
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.align 11
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ENTRY(vectors)
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ventry el1_sync_invalid // Synchronous EL1t
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ventry el1_irq_invalid // IRQ EL1t
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ventry el1_fiq_invalid // FIQ EL1t
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ventry el1_error_invalid // Error EL1t
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ventry el1_sync // Synchronous EL1h
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ventry el1_irq // IRQ EL1h
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ventry el1_fiq_invalid // FIQ EL1h
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ventry el1_error_invalid // Error EL1h
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ventry el0_sync // Synchronous 64-bit EL0
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ventry el0_irq // IRQ 64-bit EL0
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ventry el0_fiq_invalid // FIQ 64-bit EL0
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ventry el0_error_invalid // Error 64-bit EL0
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ventry el0_sync_invalid // Synchronous 32-bit EL0
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ventry el0_irq_invalid // IRQ 32-bit EL0
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ventry el0_fiq_invalid // FIQ 32-bit EL0
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ventry el0_error_invalid // Error 32-bit EL0
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END(vectors)
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/*
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* Invalid mode handlers
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*/
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.macro inv_entry, el, reason, regsize = 64
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kernel_entry el, \regsize
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mov x0, sp
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mov x1, #\reason
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mrs x2, esr_el1
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enable_nmi
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.if \el == 0
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bl bad_mode
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b ret_to_user
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.else
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b bad_mode
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.endif
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.endm
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el0_sync_invalid:
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inv_entry 0, BAD_SYNC
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ENDPROC(el0_sync_invalid)
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el0_irq_invalid:
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inv_entry 0, BAD_IRQ
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ENDPROC(el0_irq_invalid)
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el0_fiq_invalid:
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inv_entry 0, BAD_FIQ
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ENDPROC(el0_fiq_invalid)
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el0_error_invalid:
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inv_entry 0, BAD_ERROR
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ENDPROC(el0_error_invalid)
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el1_sync_invalid:
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inv_entry 1, BAD_SYNC
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ENDPROC(el1_sync_invalid)
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el1_irq_invalid:
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inv_entry 1, BAD_IRQ
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ENDPROC(el1_irq_invalid)
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el1_fiq_invalid:
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inv_entry 1, BAD_FIQ
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ENDPROC(el1_fiq_invalid)
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el1_error_invalid:
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inv_entry 1, BAD_ERROR
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ENDPROC(el1_error_invalid)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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el1_sync:
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kernel_entry 1
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mrs x1, esr_el1 // read the syndrome register
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lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
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cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
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b.eq el1_da
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// cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
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// b.eq el1_ia
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cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
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b.eq el1_undef
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cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
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b.eq el1_undef
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// cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
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// b.ge el1_dbg
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b el1_inv
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el1_ia:
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/*
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* Fall through to the Data abort case
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*/
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el1_da:
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/*
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* Data abort handling
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*/
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mrs x0, far_el1
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enable_nmi
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enable_dbg
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#if defined(CONFIG_HAS_NMI)
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# define PSR_INTR_SHIFT PSR_G_SHIFT // PSR_G_BIT
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#else /* defined(CONFIG_HAS_NMI) */
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# define PSR_INTR_SHIFT 7 // PSR_I_BIT
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#endif /* defined(CONFIG_HAS_NMI) */
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// re-enable interrupts if they were enabled in the aborted context
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tbnz x23, #PSR_INTR_SHIFT, 1f
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enable_irq x2
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1:
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mov x2, sp // struct pt_regs
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bl do_mem_abort
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// disable interrupts before pulling preserved data off the stack
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kernel_exit 1
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el1_sp_pc:
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/*
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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enable_nmi
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enable_dbg
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mov x2, sp
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b do_sp_pc_abort
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el1_undef:
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/*
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* Undefined instruction
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*/
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enable_nmi
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enable_dbg
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mov x0, sp
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b do_undefinstr
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// el1_dbg:
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// /*
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// * Debug exception handling
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// */
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// cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
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// cinc x24, x24, eq // set bit '0'
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// tbz x24, #0, el1_inv // EL1 only
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// mrs x0, far_el1
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// mov x2, sp // struct pt_regs
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// bl do_debug_exception
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// kernel_exit 1
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el1_inv:
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// TODO: add support for undefined instructions in kernel mode
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mov x0, sp
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mov x1, #BAD_SYNC
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mrs x2, esr_el1
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enable_nmi
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enable_dbg
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b bad_mode
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ENDPROC(el1_sync)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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el1_irq:
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kernel_entry 1
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enable_dbg
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irq_handler
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kernel_exit 1
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ENDPROC(el1_irq)
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/*
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* EL0 mode handlers.
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*/
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.align 6
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el0_sync:
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kernel_entry 0
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mrs x25, esr_el1 // read the syndrome register
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lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
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cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
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b.eq el0_svc
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cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
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b.eq el0_da
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cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
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b.eq el0_ia
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cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
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b.eq el0_fpsimd_acc
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#ifdef CONFIG_ARM64_SVE
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cmp x24, #ESR_ELx_EC_SVE // SVE access
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b.eq el0_sve_acc
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#endif
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cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
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b.eq el0_fpsimd_exc
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cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
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b.eq el0_undef
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cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
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b.eq el0_sp_pc
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cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
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b.eq el0_sp_pc
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cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
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b.eq el0_undef
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cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
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b.ge el0_dbg
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b el0_inv
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el0_svc:
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uxtw scno, w8 // syscall number in w8
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stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
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enable_nmi
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enable_dbg_and_irq x0
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adrp x16, __arm64_syscall_handler
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ldr x16, [x16, #:lo12:__arm64_syscall_handler]
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mov x0, scno
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mov x1, sp
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blr x16 // __arm64_syscall_handler(int, syscall_num, ihk_mc_user_context_t *uctx);
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/* Signal check has been completed at the stage of came back. */
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b ret_fast_syscall
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el0_da:
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/*
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* Data abort handling
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*/
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mrs x26, far_el1
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// enable interrupts before calling the main handler
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enable_nmi
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enable_dbg_and_irq x0
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// ct_user_exit
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bic x0, x26, #(0xff << 56)
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mov x1, x25
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mov x2, sp
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bl do_mem_abort
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b ret_to_user
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el0_ia:
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/*
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* Instruction abort handling
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*/
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mrs x26, far_el1
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// enable interrupts before calling the main handler
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enable_nmi
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enable_dbg_and_irq x0
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// ct_user_exit
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mov x0, x26
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mov x1, x25
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mov x2, sp
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bl do_mem_abort
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b ret_to_user
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el0_fpsimd_acc:
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/*
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* Floating Point or Advanced SIMD access
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*/
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enable_nmi
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enable_dbg
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// ct_user_exit
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mov x0, x25
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mov x1, sp
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bl do_fpsimd_acc
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b ret_to_user
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#ifdef CONFIG_ARM64_SVE
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/*
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* Scalable Vector Extension access
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*/
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el0_sve_acc:
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enable_nmi
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enable_dbg
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// ct_user_exit
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mov x0, x25
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mov x1, sp
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bl do_sve_acc
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b ret_to_user
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#endif
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el0_fpsimd_exc:
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/*
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* Floating Point, Advanced SIMD or SVE exception
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*/
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enable_nmi
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enable_dbg
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// ct_user_exit
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mov x0, x25
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mov x1, sp
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bl do_fpsimd_exc
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b ret_to_user
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el0_sp_pc:
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/*
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* Stack or PC alignment exception handling
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*/
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mrs x26, far_el1
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// enable interrupts before calling the main handler
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enable_nmi
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enable_dbg_and_irq x0
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mov x0, x26
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mov x1, x25
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mov x2, sp
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bl do_sp_pc_abort
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b ret_to_user
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el0_undef:
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/*
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* Undefined instruction
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*/
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// enable interrupts before calling the main handler
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enable_nmi
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enable_dbg_and_irq x0
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// ct_user_exit
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mov x0, sp
|
||||
bl do_undefinstr
|
||||
b ret_to_user
|
||||
el0_dbg:
|
||||
/*
|
||||
* Debug exception handling
|
||||
*/
|
||||
tbnz x24, #0, el0_inv // EL0 only
|
||||
mrs x0, far_el1
|
||||
mov x1, x25
|
||||
mov x2, sp
|
||||
enable_nmi
|
||||
bl do_debug_exception
|
||||
enable_dbg
|
||||
// ct_user_exit
|
||||
b ret_to_user
|
||||
el0_inv:
|
||||
enable_dbg
|
||||
mov x0, sp
|
||||
mov x1, #BAD_SYNC
|
||||
mrs x2, esr_el1
|
||||
enable_nmi
|
||||
bl bad_mode
|
||||
b ret_to_user
|
||||
ENDPROC(el0_sync)
|
||||
.align 6
|
||||
el0_irq:
|
||||
kernel_entry 0
|
||||
enable_dbg
|
||||
irq_handler
|
||||
b ret_to_user
|
||||
ENDPROC(el0_irq)
|
||||
|
||||
/*
|
||||
* Register switch for AArch64. The callee-saved registers need to be saved
|
||||
* and restored. On entry:
|
||||
* x0 = previous task_struct (must be preserved across the switch)
|
||||
* x1 = next task_struct
|
||||
* Previous and next are guaranteed not to be the same.
|
||||
*
|
||||
*/
|
||||
ENTRY(cpu_switch_to)
|
||||
cmp x0, xzr // for idle process branch(skip save)
|
||||
b.eq 1f
|
||||
add x8, x0, #TI_CPU_CONTEXT
|
||||
mov x9, sp
|
||||
stp x19, x20, [x8], #16 // store callee-saved registers
|
||||
stp x21, x22, [x8], #16
|
||||
stp x23, x24, [x8], #16
|
||||
stp x25, x26, [x8], #16
|
||||
stp x27, x28, [x8], #16
|
||||
stp x29, x9, [x8], #16
|
||||
str lr, [x8]
|
||||
1: add x8, x1, #TI_CPU_CONTEXT
|
||||
ldp x19, x20, [x8], #16 // restore callee-saved registers
|
||||
ldp x21, x22, [x8], #16
|
||||
ldp x23, x24, [x8], #16
|
||||
ldp x25, x26, [x8], #16
|
||||
ldp x27, x28, [x8], #16
|
||||
ldp x29, x9, [x8], #16
|
||||
ldr lr, [x8]
|
||||
mov sp, x9
|
||||
mov x0, x2 // return void *prev
|
||||
ret
|
||||
ENDPROC(cpu_switch_to)
|
||||
|
||||
|
||||
ret_fast_syscall:
|
||||
kernel_exit 0, 1
|
||||
ENDPROC(ret_fast_syscall)
|
||||
|
||||
/*
|
||||
* "slow" syscall return path.
|
||||
*/
|
||||
ret_to_user:
|
||||
no_work_pending:
|
||||
kernel_exit 0, 1
|
||||
ENDPROC(ret_to_user)
|
||||
|
||||
/*
|
||||
* This is how we return from a fork.
|
||||
*/
|
||||
ENTRY(ret_from_fork)
|
||||
// bl schedule_tail
|
||||
cbz x19, 1f // not a kernel thread
|
||||
mov x0, x20
|
||||
blr x19
|
||||
1: get_thread_info tsk
|
||||
bl release_runq_lock
|
||||
b ret_to_user
|
||||
ENDPROC(ret_from_fork)
|
||||
|
||||
/* TODO: skeleton for rusage */
|
||||
ENTRY(__freeze)
|
||||
ENDPROC(__freeze)
|
||||
Reference in New Issue
Block a user