Following arm64-support to development branch
This includes the following fixes: * fix build of arch/arm64/kernel/vdso Change-Id: I73b05034d29f7f8731ac17f9736edbba4fb2c639
This commit is contained in:
Takehiro Shiratori
committed by
Dominique Martinet
Dominique Martinet
parent
e52d748744
commit
d4d78e9c61
@ -1,4 +1,4 @@
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/* cpu.c COPYRIGHT FUJITSU LIMITED 2015-2017 */
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/* cpu.c COPYRIGHT FUJITSU LIMITED 2015-2018 */
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#include <ihk/cpu.h>
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#include <ihk/debug.h>
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#include <ihk/mm.h>
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@ -32,6 +32,7 @@
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#include <cpufeature.h>
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#include <debug.h>
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#include <hwcap.h>
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#include <virt.h>
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//#define DEBUG_PRINT_CPU
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@ -43,7 +44,6 @@
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#endif
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struct cpuinfo_arm64 cpuinfo_data[NR_CPUS]; /* index is logical cpuid */
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static unsigned int per_cpu_timer_val[NR_CPUS] = { 0 };
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static struct list_head handlers[1024];
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static void cpu_init_interrupt_handler(void);
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@ -114,137 +114,54 @@ static struct ihk_mc_interrupt_handler cpu_stop_handler = {
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.priv = NULL,
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};
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/* @ref.impl include/clocksource/arm_arch_timer.h */
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
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#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
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static void physical_timer_handler(void *priv)
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extern long freeze_thaw(void *nmi_ctx);
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static void multi_nm_interrupt_handler(void *priv)
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{
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unsigned int ctrl = 0;
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int cpu = ihk_mc_get_processor_id();
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dkprintf("CPU%d: catch physical timer\n", cpu);
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asm volatile("mrs %0, cntp_ctl_el0" : "=r" (ctrl));
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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unsigned int zero = 0;
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unsigned int val = ctrl;
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unsigned int clocks = per_cpu_timer_val[cpu];
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unsigned long irqstate;
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struct cpu_local_var *v = get_this_cpu_local_var();
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/* set resched flag */
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irqstate = ihk_mc_spinlock_lock(&v->runq_lock);
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v->flags |= CPU_FLAG_NEED_RESCHED;
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ihk_mc_spinlock_unlock(&v->runq_lock, irqstate);
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/* gen control register value */
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val &= ~(ARCH_TIMER_CTRL_IT_STAT | ARCH_TIMER_CTRL_IT_MASK);
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val |= ARCH_TIMER_CTRL_ENABLE;
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/* set timer re-enable for periodic */
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (zero));
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asm volatile("msr cntp_tval_el0, %0" : : "r" (clocks));
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
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}
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}
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static struct ihk_mc_interrupt_handler phys_timer_handler = {
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.func = physical_timer_handler,
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.priv = NULL,
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};
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static void virtual_timer_handler(void *priv)
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{
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unsigned int ctrl = 0;
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int cpu = ihk_mc_get_processor_id();
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dkprintf("CPU%d: catch virtual timer\n", cpu);
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asm volatile("mrs %0, cntv_ctl_el0" : "=r" (ctrl));
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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unsigned int zero = 0;
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unsigned int val = ctrl;
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unsigned int clocks = per_cpu_timer_val[cpu];
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unsigned long irqstate;
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struct cpu_local_var *v = get_this_cpu_local_var();
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/* set resched flag */
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irqstate = ihk_mc_spinlock_lock(&v->runq_lock);
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v->flags |= CPU_FLAG_NEED_RESCHED;
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ihk_mc_spinlock_unlock(&v->runq_lock, irqstate);
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/* gen control register value */
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val &= ~(ARCH_TIMER_CTRL_IT_STAT | ARCH_TIMER_CTRL_IT_MASK);
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val |= ARCH_TIMER_CTRL_ENABLE;
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/* set timer re-enable for periodic */
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asm volatile("msr cntv_ctl_el0, %0" : : "r" (zero));
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asm volatile("msr cntv_tval_el0, %0" : : "r" (clocks));
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asm volatile("msr cntv_ctl_el0, %0" : : "r" (val));
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}
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}
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static struct ihk_mc_interrupt_handler virt_timer_handler = {
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.func = virtual_timer_handler,
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.priv = NULL,
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};
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static void memdump_interrupt_handler(void *priv)
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{
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struct pt_regs *regs;
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extern int nmi_mode;
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struct pt_regs *regs = (struct pt_regs *)priv;
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union arm64_cpu_local_variables *clv;
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regs = cpu_local_var(current)->uctx;
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clv = get_arm64_this_cpu_local();
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switch (nmi_mode) {
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case 1:
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case 2:
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/* mode == 1or2, for FREEZER NMI */
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dkprintf("%s: freeze mode NMI catch. (nmi_mode=%d)\n",
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__func__, nmi_mode);
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freeze_thaw(NULL);
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break;
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if (regs && interrupt_from_user(regs)) {
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memcpy(clv->arm64_cpu_local_thread.panic_regs, regs->regs, sizeof(regs->regs));
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clv->arm64_cpu_local_thread.panic_regs[31] = regs->sp;
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clv->arm64_cpu_local_thread.panic_regs[32] = regs->pc;
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clv->arm64_cpu_local_thread.panic_regs[33] = regs->pstate;
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}
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else {
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asm volatile (
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"stp x0, x1, [%3, #16 * 0]\n"
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"stp x2, x3, [%3, #16 * 1]\n"
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"stp x4, x5, [%3, #16 * 2]\n"
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"stp x6, x7, [%3, #16 * 3]\n"
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"stp x8, x9, [%3, #16 * 4]\n"
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"stp x10, x11, [%3, #16 * 5]\n"
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"stp x12, x13, [%3, #16 * 6]\n"
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"stp x14, x15, [%3, #16 * 7]\n"
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"stp x16, x17, [%3, #16 * 8]\n"
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"stp x18, x19, [%3, #16 * 9]\n"
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"stp x20, x21, [%3, #16 * 10]\n"
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"stp x22, x23, [%3, #16 * 11]\n"
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"stp x24, x25, [%3, #16 * 12]\n"
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"stp x26, x27, [%3, #16 * 13]\n"
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"stp x28, x29, [%3, #16 * 14]\n"
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"str x30, [%3, #16 * 15]\n"
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"mov %0, sp\n"
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"adr %1, 1f\n"
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"mrs %2, spsr_el1\n"
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"1:"
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: "=r" (clv->arm64_cpu_local_thread.panic_regs[31]), /* sp */
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"=r" (clv->arm64_cpu_local_thread.panic_regs[32]), /* pc */
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"=r" (clv->arm64_cpu_local_thread.panic_regs[33]) /* spsr_el1 */
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: "r" (&clv->arm64_cpu_local_thread.panic_regs)
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: "memory"
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);
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}
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case 0:
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/* mode == 0, for MEMDUMP NMI */
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clv = get_arm64_this_cpu_local();
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clv->arm64_cpu_local_thread.paniced = 1;
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if (regs) {
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memcpy(clv->arm64_cpu_local_thread.panic_regs,
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regs->regs, sizeof(regs->regs));
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clv->arm64_cpu_local_thread.panic_regs[31] = regs->sp;
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clv->arm64_cpu_local_thread.panic_regs[32] = regs->pc;
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clv->arm64_cpu_local_thread.panic_regs[33] =
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regs->pstate;
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}
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clv->arm64_cpu_local_thread.paniced = 1;
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ihk_mc_query_mem_areas();
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/* memdump-nmi is halted McKernel, break is unnecessary. */
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/* fall through */
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case 3:
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/* mode == 3, for SHUTDOWN-WAIT NMI */
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while (1) {
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cpu_halt();
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}
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break;
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while(1)
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{
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cpu_halt();
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default:
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ekprintf("%s: Unknown nmi-mode(%d) detected.\n",
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__func__, nmi_mode);
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break;
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}
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}
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static struct ihk_mc_interrupt_handler memdump_handler = {
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.func = memdump_interrupt_handler,
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static struct ihk_mc_interrupt_handler multi_nmi_handler = {
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.func = multi_nm_interrupt_handler,
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.priv = NULL,
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};
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@ -331,19 +248,160 @@ static void setup_processor(void)
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static char *trampoline_va, *first_page_va;
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unsigned long is_use_virt_timer(void)
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static inline uint64_t pwr_arm64hpc_read_imp_fj_core_uarch_restrection_el1(void)
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{
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extern unsigned long ihk_param_use_virt_timer;
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uint64_t reg;
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switch (ihk_param_use_virt_timer) {
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case 0: /* physical */
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case 1: /* virtual */
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break;
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default: /* invalid */
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panic("PANIC: is_use_virt_timer(): timer select neither phys-timer nor virt-timer.\n");
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break;
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asm volatile("mrs_s %0, " __stringify(IMP_FJ_CORE_UARCH_RESTRECTION_EL1)
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: "=r" (reg) : : "memory");
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return reg;
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}
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static ihk_spinlock_t imp_fj_core_uarch_restrection_el1_lock =
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SPIN_LOCK_UNLOCKED;
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static inline void pwr_arm64hpc_write_imp_fj_core_uarch_restrection_el1(uint64_t set_bit,
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uint64_t clear_bit)
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{
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uint64_t reg;
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unsigned long flags;
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flags = ihk_mc_spinlock_lock(&imp_fj_core_uarch_restrection_el1_lock);
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reg = pwr_arm64hpc_read_imp_fj_core_uarch_restrection_el1();
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reg = (reg & ~clear_bit) | set_bit;
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asm volatile("msr_s " __stringify(IMP_FJ_CORE_UARCH_RESTRECTION_EL1) ", %0"
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: : "r" (reg) : "memory");
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ihk_mc_spinlock_unlock(&imp_fj_core_uarch_restrection_el1_lock, flags);
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}
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static inline uint64_t pwr_arm64hpc_read_imp_soc_standby_ctrl_el1(void)
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{
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uint64_t reg;
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asm volatile("mrs_s %0, " __stringify(IMP_SOC_STANDBY_CTRL_EL1)
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: "=r" (reg) : : "memory");
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return reg;
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}
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static ihk_spinlock_t imp_soc_standby_ctrl_el1_lock = SPIN_LOCK_UNLOCKED;
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static inline void pwr_arm64hpc_write_imp_soc_standby_ctrl_el1(uint64_t set_bit,
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uint64_t clear_bit)
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{
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unsigned long flags;
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uint64_t reg;
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flags = ihk_mc_spinlock_lock(&imp_soc_standby_ctrl_el1_lock);
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reg = pwr_arm64hpc_read_imp_soc_standby_ctrl_el1();
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reg = (reg & ~clear_bit) | set_bit;
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asm volatile("msr_s " __stringify(IMP_SOC_STANDBY_CTRL_EL1) ", %0"
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: : "r" (reg) : "memory");
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ihk_mc_spinlock_unlock(&imp_soc_standby_ctrl_el1_lock, flags);
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}
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static unsigned long *retention_state_flag;
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static inline int is_hpcpwr_available(void)
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{
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if (retention_state_flag)
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return 1;
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else
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return 0;
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}
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static inline void pwr_arm64hpc_map_retention_state_flag(void)
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{
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extern unsigned long ihk_param_retention_state_flag_pa;
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unsigned long size = BITS_TO_LONGS(NR_CPUS) * sizeof(unsigned long);
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if (!ihk_param_retention_state_flag_pa) {
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return;
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}
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return ihk_param_use_virt_timer;
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retention_state_flag = map_fixed_area(ihk_param_retention_state_flag_pa,
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size, 0);
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}
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static inline int pwr_arm64hpc_retention_state_get(uint64_t *val)
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{
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unsigned long linux_core_id;
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int cpu = ihk_mc_get_processor_id();
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int ret;
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if (!is_hpcpwr_available()) {
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*val = 0;
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return 0;
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}
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ret = ihk_mc_get_core(cpu, &linux_core_id, NULL, NULL);
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if (ret) {
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return ret;
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}
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*val = test_bit(linux_core_id, retention_state_flag);
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return ret;
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}
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static inline int pwr_arm64hpc_retention_state_set(uint64_t val)
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{
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unsigned long linux_core_id;
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int cpu = ihk_mc_get_processor_id();
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int ret;
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if (!is_hpcpwr_available()) {
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return 0;
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}
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ret = ihk_mc_get_core(cpu, &linux_core_id, NULL, NULL);
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if (ret) {
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return ret;
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}
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if (val) {
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set_bit(cpu, retention_state_flag);
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} else {
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clear_bit(cpu, retention_state_flag);
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}
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return ret;
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}
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static inline int pwr_arm64hpc_enable_retention_state(void)
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{
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if (!is_hpcpwr_available()) {
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return 0;
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}
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pwr_arm64hpc_write_imp_soc_standby_ctrl_el1(IMP_SOC_STANDBY_CTRL_EL1_RETENTION,
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0);
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return 0;
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}
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static inline void init_power_management(void)
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{
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int state;
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uint64_t imp_fj_clear_bit = 0;
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uint64_t imp_soc_clear_bit = 0;
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if (!is_hpcpwr_available()) {
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return;
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}
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/* retention state */
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state = pwr_arm64hpc_retention_state_set(0);
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if (state) {
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panic("error: initialize power management\n");
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}
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/* issue state */
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imp_fj_clear_bit |= IMP_FJ_CORE_UARCH_RESTRECTION_EL1_ISSUE_RESTRICTION;
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/* eco_state */
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imp_fj_clear_bit |= IMP_FJ_CORE_UARCH_RESTRECTION_EL1_FL_RESTRICT_TRANS;
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imp_soc_clear_bit |= IMP_SOC_STANDBY_CTRL_EL1_ECO_MODE;
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/* ex_pipe_state */
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imp_fj_clear_bit |= IMP_FJ_CORE_UARCH_RESTRECTION_EL1_EX_RESTRICTION;
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/* write */
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pwr_arm64hpc_write_imp_fj_core_uarch_restrection_el1(0,
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imp_fj_clear_bit);
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pwr_arm64hpc_write_imp_soc_standby_ctrl_el1(0, imp_soc_clear_bit);
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}
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/*@
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@ -361,23 +419,19 @@ void ihk_mc_init_ap(void)
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kprintf("# of cpus : %d\n", cpu_info->ncpus);
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init_processors_local(cpu_info->ncpus);
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kprintf("IKC IRQ vector: %d, IKC target CPU APIC: %d\n",
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ihk_ikc_irq, ihk_ikc_irq_apicid);
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/* Do initialization for THIS cpu (BSP) */
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assign_processor_id();
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ihk_mc_register_interrupt_handler(INTRID_CPU_STOP, &cpu_stop_handler);
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ihk_mc_register_interrupt_handler(INTRID_MEMDUMP, &memdump_handler);
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ihk_mc_register_interrupt_handler(INTRID_MULTI_NMI, &multi_nmi_handler);
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ihk_mc_register_interrupt_handler(
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ihk_mc_get_vector(IHK_TLB_FLUSH_IRQ_VECTOR_START), &remote_tlb_flush_handler);
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ihk_mc_get_vector(IHK_TLB_FLUSH_IRQ_VECTOR_START),
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&remote_tlb_flush_handler);
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ihk_mc_register_interrupt_handler(get_timer_intrid(),
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get_timer_handler());
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if (is_use_virt_timer()) {
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ihk_mc_register_interrupt_handler(get_virt_timer_intrid(), &virt_timer_handler);
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} else {
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ihk_mc_register_interrupt_handler(get_phys_timer_intrid(), &phys_timer_handler);
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}
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init_smp_processor();
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init_power_management();
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}
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extern void vdso_init(void);
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@ -386,15 +440,13 @@ long (*__arm64_syscall_handler)(int, ihk_mc_user_context_t *);
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/* @ref.impl arch/arm64/include/asm/arch_timer.h::arch_timer_get_cntkctl */
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static inline unsigned int arch_timer_get_cntkctl(void)
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{
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unsigned int cntkctl;
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asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl));
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return cntkctl;
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return read_sysreg(cntkctl_el1);
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}
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/* @ref.impl arch/arm64/include/asm/arch_timer.h::arch_timer_set_cntkctl */
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static inline void arch_timer_set_cntkctl(unsigned int cntkctl)
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{
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asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl));
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write_sysreg(cntkctl, cntkctl_el1);
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}
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#ifdef CONFIG_ARM_ARCH_TIMER_EVTSTREAM
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@ -460,19 +512,19 @@ void init_cpu(void)
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{
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if(gic_enable)
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gic_enable();
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arm64_init_per_cpu_perfctr();
|
||||
arm64_enable_pmu();
|
||||
|
||||
if (xos_is_tchip()) {
|
||||
vhbm_barrier_registers_init();
|
||||
scdrv_registers_init();
|
||||
hpc_registers_init();
|
||||
}
|
||||
arm64_enable_user_access_pmu_regs();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM64_VHE
|
||||
/* @ref.impl arch/arm64/include/asm/virt.h */
|
||||
static inline int is_kernel_in_hyp_mode(void)
|
||||
{
|
||||
unsigned long el;
|
||||
|
||||
asm("mrs %0, CurrentEL" : "=r" (el));
|
||||
return el == CurrentEL_EL2;
|
||||
}
|
||||
|
||||
/* @ref.impl arch/arm64/kernel/smp.c */
|
||||
/* Whether the boot CPU is running in HYP mode or not */
|
||||
static int boot_cpu_hyp_mode;
|
||||
@ -517,8 +569,12 @@ void setup_arm64(void)
|
||||
|
||||
arm64_init_perfctr();
|
||||
|
||||
arch_timer_init();
|
||||
|
||||
gic_init();
|
||||
|
||||
pwr_arm64hpc_map_retention_state_flag();
|
||||
|
||||
init_cpu();
|
||||
|
||||
init_gettime_support();
|
||||
@ -561,6 +617,7 @@ void setup_arm64_ap(void (*next_func)(void))
|
||||
debug_monitors_init();
|
||||
arch_timer_configure_evtstream();
|
||||
init_cpu();
|
||||
init_power_management();
|
||||
call_ap_func(next_func);
|
||||
|
||||
/* BUG */
|
||||
@ -590,6 +647,7 @@ static void show_context_stack(struct pt_regs *regs)
|
||||
max_loop = (stack_top - sp) / min_stack_frame_size;
|
||||
|
||||
for (i = 0; i < max_loop; i++) {
|
||||
extern char _head[], _end[];
|
||||
uintptr_t *fp, *lr;
|
||||
fp = (uintptr_t *)sp;
|
||||
lr = (uintptr_t *)(sp + 8);
|
||||
@ -598,7 +656,8 @@ static void show_context_stack(struct pt_regs *regs)
|
||||
break;
|
||||
}
|
||||
|
||||
if ((*lr < MAP_KERNEL_START) || (*lr > MAP_KERNEL_START + MAP_KERNEL_SIZE)) {
|
||||
if ((*lr < (unsigned long)_head) ||
|
||||
(*lr > (unsigned long)_end)) {
|
||||
break;
|
||||
}
|
||||
|
||||
@ -623,7 +682,7 @@ void handle_IPI(unsigned int vector, struct pt_regs *regs)
|
||||
else {
|
||||
list_for_each_entry(h, &handlers[vector], list) {
|
||||
if (h->func) {
|
||||
h->func(h->priv);
|
||||
h->func(h->priv == NULL ? regs : h->priv);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -639,7 +698,18 @@ static void __arm64_wakeup(int hw_cpuid, unsigned long entry)
|
||||
/** IHK Functions **/
|
||||
|
||||
/* send WFI(Wait For Interrupt) instruction */
|
||||
extern void cpu_do_idle(void);
|
||||
static inline void cpu_do_idle(void)
|
||||
{
|
||||
extern void __cpu_do_idle(void);
|
||||
uint64_t retention;
|
||||
int state;
|
||||
|
||||
state = pwr_arm64hpc_retention_state_get(&retention);
|
||||
if ((state == 0) && (retention != 0)) {
|
||||
pwr_arm64hpc_enable_retention_state();
|
||||
}
|
||||
__cpu_do_idle();
|
||||
}
|
||||
|
||||
/* halt by WFI(Wait For Interrupt) */
|
||||
void cpu_halt(void)
|
||||
@ -1113,20 +1183,32 @@ long ihk_mc_show_cpuinfo(char *buf, size_t buf_size, unsigned long read_off, int
|
||||
int j = 0;
|
||||
|
||||
/* generate strings */
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "processor\t: %d\n", cpuinfo->hwid);
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "Features\t:");
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"processor\t: %d\n", cpuinfo->hwid);
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff, "Features\t:");
|
||||
|
||||
for (j = 0; hwcap_str[j]; j++) {
|
||||
if (elf_hwcap & (1 << j)) {
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, " %s", hwcap_str[j]);
|
||||
loff += scnprintf(lbuf + loff,
|
||||
lbuf_size - loff,
|
||||
" %s", hwcap_str[j]);
|
||||
}
|
||||
}
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "\n");
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "CPU implementer\t: 0x%02x\n", MIDR_IMPLEMENTOR(midr));
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "CPU architecture: 8\n");
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
|
||||
loff += snprintf(lbuf + loff, lbuf_size - loff, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff, "\n");
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"CPU implementer\t: 0x%02x\n",
|
||||
MIDR_IMPLEMENTOR(midr));
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"CPU architecture: 8\n");
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"CPU variant\t: 0x%x\n",
|
||||
MIDR_VARIANT(midr));
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"CPU part\t: 0x%03x\n",
|
||||
MIDR_PARTNUM(midr));
|
||||
loff += scnprintf(lbuf + loff, lbuf_size - loff,
|
||||
"CPU revision\t: %d\n\n",
|
||||
MIDR_REVISION(midr));
|
||||
|
||||
/* check buffer depletion */
|
||||
if ((i < num_processors - 1) && ((lbuf_size - loff) == 1)) {
|
||||
@ -1408,6 +1490,10 @@ out:
|
||||
void
|
||||
save_fp_regs(struct thread *thread)
|
||||
{
|
||||
if (thread == &cpu_local_var(idle)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (likely(elf_hwcap & (HWCAP_FP | HWCAP_ASIMD))) {
|
||||
if (check_and_allocate_fp_regs(thread) != 0) {
|
||||
// alloc error.
|
||||
@ -1468,26 +1554,6 @@ restore_fp_regs(struct thread *thread)
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
lapic_timer_enable(unsigned int clocks)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
/* gen control register value */
|
||||
asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
|
||||
val &= ~(ARCH_TIMER_CTRL_IT_STAT | ARCH_TIMER_CTRL_IT_MASK);
|
||||
val |= ARCH_TIMER_CTRL_ENABLE;
|
||||
|
||||
if (is_use_virt_timer()) {
|
||||
asm volatile("msr cntv_tval_el0, %0" : : "r" (clocks));
|
||||
asm volatile("msr cntv_ctl_el0, %0" : : "r" (val));
|
||||
} else {
|
||||
asm volatile("msr cntp_tval_el0, %0" : : "r" (clocks));
|
||||
asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
|
||||
}
|
||||
per_cpu_timer_val[ihk_mc_get_processor_id()] = clocks;
|
||||
}
|
||||
|
||||
void
|
||||
unhandled_page_fault(struct thread *thread, void *fault_addr, void *regs)
|
||||
{
|
||||
@ -1540,26 +1606,6 @@ unhandled_page_fault(struct thread *thread, void *fault_addr, void *regs)
|
||||
return;
|
||||
}
|
||||
|
||||
void
|
||||
lapic_timer_disable()
|
||||
{
|
||||
unsigned int zero = 0;
|
||||
unsigned int val = 0;
|
||||
|
||||
/* gen control register value */
|
||||
asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
|
||||
val &= ~(ARCH_TIMER_CTRL_IT_STAT | ARCH_TIMER_CTRL_IT_MASK | ARCH_TIMER_CTRL_ENABLE);
|
||||
|
||||
if (is_use_virt_timer()) {
|
||||
asm volatile("msr cntv_ctl_el0, %0" : : "r" (val));
|
||||
asm volatile("msr cntv_tval_el0, %0" : : "r" (zero));
|
||||
} else {
|
||||
asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
|
||||
asm volatile("msr cntp_tval_el0, %0" : : "r" (zero));
|
||||
}
|
||||
per_cpu_timer_val[ihk_mc_get_processor_id()] = 0;
|
||||
}
|
||||
|
||||
void init_tick(void)
|
||||
{
|
||||
dkprintf("init_tick():\n");
|
||||
@ -1588,25 +1634,174 @@ void arch_start_pvclock(void)
|
||||
void
|
||||
mod_nmi_ctx(void *nmi_ctx, void (*func)())
|
||||
{
|
||||
/* TODO: skeleton for rusage */
|
||||
func();
|
||||
}
|
||||
|
||||
extern void freeze(void);
|
||||
void __freeze(void)
|
||||
{
|
||||
freeze();
|
||||
}
|
||||
|
||||
|
||||
#define SYSREG_READ_S(sys_reg) case (sys_reg): asm volatile("mrs_s %0, " __stringify(sys_reg) : "=r" (*val)); break
|
||||
static inline int arch_cpu_mrs(uint32_t sys_reg, uint64_t *val)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (sys_reg) {
|
||||
SYSREG_READ_S(IMP_FJ_TAG_ADDRESS_CTRL_EL1);
|
||||
SYSREG_READ_S(IMP_SCCR_CTRL_EL1);
|
||||
SYSREG_READ_S(IMP_SCCR_ASSIGN_EL1);
|
||||
SYSREG_READ_S(IMP_SCCR_SET0_L2_EL1);
|
||||
SYSREG_READ_S(IMP_SCCR_SET1_L2_EL1);
|
||||
SYSREG_READ_S(IMP_SCCR_L1_EL0);
|
||||
SYSREG_READ_S(IMP_PF_CTRL_EL1);
|
||||
SYSREG_READ_S(IMP_PF_STREAM_DETECT_CTRL_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL0_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL1_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL2_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL3_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL4_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL5_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL6_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_CTRL7_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE0_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE1_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE2_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE3_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE4_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE5_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE6_EL0);
|
||||
SYSREG_READ_S(IMP_PF_INJECTION_DISTANCE7_EL0);
|
||||
SYSREG_READ_S(IMP_BARRIER_CTRL_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_BST_BIT_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB0_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB1_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB2_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB3_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB4_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_INIT_SYNC_BB5_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_ASSIGN_SYNC_W0_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_ASSIGN_SYNC_W1_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_ASSIGN_SYNC_W2_EL1);
|
||||
SYSREG_READ_S(IMP_BARRIER_ASSIGN_SYNC_W3_EL1);
|
||||
SYSREG_READ_S(IMP_SOC_STANDBY_CTRL_EL1);
|
||||
SYSREG_READ_S(IMP_FJ_CORE_UARCH_CTRL_EL2);
|
||||
SYSREG_READ_S(IMP_FJ_CORE_UARCH_RESTRECTION_EL1);
|
||||
/* fall through */
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int arch_cpu_read_register(struct ihk_os_cpu_register *desc)
|
||||
{
|
||||
int ret = 0;
|
||||
uint64_t value;
|
||||
|
||||
if (desc->addr) {
|
||||
panic("memory mapped register is not supported.\n");
|
||||
} else if (desc->addr_ext) {
|
||||
ret = arch_cpu_mrs(desc->addr_ext, &value);
|
||||
if (ret == 0) {
|
||||
desc->val = value;
|
||||
}
|
||||
} else {
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define SYSREG_WRITE_S(sys_reg) case (sys_reg): asm volatile("msr_s " __stringify(sys_reg) ", %0" :: "r" (val)); break
|
||||
static inline int arch_cpu_msr(uint32_t sys_reg, uint64_t val)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (sys_reg) {
|
||||
SYSREG_WRITE_S(IMP_FJ_TAG_ADDRESS_CTRL_EL1);
|
||||
SYSREG_WRITE_S(IMP_SCCR_CTRL_EL1);
|
||||
SYSREG_WRITE_S(IMP_SCCR_ASSIGN_EL1);
|
||||
SYSREG_WRITE_S(IMP_SCCR_SET0_L2_EL1);
|
||||
SYSREG_WRITE_S(IMP_SCCR_SET1_L2_EL1);
|
||||
SYSREG_WRITE_S(IMP_SCCR_L1_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_CTRL_EL1);
|
||||
SYSREG_WRITE_S(IMP_PF_STREAM_DETECT_CTRL_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL0_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL1_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL2_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL3_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL4_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL5_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL6_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_CTRL7_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE0_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE1_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE2_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE3_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE4_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE5_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE6_EL0);
|
||||
SYSREG_WRITE_S(IMP_PF_INJECTION_DISTANCE7_EL0);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_CTRL_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_BST_BIT_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB0_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB1_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB2_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB3_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB4_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_INIT_SYNC_BB5_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_ASSIGN_SYNC_W0_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_ASSIGN_SYNC_W1_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_ASSIGN_SYNC_W2_EL1);
|
||||
SYSREG_WRITE_S(IMP_BARRIER_ASSIGN_SYNC_W3_EL1);
|
||||
SYSREG_WRITE_S(IMP_FJ_CORE_UARCH_CTRL_EL2);
|
||||
SYSREG_WRITE_S(IMP_FJ_CORE_UARCH_RESTRECTION_EL1);
|
||||
/* fallthrough */
|
||||
case IMP_SOC_STANDBY_CTRL_EL1:
|
||||
asm volatile("msr_s " __stringify(IMP_SOC_STANDBY_CTRL_EL1) ", %0"
|
||||
: : "r" (val) : "memory");
|
||||
if (val & IMP_SOC_STANDBY_CTRL_EL1_MODE_CHANGE) {
|
||||
wfe();
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int arch_cpu_write_register(struct ihk_os_cpu_register *desc)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (desc->addr) {
|
||||
panic("memory mapped register is not supported.\n");
|
||||
} else if (desc->addr_ext) {
|
||||
ret = arch_cpu_msr(desc->addr_ext, desc->val);
|
||||
} else {
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int arch_cpu_read_write_register(
|
||||
struct ihk_os_cpu_register *desc,
|
||||
enum mcctrl_os_cpu_operation op)
|
||||
{
|
||||
/* TODO: skeleton for patch:0676 */
|
||||
int ret;
|
||||
if (op == MCCTRL_OS_CPU_READ_REGISTER) {
|
||||
// desc->val = rdmsr(desc->addr);
|
||||
ret = arch_cpu_read_register(desc);
|
||||
}
|
||||
else if (op == MCCTRL_OS_CPU_WRITE_REGISTER) {
|
||||
// wrmsr(desc->addr, desc->val);
|
||||
ret = arch_cpu_write_register(desc);
|
||||
}
|
||||
else {
|
||||
return -1;
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int smp_call_func(cpu_set_t *__cpu_set, smp_func_t __func, void *__arg)
|
||||
|
||||
Reference in New Issue
Block a user