gh0s7/mckernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freeze: change freeze-thaw to normal interrupt

Browse Source 
Change-Id: Ib4dbac28f0074595e92ef316945b37ef4bc18327
This commit is contained in:
TOIDA,Suguru
2019-08-27 13:32:37 +09:00
committed by Masamichi Takagi
parent 299d47abf5
commit ff982b8594
8 changed files with 67 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
arch/arm64/kernel/cpu.c
View File

@ -119,6 +119,22 @@ static struct ihk_mc_interrupt_handler cpu_stop_handler = {
};
extern long freeze_thaw(void *nmi_ctx);
static void multi_interrupt_handler(void *priv)
{
switch (multi_intr_mode) {
case 1:
case 2: /* mode == 1or2, for FREEZER intr */
dkprintf("%s: freeze mode intr catch. (multi_intr_mode=%d)\n",
__func__, multi_intr_mode);
freeze_thaw(NULL);
break;
default:
ekprintf("%s: Unknown multi-intr-mode(%d) detected.\n",
__func__, multi_intr_mode);
break;
}
}
static void multi_nm_interrupt_handler(void *priv)
{
extern int nmi_mode;
@ -126,14 +142,6 @@ static void multi_nm_interrupt_handler(void *priv)
union arm64_cpu_local_variables *clv;
switch (nmi_mode) {
case 1:
case 2:
/* mode == 1or2, for FREEZER NMI */
dkprintf("%s: freeze mode NMI catch. (nmi_mode=%d)\n",
__func__, nmi_mode);
freeze_thaw(NULL);
break;
case 0:
/* mode == 0, for MEMDUMP NMI */
clv = get_arm64_this_cpu_local();
@ -164,6 +172,11 @@ static void multi_nm_interrupt_handler(void *priv)
}
}
static struct ihk_mc_interrupt_handler multi_intr_handler = {
.func = multi_interrupt_handler,
.priv = NULL,
};
static struct ihk_mc_interrupt_handler multi_nmi_handler = {
.func = multi_nm_interrupt_handler,
.priv = NULL,
@ -428,6 +441,8 @@ void ihk_mc_init_ap(void)
ihk_mc_register_interrupt_handler(INTRID_CPU_STOP, &cpu_stop_handler);
ihk_mc_register_interrupt_handler(INTRID_MULTI_NMI, &multi_nmi_handler);
ihk_mc_register_interrupt_handler(INTRID_MULTI_INTR,
&multi_intr_handler);
ihk_mc_register_interrupt_handler(
ihk_mc_get_vector(IHK_TLB_FLUSH_IRQ_VECTOR_START),
&remote_tlb_flush_handler);

5
arch/arm64/kernel/include/irq.h
View File

@ -1,4 +1,4 @@
/* irq.h COPYRIGHT FUJITSU LIMITED 2015-2018 */
/* irq.h COPYRIGHT FUJITSU LIMITED 2015-2019 */
#ifndef __HEADER_ARM64_IRQ_H
#define __HEADER_ARM64_IRQ_H
@ -14,7 +14,8 @@
#define INTRID_QUERY_FREE_MEM 2
#define INTRID_CPU_STOP 3
#define INTRID_TLB_FLUSH 4
#define INTRID_STACK_TRACE 6
#define INTRID_STACK_TRACE 5
#define INTRID_MULTI_INTR 6
#define INTRID_MULTI_NMI 7
/* use PPI interrupt number */

40
arch/x86_64/kernel/interrupt.S
View File

@ -1,3 +1,4 @@
/* interrupt.S COPYRIGHT FUJITSU LIMITED 2019 */
/**
* \file interrupt.S
* License details are found in the file LICENSE.
@ -91,6 +92,9 @@ vector=vector+1
.endr
common_interrupt:
#define MULT_INTR_VECTOR 242
cmp $(MULT_INTR_VECTOR),%rdi
je 1f
PUSH_ALL_REGS
movq ERROR_OFFSET(%rsp), %rdi
movq %rsp, %rsi
@ -98,6 +102,23 @@ common_interrupt:
POP_ALL_REGS
addq $8, %rsp
iretq
1:
#define PANIC_REGS 240
movq %rax,%gs:PANIC_REGS+0x00
movq %rsp,%gs:PANIC_REGS+0x08
cld
movq %gs:PANIC_REGS+0x00,%rax
PUSH_ALL_REGS
subq $40, %rsp
movq %rsp,%gs:PANIC_REGS+0x10
movq %rsp, %rdi
call freeze_thaw
cmpq $0, %rax
jnz 2f
addq $40, %rsp
2:
POP_ALL_REGS
iretq
.globl __page_fault_handler_address
__page_fault_handler_address:
@ -140,31 +161,12 @@ __freeze:
.globl nmi
nmi:
#define PANICED 232
#define PANIC_REGS 240
movq %rax,%gs:PANIC_REGS+0x00
movq %rsp,%gs:PANIC_REGS+0x08
movl nmi_mode(%rip),%eax
cmp $3,%rax
je 4f
cmp $1,%rax
je 1f
cmp $2,%rax
jne 3f
1:
cld
movq %gs:PANIC_REGS+0x00,%rax
PUSH_ALL_REGS
subq $40, %rsp
movq %rsp,%gs:PANIC_REGS+0x10
movq %rsp, %rdi
call freeze_thaw
cmpq $0, %rax
jnz 2f
addq $40, %rsp
2:
POP_ALL_REGS
iretq
3:
movq %rbx,%gs:PANIC_REGS+0x08
movq %rcx,%gs:PANIC_REGS+0x10