d4d78e9c61
This includes the following fixes: * fix build of arch/arm64/kernel/vdso Change-Id: I73b05034d29f7f8731ac17f9736edbba4fb2c639
128 lines
2.8 KiB
C
128 lines
2.8 KiB
C
/* registers.h COPYRIGHT FUJITSU LIMITED 2015-2018 */
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#ifndef __HEADER_ARM64_COMMON_REGISTERS_H
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#define __HEADER_ARM64_COMMON_REGISTERS_H
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#include <types.h>
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#include <arch/cpu.h>
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#include <sysreg.h>
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#define RFLAGS_CF (1 << 0)
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#define RFLAGS_PF (1 << 2)
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#define RFLAGS_AF (1 << 4)
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#define RFLAGS_ZF (1 << 6)
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#define RFLAGS_SF (1 << 7)
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#define RFLAGS_TF (1 << 8)
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#define RFLAGS_IF (1 << 9)
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#define RFLAGS_DF (1 << 10)
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#define RFLAGS_OF (1 << 11)
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#define RFLAGS_IOPL (3 << 12)
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#define RFLAGS_NT (1 << 14)
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#define RFLAGS_RF (1 << 16)
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#define RFLAGS_VM (1 << 17)
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#define RFLAGS_AC (1 << 18)
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#define RFLAGS_VIF (1 << 19)
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#define RFLAGS_VIP (1 << 20)
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#define RFLAGS_ID (1 << 21)
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#define DB6_B0 (1 << 0)
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#define DB6_B1 (1 << 1)
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#define DB6_B2 (1 << 2)
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#define DB6_B3 (1 << 3)
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#define DB6_BD (1 << 13)
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#define DB6_BS (1 << 14)
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#define DB6_BT (1 << 15)
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#define MSR_EFER 0xc0000080
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#define MSR_STAR 0xc0000081
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#define MSR_LSTAR 0xc0000082
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#define MSR_FMASK 0xc0000084
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#define MSR_FS_BASE 0xc0000100
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#define MSR_GS_BASE 0xc0000101
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#define MSR_IA32_APIC_BASE 0x000000001b
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#define MSR_PLATFORM_INFO 0x000000ce
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
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#define MSR_IA32_CR_PAT 0x00000277
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#define CVAL(event, mask) \
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((((event) & 0xf00) << 24) | ((mask) << 8) | ((event) & 0xff))
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#define CVAL2(event, mask, inv, count) \
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((((event) & 0xf00) << 24) | ((mask) << 8) | ((event) & 0xff) | \
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((inv & 1) << 23) | ((count & 0xff) << 24))
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/* AMD */
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#define MSR_PERF_CTL_0 0xc0010000
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#define MSR_PERF_CTR_0 0xc0010004
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static unsigned long xgetbv(unsigned int index)
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{
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return 0;
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}
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static void xsetbv(unsigned int index, unsigned long val)
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{
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}
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static unsigned long rdpmc(unsigned int counter)
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{
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return 0;
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}
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static unsigned long rdmsr(unsigned int index)
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{
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return 0;
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}
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/* @ref.impl linux4.10.16 */
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/* arch/arm64/include/asm/arch_timer.h:arch_counter_get_cntvct() */
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static inline unsigned long rdtsc(void)
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{
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isb();
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return read_sysreg(cntvct_el0);
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}
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static void set_perfctl(int counter, int event, int mask)
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{
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}
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static void start_perfctr(int counter)
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{
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}
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static void stop_perfctr(int counter)
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{
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}
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static void clear_perfctl(int counter)
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{
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}
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static void set_perfctr(int counter, unsigned long value)
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{
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}
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static unsigned long read_perfctr(int counter)
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{
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return 0;
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}
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#define ihk_mc_mb() do {} while(0);
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#define REGS_GET_STACK_POINTER(regs) (((struct pt_regs *)regs)->sp)
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enum arm64_pf_error_code {
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PF_PROT = 1 << 0,
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PF_WRITE = 1 << 1,
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PF_USER = 1 << 2,
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PF_RSVD = 1 << 3,
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PF_INSTR = 1 << 4,
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PF_PATCH = 1 << 29,
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PF_POPULATE = 1 << 30,
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};
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#endif /* !__HEADER_ARM64_COMMON_REGISTERS_H */
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