beac6c3e80
Change-Id: I4c0fca7d34e69b4774141e115b8ebc03c5c1e8b3 Fujitsu: POSTK_DEBUG_ARCH_DEP_12 Refs: #1355
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/* archdeps.h COPYRIGHT FUJITSU LIMITED 2017 */
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#ifndef __HEADER_MCCTRL_ARM64_ARCHDEPS_H
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#define __HEADER_MCCTRL_ARM64_ARCHDEPS_H
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#ifdef POSTK_DEBUG_ARCH_DEP_100 /* rus_mmap() setting vm_flags arch depend defined */
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#include <linux/mm.h>
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#endif /* POSTK_DEBUG_ARCH_DEP_100 */
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extern int translate_rva_to_rpa(ihk_os_t os, unsigned long rpt, unsigned long rva,
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unsigned long *rpap, unsigned long *pgsizep);
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#define PFN_WRITE_COMBINED PTE_ATTRINDX(MT_NORMAL_NC)
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static inline bool pte_is_write_combined(pte_t pte)
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{
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#if defined(MIDR_CPU_MODEL_MASK)
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/*
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* Fix up arm64 braindamage of using NORMAL_NC for write
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* combining when Device GRE exists specifically for the
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* purpose. Needed on ThunderX2.
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*/
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switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
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#if defined(ARM_CPU_IMP_BRCM) && defined(BRCM_CPU_PART_VULCAN)
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case MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN):
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#endif
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case MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2):
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return ((pte_val(pte) & PTE_ATTRINDX_MASK) ==
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PTE_ATTRINDX(MT_DEVICE_GRE));
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}
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#endif
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return ((pte_val(pte) & PTE_ATTRINDX_MASK) == PFN_WRITE_COMBINED);
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}
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#define ARMV8_IDX_COUNTER0 0
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#define ARCH_PERF_COUNTER_START ARMV8_IDX_COUNTER0
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0)
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static const unsigned long arch_rus_vm_flags = VM_RESERVED | VM_MIXEDMAP | VM_EXEC;
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#else
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static const unsigned long arch_rus_vm_flags = VM_DONTDUMP | VM_MIXEDMAP | VM_EXEC;
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#endif
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#endif /* __HEADER_MCCTRL_ARM64_ARCHDEPS_H */
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