d4d78e9c61
This includes the following fixes: * fix build of arch/arm64/kernel/vdso Change-Id: I73b05034d29f7f8731ac17f9736edbba4fb2c639
103 lines
5.1 KiB
C
103 lines
5.1 KiB
C
/* imp-sysreg.h COPYRIGHT FUJITSU LIMITED 2016-2018 */
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#ifndef __ASM_IMP_SYSREG_H
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#define __ASM_IMP_SYSREG_H
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#ifndef __ASSEMBLY__
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/* register sys_reg list */
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1 sys_reg(3, 0, 11, 2, 0)
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#define IMP_SCCR_CTRL_EL1 sys_reg(3, 0, 11, 8, 0)
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#define IMP_SCCR_ASSIGN_EL1 sys_reg(3, 0, 11, 8, 1)
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#define IMP_SCCR_SET0_L2_EL1 sys_reg(3, 0, 15, 8, 2)
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#define IMP_SCCR_SET1_L2_EL1 sys_reg(3, 0, 15, 8, 3)
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#define IMP_SCCR_L1_EL0 sys_reg(3, 3, 11, 8, 2)
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#define IMP_PF_CTRL_EL1 sys_reg(3, 0, 11, 4, 0)
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#define IMP_PF_STREAM_DETECT_CTRL_EL0 sys_reg(3, 3, 11, 4, 0)
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#define IMP_PF_INJECTION_CTRL0_EL0 sys_reg(3, 3, 11, 6, 0)
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#define IMP_PF_INJECTION_CTRL1_EL0 sys_reg(3, 3, 11, 6, 1)
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#define IMP_PF_INJECTION_CTRL2_EL0 sys_reg(3, 3, 11, 6, 2)
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#define IMP_PF_INJECTION_CTRL3_EL0 sys_reg(3, 3, 11, 6, 3)
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#define IMP_PF_INJECTION_CTRL4_EL0 sys_reg(3, 3, 11, 6, 4)
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#define IMP_PF_INJECTION_CTRL5_EL0 sys_reg(3, 3, 11, 6, 5)
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#define IMP_PF_INJECTION_CTRL6_EL0 sys_reg(3, 3, 11, 6, 6)
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#define IMP_PF_INJECTION_CTRL7_EL0 sys_reg(3, 3, 11, 6, 7)
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#define IMP_PF_INJECTION_DISTANCE0_EL0 sys_reg(3, 3, 11, 7, 0)
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#define IMP_PF_INJECTION_DISTANCE1_EL0 sys_reg(3, 3, 11, 7, 1)
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#define IMP_PF_INJECTION_DISTANCE2_EL0 sys_reg(3, 3, 11, 7, 2)
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#define IMP_PF_INJECTION_DISTANCE3_EL0 sys_reg(3, 3, 11, 7, 3)
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#define IMP_PF_INJECTION_DISTANCE4_EL0 sys_reg(3, 3, 11, 7, 4)
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#define IMP_PF_INJECTION_DISTANCE5_EL0 sys_reg(3, 3, 11, 7, 5)
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#define IMP_PF_INJECTION_DISTANCE6_EL0 sys_reg(3, 3, 11, 7, 6)
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#define IMP_PF_INJECTION_DISTANCE7_EL0 sys_reg(3, 3, 11, 7, 7)
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#define IMP_BARRIER_CTRL_EL1 sys_reg(3, 0, 11, 12, 0)
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#define IMP_BARRIER_BST_BIT_EL1 sys_reg(3, 0, 11, 12, 4)
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#define IMP_BARRIER_INIT_SYNC_BB0_EL1 sys_reg(3, 0, 15, 13, 0)
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#define IMP_BARRIER_INIT_SYNC_BB1_EL1 sys_reg(3, 0, 15, 13, 1)
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#define IMP_BARRIER_INIT_SYNC_BB2_EL1 sys_reg(3, 0, 15, 13, 2)
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#define IMP_BARRIER_INIT_SYNC_BB3_EL1 sys_reg(3, 0, 15, 13, 3)
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#define IMP_BARRIER_INIT_SYNC_BB4_EL1 sys_reg(3, 0, 15, 13, 4)
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#define IMP_BARRIER_INIT_SYNC_BB5_EL1 sys_reg(3, 0, 15, 13, 5)
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#define IMP_BARRIER_ASSIGN_SYNC_W0_EL1 sys_reg(3, 0, 15, 15, 0)
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#define IMP_BARRIER_ASSIGN_SYNC_W1_EL1 sys_reg(3, 0, 15, 15, 1)
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#define IMP_BARRIER_ASSIGN_SYNC_W2_EL1 sys_reg(3, 0, 15, 15, 2)
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#define IMP_BARRIER_ASSIGN_SYNC_W3_EL1 sys_reg(3, 0, 15, 15, 3)
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#define IMP_SOC_STANDBY_CTRL_EL1 sys_reg(3, 0, 11, 0, 0)
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#define IMP_FJ_CORE_UARCH_CTRL_EL2 sys_reg(3, 4, 11, 0, 4)
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1 sys_reg(3, 0, 11, 0, 5)
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/* macros */
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#define PWR_REG_MASK(reg, feild) (((UL(1) << ((reg##_##feild##_MSB) - (reg##_##feild##_LSB) + 1)) - 1) << (reg##_##feild##_LSB))
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/* IMP_FJ_TAG_ADDRESS_CTRL_EL1 */
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_TBO0_SHIFT (0)
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_SEC0_SHIFT (8)
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_PFE0_SHIFT (9)
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_TBO0_MASK (1UL << IMP_FJ_TAG_ADDRESS_CTRL_EL1_TBO0_SHIFT)
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_SEC0_MASK (1UL << IMP_FJ_TAG_ADDRESS_CTRL_EL1_SEC0_SHIFT)
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#define IMP_FJ_TAG_ADDRESS_CTRL_EL1_PFE0_MASK (1UL << IMP_FJ_TAG_ADDRESS_CTRL_EL1_PFE0_SHIFT)
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/* IMP_SCCR_CTRL_EL1 */
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#define IMP_SCCR_CTRL_EL1_EL1AE_SHIFT (63)
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#define IMP_SCCR_CTRL_EL1_EL1AE_MASK (1UL << IMP_SCCR_CTRL_EL1_EL1AE_SHIFT)
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/* IMP_SCCR_SET0_L2_EL1 */
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#define IMP_SCCR_SET0_L2_EL1_L2_SEC0_SHIFT (0)
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/* IMP_PF_CTRL_EL1 */
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#define IMP_PF_CTRL_EL1_EL1AE_ENABLE (1UL << 63)
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#define IMP_PF_CTRL_EL1_EL0AE_ENABLE (1UL << 62)
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/* IMP_BARRIER_CTRL_EL1 */
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#define IMP_BARRIER_CTRL_EL1_EL1AE_ENABLE (1UL << 63)
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#define IMP_BARRIER_CTRL_EL1_EL0AE_ENABLE (1UL << 62)
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/* IMP_SOC_STANDBY_CTRL_EL1 */
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#define IMP_SOC_STANDBY_CTRL_EL1_ECO_MODE_MSB 2
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#define IMP_SOC_STANDBY_CTRL_EL1_ECO_MODE_LSB 2
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#define IMP_SOC_STANDBY_CTRL_EL1_MODE_CHANGE_MSB 1
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#define IMP_SOC_STANDBY_CTRL_EL1_MODE_CHANGE_LSB 1
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#define IMP_SOC_STANDBY_CTRL_EL1_RETENTION_MSB 0
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#define IMP_SOC_STANDBY_CTRL_EL1_RETENTION_LSB 0
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#define IMP_SOC_STANDBY_CTRL_EL1_ECO_MODE PWR_REG_MASK(IMP_SOC_STANDBY_CTRL_EL1, ECO_MODE)
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#define IMP_SOC_STANDBY_CTRL_EL1_MODE_CHANGE PWR_REG_MASK(IMP_SOC_STANDBY_CTRL_EL1, MODE_CHANGE)
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#define IMP_SOC_STANDBY_CTRL_EL1_RETENTION PWR_REG_MASK(IMP_SOC_STANDBY_CTRL_EL1, RETENTION)
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/* IMP_FJ_CORE_UARCH_RESTRECTION_EL1 */
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_FL_RESTRICT_TRANS_MSB 33
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_FL_RESTRICT_TRANS_LSB 33
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_ISSUE_RESTRICTION_MSB 9
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_ISSUE_RESTRICTION_LSB 8
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_EX_RESTRICTION_MSB 0
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_EX_RESTRICTION_LSB 0
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_FL_RESTRICT_TRANS PWR_REG_MASK(IMP_FJ_CORE_UARCH_RESTRECTION_EL1, FL_RESTRICT_TRANS)
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_ISSUE_RESTRICTION PWR_REG_MASK(IMP_FJ_CORE_UARCH_RESTRECTION_EL1, ISSUE_RESTRICTION)
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#define IMP_FJ_CORE_UARCH_RESTRECTION_EL1_EX_RESTRICTION PWR_REG_MASK(IMP_FJ_CORE_UARCH_RESTRECTION_EL1, EX_RESTRICTION)
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void scdrv_registers_init(void);
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void hpc_registers_init(void);
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void vhbm_barrier_registers_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_IMP_SYSREG_H */
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