9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
14 lines
378 B
ArmAsm
14 lines
378 B
ArmAsm
/* proc-macros.S COPYRIGHT FUJITSU LIMITED 2015 */
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#include <arch-memory.h>
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register.
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*/
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.macro dcache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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