9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
33 lines
776 B
C
33 lines
776 B
C
/* cas.h COPYRIGHT FUJITSU LIMITED 2015-2016 */
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#ifndef __HEADER_ARM64_COMMON_CAS_H
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#define __HEADER_ARM64_COMMON_CAS_H
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#include <arch/cpu.h>
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/* @ref.impl arch/arm64/include/asm/cmpxchg.h::__cmpxchg (size == 8 case) */
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/* 8 byte compare and swap, return 0:fail, 1:success */
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static inline int
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compare_and_swap(void *addr, unsigned long olddata, unsigned long newdata)
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{
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unsigned long oldval = 0, res = 0;
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smp_mb();
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do {
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asm volatile("// __cmpxchg8\n"
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" ldxr %1, %2\n"
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" mov %w0, #0\n"
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" cmp %1, %3\n"
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" b.ne 1f\n"
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" stxr %w0, %4, %2\n"
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"1:\n"
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: "=&r" (res), "=&r" (oldval), "+Q" (*(unsigned long *)addr)
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: "Ir" (olddata), "r" (newdata)
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: "cc");
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} while (res);
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smp_mb();
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return (oldval == olddata);
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}
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#endif /* !__HEADER_ARM64_COMMON_CAS_H */
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