9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
152 lines
2.7 KiB
C
152 lines
2.7 KiB
C
/* fpsimdmacros.h COPYRIGHT FUJITSU LIMITED 2016-2017 */
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.macro _check_reg nr
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.if (\nr) < 0 || (\nr) > 31
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.error "Bad register number \nr."
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.endif
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.endm
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.macro _check_zreg znr
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.if (\znr) < 0 || (\znr) > 31
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.error "Bad Scalable Vector Extension vector register number \znr."
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.endif
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.endm
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.macro _check_preg pnr
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.if (\pnr) < 0 || (\pnr) > 15
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.error "Bad Scalable Vector Extension predicate register number \pnr."
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.endif
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.endm
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.macro _check_num n, min, max
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.if (\n) < (\min) || (\n) > (\max)
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.error "Number \n out of range [\min,\max]"
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.endif
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.endm
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.macro _zstrv znt, nspb, ioff=0
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_check_zreg \znt
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_check_reg \nspb
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_check_num (\ioff), -0x100, 0xff
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.inst 0xe5804000 \
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| (\znt) \
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| ((\nspb) << 5) \
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| (((\ioff) & 7) << 10) \
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| (((\ioff) & 0x1f8) << 13)
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.endm
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.macro _zldrv znt, nspb, ioff=0
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_check_zreg \znt
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_check_reg \nspb
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_check_num (\ioff), -0x100, 0xff
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.inst 0x85804000 \
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| (\znt) \
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| ((\nspb) << 5) \
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| (((\ioff) & 7) << 10) \
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| (((\ioff) & 0x1f8) << 13)
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.endm
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.macro _zstrp pnt, nspb, ioff=0
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_check_preg \pnt
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_check_reg \nspb
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_check_num (\ioff), -0x100, 0xff
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.inst 0xe5800000 \
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| (\pnt) \
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| ((\nspb) << 5) \
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| (((\ioff) & 7) << 10) \
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| (((\ioff) & 0x1f8) << 13)
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.endm
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.macro _zldrp pnt, nspb, ioff=0
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_check_preg \pnt
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_check_reg \nspb
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_check_num (\ioff), -0x100, 0xff
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.inst 0x85800000 \
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| (\pnt) \
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| ((\nspb) << 5) \
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| (((\ioff) & 7) << 10) \
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| (((\ioff) & 0x1f8) << 13)
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.endm
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.macro _zrdvl nspd, is1
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_check_reg \nspd
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_check_num (\is1), -0x20, 0x1f
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.inst 0x04bf5000 \
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| (\nspd) \
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| (((\is1) & 0x3f) << 5)
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.endm
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.macro _zrdffr pnd
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_check_preg \pnd
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.inst 0x2519f000 \
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| (\pnd)
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.endm
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.macro _zwrffr pnd
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_check_preg \pnd
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.inst 0x25289000 \
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| ((\pnd) << 5)
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.endm
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.macro for from, to, insn
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.if (\from) >= (\to)
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\insn (\from)
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.exitm
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.endif
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for \from, ((\from) + (\to)) / 2, \insn
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for ((\from) + (\to)) / 2 + 1, \to, \insn
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.endm
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.macro sve_save nb, xpfpsr, ntmp
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.macro savez n
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_zstrv \n, \nb, (\n) - 34
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.endm
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.macro savep n
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_zstrp \n, \nb, (\n) - 16
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.endm
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for 0, 31, savez
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for 0, 15, savep
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_zrdffr 0
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_zstrp 0, \nb
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_zldrp 0, \nb, -16
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mrs x\ntmp, fpsr
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str w\ntmp, [\xpfpsr]
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mrs x\ntmp, fpcr
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str w\ntmp, [\xpfpsr, #4]
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.purgem savez
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.purgem savep
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.endm
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.macro sve_load nb, xpfpsr, xvqminus1 ntmp
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mrs_s x\ntmp, SYS_ZCR_EL1
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bic x\ntmp, x\ntmp, ZCR_EL1_LEN_MASK
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orr x\ntmp, x\ntmp, \xvqminus1
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msr_s SYS_ZCR_EL1, x\ntmp // self-synchronising
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.macro loadz n
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_zldrv \n, \nb, (\n) - 34
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.endm
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.macro loadp n
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_zldrp \n, \nb, (\n) - 16
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.endm
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for 0, 31, loadz
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_zldrp 0, \nb
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_zwrffr 0
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for 0, 15, loadp
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ldr w\ntmp, [\xpfpsr]
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msr fpsr, x\ntmp
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ldr w\ntmp, [\xpfpsr, #4]
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msr fpcr, x\ntmp
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.purgem loadz
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.purgem loadp
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.endm
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