9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
59 lines
1.4 KiB
ArmAsm
59 lines
1.4 KiB
ArmAsm
/* hyp-stub.S COPYRIGHT FUJITSU LIMITED 2015 */
|
|
#include <linkage.h>
|
|
#include <assembler.h>
|
|
|
|
.text
|
|
.align 11
|
|
|
|
ENTRY(__hyp_stub_vectors)
|
|
ventry el2_sync_invalid // Synchronous EL2t
|
|
ventry el2_irq_invalid // IRQ EL2t
|
|
ventry el2_fiq_invalid // FIQ EL2t
|
|
ventry el2_error_invalid // Error EL2t
|
|
|
|
ventry el2_sync_invalid // Synchronous EL2h
|
|
ventry el2_irq_invalid // IRQ EL2h
|
|
ventry el2_fiq_invalid // FIQ EL2h
|
|
ventry el2_error_invalid // Error EL2h
|
|
|
|
ventry el1_sync // Synchronous 64-bit EL1
|
|
ventry el1_irq_invalid // IRQ 64-bit EL1
|
|
ventry el1_fiq_invalid // FIQ 64-bit EL1
|
|
ventry el1_error_invalid // Error 64-bit EL1
|
|
|
|
ventry el1_sync_invalid // Synchronous 32-bit EL1
|
|
ventry el1_irq_invalid // IRQ 32-bit EL1
|
|
ventry el1_fiq_invalid // FIQ 32-bit EL1
|
|
ventry el1_error_invalid // Error 32-bit EL1
|
|
ENDPROC(__hyp_stub_vectors)
|
|
|
|
.align 11
|
|
|
|
el1_sync:
|
|
mrs x1, esr_el2
|
|
lsr x1, x1, #26
|
|
cmp x1, #0x16
|
|
b.ne 2f // Not an HVC trap
|
|
cbz x0, 1f
|
|
msr vbar_el2, x0 // Set vbar_el2
|
|
b 2f
|
|
1: mrs x0, vbar_el2 // Return vbar_el2
|
|
2: eret
|
|
ENDPROC(el1_sync)
|
|
|
|
.macro invalid_vector label
|
|
\label:
|
|
b \label
|
|
ENDPROC(\label)
|
|
.endm
|
|
|
|
invalid_vector el2_sync_invalid
|
|
invalid_vector el2_irq_invalid
|
|
invalid_vector el2_fiq_invalid
|
|
invalid_vector el2_error_invalid
|
|
invalid_vector el1_sync_invalid
|
|
invalid_vector el1_irq_invalid
|
|
invalid_vector el1_fiq_invalid
|
|
invalid_vector el1_error_invalid
|
|
|