9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
148 lines
2.6 KiB
C
148 lines
2.6 KiB
C
/* assembler.h COPYRIGHT FUJITSU LIMITED 2015-2017 */
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#ifndef __HEADER_ARM64_COMMON_ASSEMBLER_H
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#define __HEADER_ARM64_COMMON_ASSEMBLER_H
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#include <thread_info.h>
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#if defined(CONFIG_HAS_NMI)
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#include <arm-gic-v3.h>
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#endif /* defined(CONFIG_HAS_NMI) */
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#if defined(CONFIG_HAS_NMI)
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/*
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* Enable and disable pseudo NMI.
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*/
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.macro disable_nmi
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msr daifset, #2
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.endm
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.macro enable_nmi
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msr daifclr, #2
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.endm
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/*
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* Enable and disable interrupts.
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*/
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.macro disable_irq, tmp
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mov \tmp, #ICC_PMR_EL1_MASKED
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msr_s ICC_PMR_EL1, \tmp
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.endm
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.macro enable_irq, tmp
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mov \tmp, #ICC_PMR_EL1_UNMASKED
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msr_s ICC_PMR_EL1, \tmp
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.endm
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#else /* defined(CONFIG_HAS_NMI) */
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/*
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* Enable and disable pseudo NMI.
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*/
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.macro disable_nmi
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.endm
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.macro enable_nmi
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.endm
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/*
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* Enable and disable interrupts.
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*/
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.macro disable_irq, tmp
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msr daifset, #2
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.endm
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.macro enable_irq, tmp
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msr daifclr, #2
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.endm
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#endif /* defined(CONFIG_HAS_NMI) */
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/*
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* Enable and disable debug exceptions.
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*/
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.macro disable_dbg
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msr daifset, #8
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.endm
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.macro enable_dbg
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msr daifclr, #8
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.endm
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #1
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msr mdscr_el1, \tmp
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isb // Synchronise with enable_dbg
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9990:
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.endm
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.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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disable_dbg
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mrs \tmp, mdscr_el1
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orr \tmp, \tmp, #1
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msr mdscr_el1, \tmp
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b 9991f
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9990:
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #1
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msr mdscr_el1, \tmp
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isb // Synchronise with enable_dbg
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9991:
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.endm
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/*
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* Enable both debug exceptions and interrupts. This is likely to be
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* faster than two daifclr operations, since writes to this register
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* are self-synchronising.
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*/
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#if defined(CONFIG_HAS_NMI)
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.macro enable_dbg_and_irq, tmp
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enable_dbg
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enable_irq \tmp
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.endm
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#else /* defined(CONFIG_HAS_NMI) */
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.macro enable_dbg_and_irq, tmp
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msr daifclr, #(8 | 2)
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.endm
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#endif /* defined(CONFIG_HAS_NMI) */
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/*
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* Register aliases.
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*/
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lr .req x30 // link register
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/*
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* Vector entry
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*/
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.macro ventry label
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.align 7
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b \label
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.endm
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/*
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* Select code when configured for BE.
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*/
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//#ifdef CONFIG_CPU_BIG_ENDIAN
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//#define CPU_BE(code...) code
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//#else
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#define CPU_BE(code...)
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//#endif
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/*
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* Select code when configured for LE.
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*/
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//#ifdef CONFIG_CPU_BIG_ENDIAN
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//#define CPU_LE(code...)
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//#else
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#define CPU_LE(code...) code
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//#endif
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#define ENDPIPROC(x) \
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.globl __pi_##x; \
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.type __pi_##x, %function; \
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.set __pi_##x, x; \
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.size __pi_##x, . - x; \
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ENDPROC(x)
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#endif /* !__HEADER_ARM64_COMMON_ASSEMBLER_H */
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