9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/* hw_breakpoint.h COPYRIGHT FUJITSU LIMITED 2016 */
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#ifndef __HEADER_ARM64_COMMON_HW_BREAKPOINT_H
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#define __HEADER_ARM64_COMMON_HW_BREAKPOINT_H
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#include <ihk/types.h>
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int hw_breakpoint_slots(int type);
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unsigned long read_wb_reg(int reg, int n);
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void write_wb_reg(int reg, int n, unsigned long val);
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void hw_breakpoint_reset(void);
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void arch_hw_breakpoint_init(void);
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struct user_hwdebug_state;
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int arch_validate_hwbkpt_settings(long note_type, struct user_hwdebug_state *hws, size_t len);
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extern int core_num_brps;
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extern int core_num_wrps;
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/* @ref.impl include/uapi/linux/hw_breakpoint.h::HW_BREAKPOINT_LEN_n, HW_BREAKPOINT_xxx, bp_type_idx */
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enum {
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HW_BREAKPOINT_LEN_1 = 1,
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HW_BREAKPOINT_LEN_2 = 2,
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HW_BREAKPOINT_LEN_4 = 4,
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HW_BREAKPOINT_LEN_8 = 8,
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};
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enum {
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HW_BREAKPOINT_EMPTY = 0,
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HW_BREAKPOINT_R = 1,
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HW_BREAKPOINT_W = 2,
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HW_BREAKPOINT_RW = HW_BREAKPOINT_R | HW_BREAKPOINT_W,
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HW_BREAKPOINT_X = 4,
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HW_BREAKPOINT_INVALID = HW_BREAKPOINT_RW | HW_BREAKPOINT_X,
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};
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enum bp_type_idx {
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TYPE_INST = 0,
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TYPE_DATA = 1,
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TYPE_MAX
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};
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/* Breakpoint */
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#define ARM_BREAKPOINT_EXECUTE 0
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/* Watchpoints */
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#define ARM_BREAKPOINT_LOAD 1
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#define ARM_BREAKPOINT_STORE 2
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#define AARCH64_ESR_ACCESS_MASK (1 << 6)
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/* Privilege Levels */
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#define AARCH64_BREAKPOINT_EL1 1
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#define AARCH64_BREAKPOINT_EL0 2
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/* Lengths */
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#define ARM_BREAKPOINT_LEN_1 0x1
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#define ARM_BREAKPOINT_LEN_2 0x3
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#define ARM_BREAKPOINT_LEN_4 0xf
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#define ARM_BREAKPOINT_LEN_8 0xff
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/* @ref.impl arch/arm64/include/asm/hw_breakpoint.h::ARM_MAX_[BRP|WRP] */
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/*
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* Limits.
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* Changing these will require modifications to the register accessors.
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*/
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#define ARM_MAX_BRP 16
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#define ARM_MAX_WRP 16
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/* @ref.impl arch/arm64/include/asm/hw_breakpoint.h::AARCH64_DBG_REG_xxx */
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/* Virtual debug register bases. */
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#define AARCH64_DBG_REG_BVR 0
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#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
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#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
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#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
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/* @ref.impl arch/arm64/include/asm/hw_breakpoint.h::AARCH64_DBG_REG_NAME_xxx */
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/* Debug register names. */
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#define AARCH64_DBG_REG_NAME_BVR "bvr"
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#define AARCH64_DBG_REG_NAME_BCR "bcr"
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#define AARCH64_DBG_REG_NAME_WVR "wvr"
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#define AARCH64_DBG_REG_NAME_WCR "wcr"
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/* @ref.impl arch/arm64/include/asm/hw_breakpoint.h::AARCH64_DBG_[READ|WRITE] */
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/* Accessor macros for the debug registers. */
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#define AARCH64_DBG_READ(N, REG, VAL) do {\
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asm volatile("mrs %0, dbg" REG #N "_el1" : "=r" (VAL));\
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} while (0)
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#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
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asm volatile("msr dbg" REG #N "_el1, %0" :: "r" (VAL));\
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} while (0)
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#endif /* !__HEADER_ARM64_COMMON_HW_BREAKPOINT_H */
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