128 lines
5.1 KiB
Plaintext
128 lines
5.1 KiB
Plaintext
*** C1384T01 start *******************************
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base mbind: 0x100000290000 - 0x1000002c0000 policy:2
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new mbind: 0x100000280000 - 0x1000002b0000 policy:0
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[OK] policies are expected
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*** C1384T01 PASSED ******************************
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*** C1384T02 start *******************************
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base mbind: 0x100000290000 - 0x1000002c0000 policy:2
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new mbind: 0x100000290000 - 0x1000002c0000 policy:0
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[OK] policies are expected
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*** C1384T02 PASSED ******************************
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*** C1384T03 start *******************************
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base mbind: 0x100000280000 - 0x1000002d0000 policy:2
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new mbind: 0x100000290000 - 0x1000002c0000 policy:0
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[OK] policies are expected
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*** C1384T03 PASSED ******************************
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*** C1384T04 start *******************************
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base mbind: 0x100000290000 - 0x1000002c0000 policy:2
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new mbind: 0x1000002a0000 - 0x1000002d0000 policy:0
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[OK] policies are expected
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*** C1384T04 PASSED ******************************
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*** C1384T05 start *******************************
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base1 mbind: 0x100000290000 - 0x1000002a0000 policy:2
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base2 mbind: 0x100000290000 - 0x1000002c0000 policy:2
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new mbind: 0x100000280000 - 0x1000002d0000 policy:0
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[OK] policies are expected
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*** C1384T05 PASSED ******************************
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*** C1384T06 start *******************************
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base1 mbind: 0x100000280000 - 0x1000002b0000 policy:2
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base2 mbind: 0x1000002b0000 - 0x1000002d0000 policy:2
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new mbind: 0x100000290000 - 0x1000002c0000 policy:0
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[OK] policies are expected
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*** C1384T06 PASSED ******************************
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*** C1384T07 start *******************************
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vma02 0 TINFO : pid = 46749 addr = 0x1000002c0000
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vma02 0 TINFO : start = 0x1000002c0000, end = 0x1000002f0000
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vma02 1 TPASS : only 1 VMA.
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*** C1384T07 PASSED (1)
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*** C1384T08 start *******************************
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tst_test.c:1096: INFO: Timeout per run is 0h 05m 00s
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mbind01.c:181: INFO: case MPOL_DEFAULT
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_DEFAULT (target exists)
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_BIND (no target)
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_BIND
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_INTERLEAVE (no target)
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_INTERLEAVE
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_PREFERRED (no target)
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_PREFERRED
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case UNKNOWN_POLICY
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_DEFAULT (invalid flags)
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mbind01.c:230: PASS: Test passed
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mbind01.c:181: INFO: case MPOL_PREFERRED (invalid nodemask)
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mbind01.c:230: PASS: Test passed
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Summary:
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passed 11
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failed 0
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skipped 0
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warnings 0
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*** C1384T08 PASSED (11)
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*** C1384T09 start *******************************
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=0 errno=0 (Success)
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RESULT: return value(ret)=0 errno=0 (Success)
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EXPECT: return value(ret)=-1 errno=14 (Bad address)
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RESULT: return value(ret)=-1 errno=14 (Bad address)
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EXPECT: return value(ret)=-1 errno=22 (Invalid argument)
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RESULT: return value(ret)=-1 errno=22 (Invalid argument)
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get_mempolicy01 0 TINFO : (case00) START
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get_mempolicy01 1 TPASS : (case00) END
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get_mempolicy01 0 TINFO : (case01) START
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get_mempolicy01 2 TPASS : (case01) END
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get_mempolicy01 0 TINFO : (case02) START
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get_mempolicy01 3 TPASS : (case02) END
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get_mempolicy01 0 TINFO : (case03) START
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get_mempolicy01 4 TPASS : (case03) END
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get_mempolicy01 0 TINFO : (case04) START
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get_mempolicy01 5 TPASS : (case04) END
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get_mempolicy01 0 TINFO : (case05) START
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get_mempolicy01 6 TPASS : (case05) END
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get_mempolicy01 0 TINFO : (case06) START
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get_mempolicy01 7 TPASS : (case06) END
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get_mempolicy01 0 TINFO : (case07) START
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get_mempolicy01 8 TPASS : (case07) END
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get_mempolicy01 0 TINFO : (case08) START
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get_mempolicy01 9 TPASS : (case08) END
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get_mempolicy01 0 TINFO : (case09) START
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get_mempolicy01 10 TPASS : (case09) END
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get_mempolicy01 0 TINFO : (case10) START
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get_mempolicy01 11 TPASS : (case10) END
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get_mempolicy01 0 TINFO : (case11) START
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get_mempolicy01 12 TPASS : (case11) END
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*** C1384T09 PASSED (12)
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