9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/* arch-perfctr.h COPYRIGHT FUJITSU LIMITED 2016-2017 */
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#ifndef __ARCH_PERFCTR_H__
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#define __ARCH_PERFCTR_H__
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#include <ihk/types.h>
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#include <ihk/cpu.h>
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/* @ref.impl arch/arm64/include/asm/pmu.h */
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struct arm_pmu {
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struct ihk_mc_interrupt_handler* handler;
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uint32_t (*read_counter)(int);
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void (*write_counter)(int, uint32_t);
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void (*reset)(void*);
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int (*enable_pmu)(void);
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void (*disable_pmu)(void);
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int (*enable_counter)(int);
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int (*disable_counter)(int);
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int (*enable_intens)(int);
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int (*disable_intens)(int);
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int (*set_event_filter)(unsigned long*, int);
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void (*write_evtype)(int, uint32_t);
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int (*get_event_idx)(int, unsigned long);
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int (*map_event)(uint32_t, uint64_t);
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int num_events;
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};
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static inline const struct arm_pmu* get_cpu_pmu(void)
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{
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extern struct arm_pmu cpu_pmu;
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return &cpu_pmu;
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}
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int arm64_init_perfctr(void);
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int arm64_enable_pmu(void);
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void arm64_disable_pmu(void);
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int armv8pmu_init(struct arm_pmu* cpu_pmu);
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/* TODO[PMU]: 共通部に定義があっても良い。今後の動向を見てここの定義を削除する */
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/*
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* Generalized hardware cache events:
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*
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* { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
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* { read, write, prefetch } x
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* { accesses, misses }
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*/
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enum perf_hw_cache_id {
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PERF_COUNT_HW_CACHE_L1D = 0,
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PERF_COUNT_HW_CACHE_L1I = 1,
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PERF_COUNT_HW_CACHE_LL = 2,
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PERF_COUNT_HW_CACHE_DTLB = 3,
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PERF_COUNT_HW_CACHE_ITLB = 4,
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PERF_COUNT_HW_CACHE_BPU = 5,
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PERF_COUNT_HW_CACHE_NODE = 6,
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PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
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};
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enum perf_hw_cache_op_id {
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PERF_COUNT_HW_CACHE_OP_READ = 0,
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PERF_COUNT_HW_CACHE_OP_WRITE = 1,
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PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
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PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
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};
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enum perf_hw_cache_op_result_id {
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PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
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PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
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PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
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};
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#endif
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