9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
197 lines
6.6 KiB
C
197 lines
6.6 KiB
C
/* pgtable-hwdef.h COPYRIGHT FUJITSU LIMITED 2015 */
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#ifndef __HEADER_ARM64_COMMON_PGTABLE_HWDEF_H
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#define __HEADER_ARM64_COMMON_PGTABLE_HWDEF_H
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#ifndef __HEADER_ARM64_COMMON_ARCH_MEMORY_H
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# error arch-memory.h
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#endif
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#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
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/*
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* PMD_SHIFT determines the size a level 2 page table entry can map.
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*/
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#if CONFIG_ARM64_PGTABLE_LEVELS > 2
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# define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3)
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# define PMD_SIZE (1UL << PMD_SHIFT)
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# define PMD_MASK (~(PMD_SIZE-1))
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# define PTRS_PER_PMD PTRS_PER_PTE
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#endif
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/*
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* PUD_SHIFT determines the size a level 1 page table entry can map.
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*/
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#if CONFIG_ARM64_PGTABLE_LEVELS > 3
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# define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3)
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# define PUD_SIZE (1UL << PUD_SHIFT)
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# define PUD_MASK (~(PUD_SIZE-1))
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# define PTRS_PER_PUD PTRS_PER_PTE
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#endif
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map
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* (depending on the configuration, this level can be 0, 1 or 2).
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*/
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#define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_ARM64_PGTABLE_LEVELS + 3)
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
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/*
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* Section address mask and size definitions.
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*/
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#define SECTION_SHIFT PMD_SHIFT
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#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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/*
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* Level 2 descriptor (PMD).
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*/
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#define PMD_TYPE_MASK (UL(3) << 0)
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#define PMD_TYPE_FAULT (UL(0) << 0)
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#define PMD_TYPE_TABLE (UL(3) << 0)
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#define PMD_TYPE_SECT (UL(1) << 0)
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#define PMD_TABLE_BIT (UL(1) << 1)
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/*
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* Table (D_Block)
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*/
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#define PMD_TBL_PXNT (UL(1) << 59)
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#define PMD_TBL_UXNT (UL(1) << 60)
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#define PMD_TBL_APT_USER (UL(1) << 61) /* 0:Access at EL0 permitted, 1:Access at EL0 not permitted */
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#define PMD_TBL_APT_RDONLY (UL(2) << 61) /* 0:read write(EL0-3) 0:read only(EL0-3) */
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#define PMD_TBL_NST (UL(1) << 63) /* 0:secure, 1:non-secure */
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/*
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* Section (D_Page)
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*/
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#define PMD_SECT_VALID (UL(1) << 0)
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#define PMD_SECT_PROT_NONE (UL(1) << 58)
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#define PMD_SECT_USER (UL(1) << 6) /* AP[1] */
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#define PMD_SECT_RDONLY (UL(1) << 7) /* AP[2] */
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#define PMD_SECT_S (UL(3) << 8)
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#define PMD_SECT_AF (UL(1) << 10)
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#define PMD_SECT_NG (UL(1) << 11)
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#define PMD_SECT_PXN (UL(1) << 53)
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#define PMD_SECT_UXN (UL(1) << 54)
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_ATTRINDX(t) (UL(t) << 2)
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#define PMD_ATTRINDX_MASK (UL(7) << 2)
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/*
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* Level 3 descriptor (PTE).
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*/
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#define PTE_TYPE_MASK (UL(3) << 0)
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#define PTE_TYPE_FAULT (UL(0) << 0)
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#define PTE_TYPE_PAGE (UL(3) << 0)
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#define PTE_TABLE_BIT (UL(1) << 1)
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#define PTE_USER (UL(1) << 6) /* AP[1] */
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#define PTE_RDONLY (UL(1) << 7) /* AP[2] */
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#define PTE_SHARED (UL(3) << 8) /* SH[1:0], inner shareable */
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#define PTE_AF (UL(1) << 10) /* Access Flag */
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#define PTE_NG (UL(1) << 11) /* nG */
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#define PTE_PXN (UL(1) << 53) /* Privileged XN */
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#define PTE_UXN (UL(1) << 54) /* User XN */
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/* Software defined PTE bits definition.*/
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#define PTE_VALID (UL(1) << 0)
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#define PTE_FILE (UL(1) << 2) /* only when !pte_present() */
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#define PTE_DIRTY (UL(1) << 55)
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#define PTE_SPECIAL (UL(1) << 56)
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#define PTE_WRITE (UL(1) << 57)
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#define PTE_PROT_NONE (UL(1) << 58) /* only when !PTE_VALID */
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PTE_ATTRINDX(t) (UL(t) << 2)
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#define PTE_ATTRINDX_MASK (UL(7) << 2)
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/*
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* Highest possible physical address supported.
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*/
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#define PHYS_MASK_SHIFT (48)
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#define PHYS_MASK (((UL(1) << PHYS_MASK_SHIFT) - 1) & PAGE_MASK)
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/*
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* TCR flags.
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*/
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#define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0))
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#define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
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#define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
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#define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
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#define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
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#define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
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#define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
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#define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
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#define TCR_TG0_4K (UL(0) << 14)
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#define TCR_TG0_64K (UL(1) << 14)
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#define TCR_TG0_16K (UL(2) << 14)
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#define TCR_TG1_16K (UL(1) << 30)
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#define TCR_TG1_4K (UL(2) << 30)
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#define TCR_TG1_64K (UL(3) << 30)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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/*
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* Memory types available.
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*/
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#define MT_DEVICE_nGnRnE 0
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#define MT_DEVICE_nGnRE 1
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#define MT_DEVICE_GRE 2
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#define MT_NORMAL_NC 3
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#define MT_NORMAL 4
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/*
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* page table entry attribute set.
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*/
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
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#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
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#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
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#define PAGE_KERNEL (_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
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#define PAGE_KERNEL_EXEC (_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
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#define PAGE_NONE (((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
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#define PAGE_SHARED (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
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#define PAGE_SHARED_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
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#define PAGE_COPY (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
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#define PAGE_COPY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
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#define PAGE_READONLY (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
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#define PAGE_READONLY_EXEC (_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY_EXEC
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#define __P101 PAGE_READONLY_EXEC
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#define __P110 PAGE_COPY_EXEC
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#define __P111 PAGE_COPY_EXEC
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY_EXEC
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#define __S101 PAGE_READONLY_EXEC
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#define __S110 PAGE_SHARED_EXEC
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#define __S111 PAGE_SHARED_EXEC
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#endif /* !__HEADER_ARM64_COMMON_PGTABLE_HWDEF_H */
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