53 lines
1.1 KiB
C
53 lines
1.1 KiB
C
/**
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* \file cpu.h
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* License details are found in the file LICENSE.
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* \brief
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* Declare architecture-dependent types and functions to control CPU.
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* \author Gou Nakamura <go.nakamura.yw@hitachi-solutions.com>
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* Copyright (C) 2015 RIKEN AICS
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*/
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/*
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* HISTORY
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*/
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#ifndef ARCH_CPU_H
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#define ARCH_CPU_H
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() barrier()
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#define arch_barrier() asm volatile("" : : : "memory")
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static inline unsigned long read_tsc(void)
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{
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unsigned int low, high;
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asm volatile("rdtsc" : "=a"(low), "=d"(high));
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return (low | ((unsigned long)high << 32));
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}
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#define smp_store_release(p, v) \
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({ \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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})
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void arch_flush_icache_all(void);
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#endif /* ARCH_CPU_H */
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