9989f41fd3
- add arm64 dependent codes with GICv3 and SVE support - fix bugs based on architecture separation requests
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/* arm-gic-v2.h COPYRIGHT FUJITSU LIMITED 2015-2017 */
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/*
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* include/linux/irqchip/arm-gic.h
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_IRQCHIP_ARM_GIC_H
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#define __LINUX_IRQCHIP_ARM_GIC_H
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/* check config */
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#if defined(CONFIG_HAS_NMI) && !defined(CONFIG_ARM_GIC_V3)
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# error GICv2 is not support NMI
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#endif
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/* @ref.impl include/linux/irqchip/arm-gic.h */
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#define GIC_CPU_CTRL 0x00
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#define GIC_CPU_PRIMASK 0x04
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#define GIC_CPU_BINPOINT 0x08
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#define GIC_CPU_INTACK 0x0c
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#define GIC_CPU_EOI 0x10
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#define GIC_CPU_RUNNINGPRI 0x14
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#define GIC_CPU_HIGHPRI 0x18
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#define GIC_CPU_ALIAS_BINPOINT 0x1c
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#define GIC_CPU_ACTIVEPRIO 0xd0
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#define GIC_CPU_IDENT 0xfc
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#define GICC_ENABLE 0x1
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#define GICC_INT_PRI_THRESHOLD 0xf0
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#define GICC_IAR_INT_ID_MASK 0x3ff
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#define GICC_INT_SPURIOUS 1023
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#define GICC_DIS_BYPASS_MASK 0x1e0
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#define GIC_DIST_CTRL 0x000
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#define GIC_DIST_CTR 0x004
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#define GIC_DIST_IGROUP 0x080
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#define GIC_DIST_ENABLE_SET 0x100
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#define GIC_DIST_ENABLE_CLEAR 0x180
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#define GIC_DIST_PENDING_SET 0x200
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#define GIC_DIST_PENDING_CLEAR 0x280
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#define GIC_DIST_ACTIVE_SET 0x300
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#define GIC_DIST_ACTIVE_CLEAR 0x380
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#define GIC_DIST_PRI 0x400
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#define GIC_DIST_TARGET 0x800
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#define GIC_DIST_CONFIG 0xc00
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#define GIC_DIST_SOFTINT 0xf00
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#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
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#define GIC_DIST_SGI_PENDING_SET 0xf20
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#define GICD_ENABLE 0x1
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#define GICD_DISABLE 0x0
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#define GICD_INT_ACTLOW_LVLTRIG 0x0
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#define GICD_INT_EN_CLR_X32 0xffffffff
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#define GICD_INT_EN_SET_SGI 0x0000ffff
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#define GICD_INT_EN_CLR_PPI 0xffff0000
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#ifdef CONFIG_HAS_NMI
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#define GICD_INT_NMI_PRI 0x40
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#define GICD_INT_DEF_PRI 0xc0
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#else
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#define GICD_INT_DEF_PRI 0xa0
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#endif
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#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
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(GICD_INT_DEF_PRI << 16) |\
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(GICD_INT_DEF_PRI << 8) |\
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GICD_INT_DEF_PRI)
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#define GICH_HCR 0x0
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#define GICH_VTR 0x4
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#define GICH_VMCR 0x8
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#define GICH_MISR 0x10
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#define GICH_EISR0 0x20
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#define GICH_EISR1 0x24
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#define GICH_ELRSR0 0x30
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#define GICH_ELRSR1 0x34
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#define GICH_APR 0xf0
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#define GICH_LR0 0x100
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#define GICH_HCR_EN (1 << 0)
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#define GICH_HCR_UIE (1 << 1)
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#define GICH_LR_VIRTUALID (0x3ff << 0)
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#define GICH_LR_PHYSID_CPUID_SHIFT (10)
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#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
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#define GICH_LR_STATE (3 << 28)
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#define GICH_LR_PENDING_BIT (1 << 28)
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#define GICH_LR_ACTIVE_BIT (1 << 29)
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#define GICH_LR_EOI (1 << 19)
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#define GICH_VMCR_CTRL_SHIFT 0
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#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT)
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#define GICH_VMCR_PRIMASK_SHIFT 27
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#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
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#define GICH_VMCR_BINPOINT_SHIFT 21
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#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT)
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#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18
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#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
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#define GICH_MISR_EOI (1 << 0)
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#define GICH_MISR_U (1 << 1)
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#endif /* __LINUX_IRQCHIP_ARM_GIC_H */
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