d4d78e9c61
This includes the following fixes: * fix build of arch/arm64/kernel/vdso Change-Id: I73b05034d29f7f8731ac17f9736edbba4fb2c639
50 lines
1.0 KiB
C
50 lines
1.0 KiB
C
/* archdep.c COPYRIGHT FUJITSU LIMITED 2017 */
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#include <asm/ptrace.h>
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/* @ref.impl arch/arm64/include/asm/atomic_ll_sc.h::__ll_sc___cmpxchg_case_mb_8() */
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unsigned long compare_and_swap(unsigned long *addr,
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unsigned long old, unsigned long new)
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{
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unsigned long tmp, oldval;
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asm volatile(
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" prfm pstl1strm, %2\n"
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"1: ldxr %1, %2\n"
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" eor %0, %1, %3\n"
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" cbnz %0, 2f\n"
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" stlxr %w0, %4, %2\n"
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" cbnz %w0, 1b\n"
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" dmb ish\n"
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" mov %1, %3\n"
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"2:"
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: "=&r"(tmp), "=&r"(oldval), "+Q"(*addr)
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: "Lr"(old), "r"(new)
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: "memory");
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return oldval;
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}
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/* @ref.impl arch/arm64/include/asm/atomic_ll_sc.h::__ll_sc___cmpxchg_case_mb_4() */
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unsigned int compare_and_swap_int(unsigned int *addr,
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unsigned int old, unsigned int new)
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{
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unsigned long tmp, oldval;
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asm volatile(
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" prfm pstl1strm, %2\n"
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"1: ldxr %w1, %2\n"
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" eor %w0, %w1, %w3\n"
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" cbnz %w0, 2f\n"
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" stlxr %w0, %w4, %2\n"
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" cbnz %w0, 1b\n"
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" dmb ish\n"
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" mov %w1, %w3\n"
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"2:"
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: "=&r"(tmp), "=&r"(oldval), "+Q"(*addr)
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: "Lr"(old), "r"(new)
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: "memory");
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return oldval;
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}
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