119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* io.h COPYRIGHT FUJITSU LIMITED 2015 */
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/*
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* Based on arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IO_H
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#define __ASM_IO_H
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#include <ihk/types.h>
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#ifdef __KERNEL__
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/*
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* Generic IO read/write. These perform native-endian accesses.
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*/
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static inline void __raw_writeb(uint8_t val, volatile void *addr)
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{
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asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writew(uint16_t val, volatile void *addr)
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{
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asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writel(uint32_t val, volatile void *addr)
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{
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asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline void __raw_writeq(uint64_t val, volatile void *addr)
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{
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asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
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}
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static inline uint8_t __raw_readb(const volatile void *addr)
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{
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uint8_t val;
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asm volatile("ldarb %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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static inline uint16_t __raw_readw(const volatile void *addr)
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{
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uint16_t val;
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asm volatile("ldarh %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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static inline uint32_t __raw_readl(const volatile void *addr)
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{
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uint32_t val;
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asm volatile("ldar %w0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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static inline uint64_t __raw_readq(const volatile void *addr)
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{
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uint64_t val;
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asm volatile("ldar %0, [%1]"
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: "=r" (val) : "r" (addr));
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ uint8_t __v = (uint8_t)__raw_readb(c); __v; })
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#define readw_relaxed(c) ({ uint16_t __v = (uint16_t)__raw_readw(c); __v; })
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#define readl_relaxed(c) ({ uint32_t __v = (uint32_t)__raw_readl(c); __v; })
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#define readq_relaxed(c) ({ uint64_t __v = (uint64_t)__raw_readq(c); __v; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb((uint8_t)(v),(c)))
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#define writew_relaxed(v,c) ((void)__raw_writew((uint16_t)(v),(c)))
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#define writel_relaxed(v,c) ((void)__raw_writel((uint32_t)(v),(c)))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((uint64_t)(v),(c)))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ uint8_t __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ uint16_t __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ uint32_t __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ uint64_t __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
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#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
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#endif /* __KERNEL__ */
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#endif /* __ASM_IO_H */
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