diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala
index d62b096..86e98cf 100644
--- a/src/main/scala/micore/Core.scala
+++ b/src/main/scala/micore/Core.scala
@@ -94,4 +94,36 @@ class Core extends Module {
     (exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr)
   stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
 
+  val id_inst =
+    Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
+
+  val id_rs1_addr = id_inst(25, 21)
+  val id_rs2_addr = id_inst(20, 16)
+  val id_wb_addr = id_inst(15, 11)
+  val mem_wb_data = Wire(UInt(WORD_LEN.W))
+  val id_rs1_data = MuxCase(
+    regfile(id_rs1_addr),
+    Seq(
+      (id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W),
+      ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
+      ((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
+    )
+  )
+  val id_rs2_data = MuxCase(
+    regfile(id_rs2_addr),
+    Seq(
+      (id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W),
+      ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
+      ((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
+    )
+  )
+
+  val id_imm_i = id_inst(15, 0)
+  val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
+  val id_imm_s = id_inst(15, 0)
+  val id_imm_s_sext = Cat(Fill(16, id_imm_s(15)), id_imm_s)
+  val id_imm_b = id_inst(15, 0)
+  val id_imm_b_sext = Cat(Fill(16, id_imm_b(15)), id_imm_b)
+  val id_imm_j = id_inst(25, 0)
+
 }