From 582917df99abf89b00b3c50592fce7f679aafd93 Mon Sep 17 00:00:00 2001 From: CGH0S7 <776459475@qq.com> Date: Sun, 29 Dec 2024 16:20:43 +0800 Subject: [PATCH] Some bugs need to be fixed. --- Core.sv | 315 ++++++++++++ Memory.sv | 88 ++++ Regfile.sv | 58 +++ Top.sv | 434 ++-------------- build.sbt | 15 +- micore.xdc | 10 +- ...15e5.cache => $1b2e4c70cf01ae9e66b4.cache} | 0 ...091b.cache => $2f10d7978379a0259464.cache} | 0 ...2b89.cache => $ae36708fca0f6afe50e3.cache} | 0 ...7efc.cache => $c326be24cfa0b447c75b.cache} | 0 src/hex/mem.hex | 40 +- src/test/scala/micore/MicoreSpec.scala | 14 +- .../update/update_cache_2.13/inputs | 2 +- .../update/update_cache_2.13/output | 2 +- .../streams/update_cache_2.13/input_dsp | 2 +- .../streams/update_cache_2.13/output_dsp | 2 +- .../updateClassifiers/_global/streams/out | 4 +- .../_global/streams/update_cache_2.13/inputs | 2 +- .../_global/streams/update_cache_2.13/output | 2 +- .../compile/bloopGenerate/_global/streams/out | 2 +- .../compileIncremental/_global/streams/out | 62 +-- .../compile/incOptions/_global/streams/out | 17 - .../test/bloopGenerate/_global/streams/out | 2 +- .../_global/streams/export | 2 +- .../managedClasspath/_global/streams/export | 2 +- .../TopOrigin.lo.fir | 480 ++++++++++++++++++ testbench.sv | 85 ++++ 27 files changed, 1106 insertions(+), 536 deletions(-) create mode 100755 Core.sv create mode 100755 Memory.sv create mode 100755 Regfile.sv rename project/target/config-classes/{$0dd3447347b5224615e5.cache => $1b2e4c70cf01ae9e66b4.cache} (100%) rename project/target/config-classes/{$6becda8e2cd53152091b.cache => $2f10d7978379a0259464.cache} (100%) rename project/target/config-classes/{$afff5d25069ab86e2b89.cache => $ae36708fca0f6afe50e3.cache} (100%) rename project/target/config-classes/{$cc949d4e621f82777efc.cache => $c326be24cfa0b447c75b.cache} (100%) create mode 100755 test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir create mode 100755 testbench.sv diff --git a/Core.sv b/Core.sv new file mode 100755 index 0000000..cc6c176 --- /dev/null +++ b/Core.sv @@ -0,0 +1,315 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/28 11:25:38 +// Design Name: +// Module Name: Core +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Core( + input clock, + reset, + output [31:0] io_imem_addr, + input [31:0] io_imem_inst, + output [31:0] io_dmem_addr, + input [31:0] io_dmem_rdata, + output io_dmem_wen, + output [31:0] io_dmem_wdata, + output io_exit, + output [31:0] s0_value + ); + + wire [31:0] _regfile_ext_R0_data; + wire [31:0] _regfile_ext_R1_data; + reg [31:0] id_reg_pc; + reg [31:0] id_reg_inst; + reg [31:0] exe_reg_pc; + reg [4:0] exe_reg_wb_addr; + reg [31:0] exe_reg_op1_data; + reg [31:0] exe_reg_op2_data; + reg [31:0] exe_reg_rs2_data; + reg [4:0] exe_reg_exe_fun; + reg [1:0] exe_reg_mem_wen; + reg [1:0] exe_reg_rf_wen; + reg [2:0] exe_reg_wb_sel; + reg [31:0] exe_reg_imm_b_sext; + reg [31:0] mem_reg_pc; + reg [4:0] mem_reg_wb_addr; + reg [31:0] mem_reg_alu_out; + reg [31:0] mem_reg_rs2_data; + reg [1:0] mem_reg_rf_wen; + reg [2:0] mem_reg_wb_sel; + reg [1:0] mem_reg_mem_wen; + reg [4:0] wb_reg_wb_addr; + reg [1:0] wb_reg_rf_wen; + reg [31:0] wb_reg_wb_data; + reg [31:0] if_reg_pc; + wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; + wire exe_br_flg = + exe_reg_exe_fun == 5'hC + ? exe_reg_op1_data != exe_reg_op2_data + : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data; + wire exe_jmp_flg = exe_reg_wb_sel == 3'h3; + always @(posedge clock) begin + automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg; + automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; + automatic logic stall_flg; + automatic logic [31:0] id_inst; + automatic logic _id_rs2_data_T_2; + automatic logic _id_rs2_data_T; + automatic logic [31:0] _id_rs2_data_T_8; + automatic logic [16:0] _GEN; + automatic logic _csignals_T_5; + automatic logic [19:0] _GEN_0; + automatic logic _csignals_T_7; + automatic logic _csignals_T_9; + automatic logic _csignals_T_11; + automatic logic _csignals_T_13; + automatic logic _csignals_T_15; + automatic logic _csignals_T_17; + automatic logic _csignals_T_19; + automatic logic [16:0] _GEN_1; + automatic logic _csignals_T_21; + automatic logic _csignals_T_23; + automatic logic _csignals_T_25; + automatic logic _csignals_T_27; + automatic logic _csignals_T_29; + automatic logic _csignals_T_31; + automatic logic _csignals_T_33; + automatic logic _csignals_T_35; + automatic logic _csignals_T_37; + automatic logic _csignals_T_39; + automatic logic _GEN_2; + automatic logic _GEN_3; + automatic logic [1:0] csignals_1; + automatic logic [2:0] _csignals_T_95; + automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]}; + automatic logic [62:0] _exe_alu_out_T_8 = + {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; + automatic logic [31:0] exe_alu_out; + stall_flg = + _id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) + & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T + & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; + id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; + _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; + _id_rs2_data_T = id_reg_inst[20:16] == 5'h0; + _id_rs2_data_T_8 = + id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 + ? mem_reg_alu_out + : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 + ? wb_reg_wb_data + : _regfile_ext_R0_data; + _GEN = {id_inst[31:26], id_inst[10:0]}; + _csignals_T_5 = _GEN == 17'h20; + _GEN_0 = {id_inst[31:28], id_inst[15:0]}; + _csignals_T_7 = _GEN_0 == 20'h80000; + _csignals_T_9 = _GEN == 17'h22; + _csignals_T_11 = _GEN == 17'h24; + _csignals_T_13 = _GEN == 17'h25; + _csignals_T_15 = _GEN == 17'h26; + _csignals_T_17 = _GEN_0 == 20'hC0000; + _csignals_T_19 = _GEN_0 == 20'hD0000; + _GEN_1 = {id_inst[30:20], id_inst[5:0]}; + _csignals_T_21 = _GEN_1 == 17'h0; + _csignals_T_23 = _GEN_1 == 17'h2; + _csignals_T_25 = _GEN_1 == 17'h3; + _csignals_T_27 = _GEN == 17'h2A; + _csignals_T_29 = _GEN_0 == 20'h40000; + _csignals_T_31 = _GEN_0 == 20'h50000; + _csignals_T_33 = id_inst == 32'hC000000; + _csignals_T_35 = _GEN_0 == 20'h8; + _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000; + _csignals_T_39 = id_inst == 32'h0; + _GEN_2 = _csignals_T_29 | _csignals_T_31; + _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2; + csignals_1 = + _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 + | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 + ? 2'h0 + : _csignals_T_33 + ? 2'h1 + : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0}; + _csignals_T_95 = + _csignals_T_5 + ? 3'h1 + : _csignals_T_7 + ? 3'h2 + : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 + ? 3'h1 + : _csignals_T_17 | _csignals_T_19 + ? 3'h2 + : _GEN_3 + ? 3'h1 + : _csignals_T_33 + ? 3'h4 + : _csignals_T_35 + ? 3'h0 + : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39}; + exe_alu_out = + exe_reg_exe_fun == 5'hE + ? exe_reg_op1_data + : exe_reg_exe_fun == 5'h9 + ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} + : exe_reg_exe_fun == 5'h8 + ? $signed($signed(exe_reg_op1_data) >>> _GEN_4) + : exe_reg_exe_fun == 5'h7 + ? exe_reg_op1_data >> _GEN_4 + : exe_reg_exe_fun == 5'h6 + ? _exe_alu_out_T_8[31:0] + : exe_reg_exe_fun == 5'h5 + ? exe_reg_op1_data ^ exe_reg_op2_data + : exe_reg_exe_fun == 5'h4 + ? exe_reg_op1_data | exe_reg_op2_data + : exe_reg_exe_fun == 5'h3 + ? exe_reg_op1_data & exe_reg_op2_data + : exe_reg_exe_fun == 5'h2 + ? exe_reg_op1_data - exe_reg_op2_data + : exe_reg_exe_fun == 5'h1 + ? exe_reg_op1_data + exe_reg_op2_data + : 32'h0; + if (~stall_flg) + id_reg_pc <= if_reg_pc; + if (_id_inst_T) + id_reg_inst <= 32'h0; + else if (~stall_flg) + id_reg_inst <= io_imem_inst; + exe_reg_pc <= id_reg_pc; + exe_reg_wb_addr <= id_reg_inst[15:11]; + if (csignals_1 == 2'h0) + exe_reg_op1_data <= + id_reg_inst[25:21] == 5'h0 + ? 32'h0 + : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2 + ? mem_reg_alu_out + : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5 + ? wb_reg_wb_data + : _regfile_ext_R1_data; + else if (csignals_1 == 2'h1) + exe_reg_op1_data <= id_reg_pc; + else + exe_reg_op1_data <= 32'h0; + if (_csignals_T_95 == 3'h5) + exe_reg_op2_data <= {id_inst[15:0], 16'h0}; + else if (_csignals_T_95 == 3'h4) + exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0}; + else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2) + exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]}; + else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T) + exe_reg_op2_data <= 32'h0; + else + exe_reg_op2_data <= _id_rs2_data_T_8; + exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8; + if (_csignals_T_5 | _csignals_T_7) + exe_reg_exe_fun <= 5'h1; + else if (_csignals_T_9) + exe_reg_exe_fun <= 5'h2; + else if (_csignals_T_11) + exe_reg_exe_fun <= 5'h3; + else if (_csignals_T_13) + exe_reg_exe_fun <= 5'h4; + else if (_csignals_T_15) + exe_reg_exe_fun <= 5'h5; + else if (_csignals_T_17) + exe_reg_exe_fun <= 5'h3; + else if (_csignals_T_19) + exe_reg_exe_fun <= 5'h4; + else if (_csignals_T_21) + exe_reg_exe_fun <= 5'h6; + else if (_csignals_T_23) + exe_reg_exe_fun <= 5'h7; + else if (_csignals_T_25) + exe_reg_exe_fun <= 5'h8; + else if (_csignals_T_27) + exe_reg_exe_fun <= 5'h9; + else if (_csignals_T_29) + exe_reg_exe_fun <= 5'hB; + else if (_csignals_T_31) + exe_reg_exe_fun <= 5'hC; + else if (_csignals_T_33) + exe_reg_exe_fun <= 5'h1; + else if (_csignals_T_35) + exe_reg_exe_fun <= 5'hE; + else + exe_reg_exe_fun <= {4'h0, _csignals_T_37}; + exe_reg_mem_wen <= 2'h0; + if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 + | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 + | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin + exe_reg_rf_wen <= 2'h1; + exe_reg_wb_sel <= 3'h1; + end + else if (_GEN_2) begin + exe_reg_rf_wen <= 2'h0; + exe_reg_wb_sel <= 3'h0; + end + else if (_csignals_T_33) begin + exe_reg_rf_wen <= 2'h1; + exe_reg_wb_sel <= 3'h3; + end + else if (_csignals_T_35) begin + exe_reg_rf_wen <= 2'h0; + exe_reg_wb_sel <= 3'h0; + end + else begin + exe_reg_rf_wen <= {1'h0, _csignals_T_37}; + exe_reg_wb_sel <= {2'h0, _csignals_T_37}; + end + exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]}; + mem_reg_pc <= exe_reg_pc; + mem_reg_wb_addr <= exe_reg_wb_addr; + mem_reg_alu_out <= exe_alu_out; + mem_reg_rs2_data <= exe_reg_rs2_data; + mem_reg_rf_wen <= exe_reg_rf_wen; + mem_reg_wb_sel <= exe_reg_wb_sel; + mem_reg_mem_wen <= exe_reg_mem_wen; + wb_reg_wb_addr <= mem_reg_wb_addr; + wb_reg_rf_wen <= mem_reg_rf_wen; + wb_reg_wb_data <= + mem_reg_wb_sel == 3'h3 + ? mem_reg_pc + 32'h4 + : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out; + if (reset) + if_reg_pc <= 32'h0; + else if (exe_br_flg) + if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; + else if (exe_jmp_flg) + if_reg_pc <= exe_alu_out; + else if (~stall_flg) + if_reg_pc <= if_reg_pc + 32'h4; + end // always @(posedge) + regfile_32x32 regfile_ext ( + .R0_addr (id_reg_inst[20:16]), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_regfile_ext_R0_data), + .R1_addr (id_reg_inst[25:21]), + .R1_en (1'h1), + .R1_clk (clock), + .R1_data (_regfile_ext_R1_data), + .W0_addr (wb_reg_wb_addr), + .W0_en (_id_rs2_data_T_5), + .W0_clk (clock), + .W0_data (wb_reg_wb_data) + ); + assign io_imem_addr = if_reg_pc; + assign io_dmem_addr = mem_reg_alu_out; + assign io_dmem_wen = mem_reg_mem_wen[0]; + assign io_dmem_wdata = mem_reg_rs2_data; + assign io_exit = id_reg_inst == 32'h00000000; + assign s0_value = _regfile_ext_R0_data; +endmodule diff --git a/Memory.sv b/Memory.sv new file mode 100755 index 0000000..1ee13a7 --- /dev/null +++ b/Memory.sv @@ -0,0 +1,88 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/28 11:28:52 +// Design Name: +// Module Name: Regfile +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mem_512x32( + input [8:0] R0_addr, + input R0_en, + R0_clk, + output [31:0] R0_data, + input [8:0] R1_addr, + input R1_en, + R1_clk, + output [31:0] R1_data, + input [8:0] W0_addr, + input W0_en, + W0_clk, + input [31:0] W0_data + ); + + reg [31:0] Memory[0:511]; + reg _R0_en_d0; + reg [8:0] _R0_addr_d0; + always @(posedge R0_clk) begin + _R0_en_d0 <= R0_en; + _R0_addr_d0 <= R0_addr; + end // always @(posedge) + reg _R1_en_d0; + reg [8:0] _R1_addr_d0; + always @(posedge R1_clk) begin + _R1_en_d0 <= R1_en; + _R1_addr_d0 <= R1_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) +`ifdef ENABLE_INITIAL_MEM_ + initial + $readmemh("src/hex/mem.hex", Memory); +`endif // ENABLE_INITIAL_MEM_ + + assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx; + assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; +endmodule + +module Memory( + input clock, + input [31:0] io_imem_addr, + output [31:0] io_imem_inst, + input [31:0] io_dmem_addr, + output [31:0] io_dmem_rdata, + input io_dmem_wen, + input [31:0] io_dmem_wdata + ); + + mem_512x32 mem_ext ( + .R0_addr (io_imem_addr[10:2]), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_imem_inst), + .R1_addr (io_dmem_addr[10:2]), + .R1_en (1'h1), + .R1_clk (clock), + .R1_data (io_dmem_rdata), + .W0_addr (io_dmem_addr[10:2]), + .W0_en (io_dmem_wen), + .W0_clk (clock), + .W0_data (io_dmem_wdata) + ); +endmodule diff --git a/Regfile.sv b/Regfile.sv new file mode 100755 index 0000000..27e1e0d --- /dev/null +++ b/Regfile.sv @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/28 11:28:52 +// Design Name: +// Module Name: Regfile +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module regfile_32x32( + input [4:0] R0_addr, + input R0_en, + R0_clk, + output [31:0] R0_data, + input [4:0] R1_addr, + input R1_en, + R1_clk, + output [31:0] R1_data, + input [4:0] W0_addr, + input W0_en, + W0_clk, + input [31:0] W0_data + ); + + reg [31:0] Memory[0:31]; + reg _R0_en_d0; + reg [4:0] _R0_addr_d0; + always @(posedge R0_clk) begin + _R0_en_d0 <= R0_en; + _R0_addr_d0 <= R0_addr; + end // always @(posedge) + reg _R1_en_d0; + reg [4:0] _R1_addr_d0; + always @(posedge R1_clk) begin + _R1_en_d0 <= R1_en; + _R1_addr_d0 <= R1_addr; + end // always @(posedge) + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx; + assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; + +endmodule diff --git a/Top.sv b/Top.sv index c181408..0dcb976 100755 --- a/Top.sv +++ b/Top.sv @@ -1,407 +1,31 @@ -// Generated by CIRCT firtool-1.62.0 -// VCS coverage exclude_file -module regfile_32x32( - input [4:0] R0_addr, - input R0_en, - R0_clk, - output [31:0] R0_data, - input [4:0] R1_addr, - input R1_en, - R1_clk, - output [31:0] R1_data, - input [4:0] W0_addr, - input W0_en, - W0_clk, - input [31:0] W0_data - ); +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/28 11:25:38 +// Design Name: +// Module Name: Core +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// - reg [31:0] Memory[0:31]; - reg _R0_en_d0; - reg [4:0] _R0_addr_d0; - always @(posedge R0_clk) begin - _R0_en_d0 <= R0_en; - _R0_addr_d0 <= R0_addr; - end // always @(posedge) - reg _R1_en_d0; - reg [4:0] _R1_addr_d0; - always @(posedge R1_clk) begin - _R1_en_d0 <= R1_en; - _R1_addr_d0 <= R1_addr; - end // always @(posedge) - always @(posedge W0_clk) begin - if (W0_en & 1'h1) - Memory[W0_addr] <= W0_data; - end // always @(posedge) - assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx; - assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; - - // DynamicDisplay show_reg() -endmodule - -module Core( - input clock, - reset, - output [31:0] io_imem_addr, - input [31:0] io_imem_inst, - output [31:0] io_dmem_addr, - input [31:0] io_dmem_rdata, - output io_dmem_wen, - output [31:0] io_dmem_wdata, - output io_exit - ); - - wire [31:0] _regfile_ext_R0_data; - wire [31:0] _regfile_ext_R1_data; - reg [31:0] id_reg_pc; - reg [31:0] id_reg_inst; - reg [31:0] exe_reg_pc; - reg [4:0] exe_reg_wb_addr; - reg [31:0] exe_reg_op1_data; - reg [31:0] exe_reg_op2_data; - reg [31:0] exe_reg_rs2_data; - reg [4:0] exe_reg_exe_fun; - reg [1:0] exe_reg_mem_wen; - reg [1:0] exe_reg_rf_wen; - reg [2:0] exe_reg_wb_sel; - reg [31:0] exe_reg_imm_b_sext; - reg [31:0] mem_reg_pc; - reg [4:0] mem_reg_wb_addr; - reg [31:0] mem_reg_alu_out; - reg [31:0] mem_reg_rs2_data; - reg [1:0] mem_reg_rf_wen; - reg [2:0] mem_reg_wb_sel; - reg [1:0] mem_reg_mem_wen; - reg [4:0] wb_reg_wb_addr; - reg [1:0] wb_reg_rf_wen; - reg [31:0] wb_reg_wb_data; - reg [31:0] if_reg_pc; - wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; - wire exe_br_flg = - exe_reg_exe_fun == 5'hC - ? exe_reg_op1_data != exe_reg_op2_data - : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data; - wire exe_jmp_flg = exe_reg_wb_sel == 3'h3; - always @(posedge clock) begin - automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg; - automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; - automatic logic stall_flg; - automatic logic [31:0] id_inst; - automatic logic _id_rs2_data_T_2; - automatic logic _id_rs2_data_T; - automatic logic [31:0] _id_rs2_data_T_8; - automatic logic [16:0] _GEN; - automatic logic _csignals_T_5; - automatic logic [19:0] _GEN_0; - automatic logic _csignals_T_7; - automatic logic _csignals_T_9; - automatic logic _csignals_T_11; - automatic logic _csignals_T_13; - automatic logic _csignals_T_15; - automatic logic _csignals_T_17; - automatic logic _csignals_T_19; - automatic logic [16:0] _GEN_1; - automatic logic _csignals_T_21; - automatic logic _csignals_T_23; - automatic logic _csignals_T_25; - automatic logic _csignals_T_27; - automatic logic _csignals_T_29; - automatic logic _csignals_T_31; - automatic logic _csignals_T_33; - automatic logic _csignals_T_35; - automatic logic _csignals_T_37; - automatic logic _csignals_T_39; - automatic logic _GEN_2; - automatic logic _GEN_3; - automatic logic [1:0] csignals_1; - automatic logic [2:0] _csignals_T_95; - automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]}; - automatic logic [62:0] _exe_alu_out_T_8 = - {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; - automatic logic [31:0] exe_alu_out; - stall_flg = - _id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) - & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T - & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; - id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; - _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; - _id_rs2_data_T = id_reg_inst[20:16] == 5'h0; - _id_rs2_data_T_8 = - id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 - ? mem_reg_alu_out - : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 - ? wb_reg_wb_data - : _regfile_ext_R0_data; - _GEN = {id_inst[31:26], id_inst[10:0]}; - _csignals_T_5 = _GEN == 17'h20; - _GEN_0 = {id_inst[31:28], id_inst[15:0]}; - _csignals_T_7 = _GEN_0 == 20'h80000; - _csignals_T_9 = _GEN == 17'h22; - _csignals_T_11 = _GEN == 17'h24; - _csignals_T_13 = _GEN == 17'h25; - _csignals_T_15 = _GEN == 17'h26; - _csignals_T_17 = _GEN_0 == 20'hC0000; - _csignals_T_19 = _GEN_0 == 20'hD0000; - _GEN_1 = {id_inst[30:20], id_inst[5:0]}; - _csignals_T_21 = _GEN_1 == 17'h0; - _csignals_T_23 = _GEN_1 == 17'h2; - _csignals_T_25 = _GEN_1 == 17'h3; - _csignals_T_27 = _GEN == 17'h2A; - _csignals_T_29 = _GEN_0 == 20'h40000; - _csignals_T_31 = _GEN_0 == 20'h50000; - _csignals_T_33 = id_inst == 32'hC000000; - _csignals_T_35 = _GEN_0 == 20'h8; - _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000; - _csignals_T_39 = id_inst == 32'h0; - _GEN_2 = _csignals_T_29 | _csignals_T_31; - _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2; - csignals_1 = - _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 - ? 2'h0 - : _csignals_T_33 - ? 2'h1 - : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0}; - _csignals_T_95 = - _csignals_T_5 - ? 3'h1 - : _csignals_T_7 - ? 3'h2 - : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 - ? 3'h1 - : _csignals_T_17 | _csignals_T_19 - ? 3'h2 - : _GEN_3 - ? 3'h1 - : _csignals_T_33 - ? 3'h4 - : _csignals_T_35 - ? 3'h0 - : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39}; - exe_alu_out = - exe_reg_exe_fun == 5'hE - ? exe_reg_op1_data - : exe_reg_exe_fun == 5'h9 - ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} - : exe_reg_exe_fun == 5'h8 - ? $signed($signed(exe_reg_op1_data) >>> _GEN_4) - : exe_reg_exe_fun == 5'h7 - ? exe_reg_op1_data >> _GEN_4 - : exe_reg_exe_fun == 5'h6 - ? _exe_alu_out_T_8[31:0] - : exe_reg_exe_fun == 5'h5 - ? exe_reg_op1_data ^ exe_reg_op2_data - : exe_reg_exe_fun == 5'h4 - ? exe_reg_op1_data | exe_reg_op2_data - : exe_reg_exe_fun == 5'h3 - ? exe_reg_op1_data & exe_reg_op2_data - : exe_reg_exe_fun == 5'h2 - ? exe_reg_op1_data - exe_reg_op2_data - : exe_reg_exe_fun == 5'h1 - ? exe_reg_op1_data + exe_reg_op2_data - : 32'h0; - if (~stall_flg) - id_reg_pc <= if_reg_pc; - if (_id_inst_T) - id_reg_inst <= 32'h0; - else if (~stall_flg) - id_reg_inst <= io_imem_inst; - exe_reg_pc <= id_reg_pc; - exe_reg_wb_addr <= id_reg_inst[15:11]; - if (csignals_1 == 2'h0) - exe_reg_op1_data <= - id_reg_inst[25:21] == 5'h0 - ? 32'h0 - : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2 - ? mem_reg_alu_out - : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5 - ? wb_reg_wb_data - : _regfile_ext_R1_data; - else if (csignals_1 == 2'h1) - exe_reg_op1_data <= id_reg_pc; - else - exe_reg_op1_data <= 32'h0; - if (_csignals_T_95 == 3'h5) - exe_reg_op2_data <= {id_inst[15:0], 16'h0}; - else if (_csignals_T_95 == 3'h4) - exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0}; - else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2) - exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]}; - else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T) - exe_reg_op2_data <= 32'h0; - else - exe_reg_op2_data <= _id_rs2_data_T_8; - exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8; - if (_csignals_T_5 | _csignals_T_7) - exe_reg_exe_fun <= 5'h1; - else if (_csignals_T_9) - exe_reg_exe_fun <= 5'h2; - else if (_csignals_T_11) - exe_reg_exe_fun <= 5'h3; - else if (_csignals_T_13) - exe_reg_exe_fun <= 5'h4; - else if (_csignals_T_15) - exe_reg_exe_fun <= 5'h5; - else if (_csignals_T_17) - exe_reg_exe_fun <= 5'h3; - else if (_csignals_T_19) - exe_reg_exe_fun <= 5'h4; - else if (_csignals_T_21) - exe_reg_exe_fun <= 5'h6; - else if (_csignals_T_23) - exe_reg_exe_fun <= 5'h7; - else if (_csignals_T_25) - exe_reg_exe_fun <= 5'h8; - else if (_csignals_T_27) - exe_reg_exe_fun <= 5'h9; - else if (_csignals_T_29) - exe_reg_exe_fun <= 5'hB; - else if (_csignals_T_31) - exe_reg_exe_fun <= 5'hC; - else if (_csignals_T_33) - exe_reg_exe_fun <= 5'h1; - else if (_csignals_T_35) - exe_reg_exe_fun <= 5'hE; - else - exe_reg_exe_fun <= {4'h0, _csignals_T_37}; - exe_reg_mem_wen <= 2'h0; - if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21 - | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin - exe_reg_rf_wen <= 2'h1; - exe_reg_wb_sel <= 3'h1; - end - else if (_GEN_2) begin - exe_reg_rf_wen <= 2'h0; - exe_reg_wb_sel <= 3'h0; - end - else if (_csignals_T_33) begin - exe_reg_rf_wen <= 2'h1; - exe_reg_wb_sel <= 3'h3; - end - else if (_csignals_T_35) begin - exe_reg_rf_wen <= 2'h0; - exe_reg_wb_sel <= 3'h0; - end - else begin - exe_reg_rf_wen <= {1'h0, _csignals_T_37}; - exe_reg_wb_sel <= {2'h0, _csignals_T_37}; - end - exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]}; - mem_reg_pc <= exe_reg_pc; - mem_reg_wb_addr <= exe_reg_wb_addr; - mem_reg_alu_out <= exe_alu_out; - mem_reg_rs2_data <= exe_reg_rs2_data; - mem_reg_rf_wen <= exe_reg_rf_wen; - mem_reg_wb_sel <= exe_reg_wb_sel; - mem_reg_mem_wen <= exe_reg_mem_wen; - wb_reg_wb_addr <= mem_reg_wb_addr; - wb_reg_rf_wen <= mem_reg_rf_wen; - wb_reg_wb_data <= - mem_reg_wb_sel == 3'h3 - ? mem_reg_pc + 32'h4 - : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out; - if (reset) - if_reg_pc <= 32'h0; - else if (exe_br_flg) - if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; - else if (exe_jmp_flg) - if_reg_pc <= exe_alu_out; - else if (~stall_flg) - if_reg_pc <= if_reg_pc + 32'h4; - end // always @(posedge) - regfile_32x32 regfile_ext ( - .R0_addr (id_reg_inst[20:16]), - .R0_en (1'h1), - .R0_clk (clock), - .R0_data (_regfile_ext_R0_data), - .R1_addr (id_reg_inst[25:21]), - .R1_en (1'h1), - .R1_clk (clock), - .R1_data (_regfile_ext_R1_data), - .W0_addr (wb_reg_wb_addr), - .W0_en (_id_rs2_data_T_5), - .W0_clk (clock), - .W0_data (wb_reg_wb_data) - ); - assign io_imem_addr = if_reg_pc; - assign io_dmem_addr = mem_reg_alu_out; - assign io_dmem_wen = mem_reg_mem_wen[0]; - assign io_dmem_wdata = mem_reg_rs2_data; - assign io_exit = id_reg_inst == 32'hC0000000; -endmodule - -// VCS coverage exclude_file -module mem_512x32( - input [8:0] R0_addr, - input R0_en, - R0_clk, - output [31:0] R0_data, - input [8:0] R1_addr, - input R1_en, - R1_clk, - output [31:0] R1_data, - input [8:0] W0_addr, - input W0_en, - W0_clk, - input [31:0] W0_data - ); - - reg [31:0] Memory[0:511]; - reg _R0_en_d0; - reg [8:0] _R0_addr_d0; - always @(posedge R0_clk) begin - _R0_en_d0 <= R0_en; - _R0_addr_d0 <= R0_addr; - end // always @(posedge) - reg _R1_en_d0; - reg [8:0] _R1_addr_d0; - always @(posedge R1_clk) begin - _R1_en_d0 <= R1_en; - _R1_addr_d0 <= R1_addr; - end // always @(posedge) - always @(posedge W0_clk) begin - if (W0_en & 1'h1) - Memory[W0_addr] <= W0_data; - end // always @(posedge) -`ifdef ENABLE_INITIAL_MEM_ - initial - $readmemh("src/hex/mem.hex", Memory); -`endif // ENABLE_INITIAL_MEM_ - - assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx; - assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx; -endmodule - -module Memory( - input clock, - input [31:0] io_imem_addr, - output [31:0] io_imem_inst, - input [31:0] io_dmem_addr, - output [31:0] io_dmem_rdata, - input io_dmem_wen, - input [31:0] io_dmem_wdata - ); - - mem_512x32 mem_ext ( - .R0_addr (io_imem_addr[10:2]), - .R0_en (1'h1), - .R0_clk (clock), - .R0_data (io_imem_inst), - .R1_addr (io_dmem_addr[10:2]), - .R1_en (1'h1), - .R1_clk (clock), - .R1_data (io_dmem_rdata), - .W0_addr (io_dmem_addr[10:2]), - .W0_en (io_dmem_wen), - .W0_clk (clock), - .W0_data (io_dmem_wdata) - ); -endmodule module Top( input clock, reset, - output io_exit + output io_exit, + output [3:0] io_anodes, // 新增：七段显示器的阳极控制信号 + output [6:0] io_segments // 新增：七段显示器的段控制信号 ); wire [31:0] _memory_io_imem_inst; @@ -410,6 +34,7 @@ module Top( wire [31:0] _core_io_dmem_addr; wire _core_io_dmem_wen; wire [31:0] _core_io_dmem_wdata; + wire [31:0] _core_s0_value; Core core ( .clock (clock), .reset (reset), @@ -419,7 +44,8 @@ module Top( .io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_wen (_core_io_dmem_wen), .io_dmem_wdata (_core_io_dmem_wdata), - .io_exit (io_exit) + .io_exit (io_exit), + .s0_value (_core_s0_value) ); Memory memory ( .clock (clock), @@ -430,5 +56,13 @@ module Top( .io_dmem_wen (_core_io_dmem_wen), .io_dmem_wdata (_core_io_dmem_wdata) ); + // 实例化 DynamicDisplay 模块 + DynamicDisplay display ( + .clock (clock), + .reset (reset), + .reg_result (_core_s0_value), // 连接 $s0 的值 + .io_anodes (io_anodes), // 连接七段显示器的阳极控制信号 + .io_segments(io_segments) // 连接七段显示器的段控制信号 + ); endmodule diff --git a/build.sbt b/build.sbt index 9d4e98d..ea06367 100755 --- a/build.sbt +++ b/build.sbt @@ -1,8 +1,8 @@ // See README.md for license details. -ThisBuild / scalaVersion := "2.13.12" -ThisBuild / version := "0.1.0" -ThisBuild / organization := "%ORGANIZATION%" +ThisBuild / scalaVersion := "2.13.12" +ThisBuild / version := "0.1.0" +ThisBuild / organization := "%ORGANIZATION%" val chiselVersion = "6.2.0" @@ -11,14 +11,17 @@ lazy val root = (project in file(".")) name := "%NAME%", libraryDependencies ++= Seq( "org.chipsalliance" %% "chisel" % chiselVersion, - "org.scalatest" %% "scalatest" % "3.2.16" % "test", + "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test", + "org.scalatest" %% "scalatest" % "3.2.16" % "test" ), scalacOptions ++= Seq( "-language:reflectiveCalls", "-deprecation", "-feature", "-Xcheckinit", - "-Ymacro-annotations", + "-Ymacro-annotations" ), - addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), + addCompilerPlugin( + "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full + ) ) diff --git a/micore.xdc b/micore.xdc index b988cf0..0e2357e 100755 --- a/micore.xdc +++ b/micore.xdc @@ -1,12 +1,10 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] -set_property PACKAGE_PIN W5 [get_ports clk] -set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property PACKAGE_PIN W5 [get_ports clock] +set_property IOSTANDARD LVCMOS33 [get_ports clock] set_property PACKAGE_PIN V17 [get_ports reset] set_property IOSTANDARD LVCMOS33 [get_ports reset] -set_property PACKAGE_PIN E19 [get_ports success_led] -set_property IOSTANDARD LVCMOS33 [get_ports success_led] -set_property PACKAGE_PIN U19 [get_ports fail_led] -set_property IOSTANDARD LVCMOS33 [get_ports fail_led] +set_property PACKAGE_PIN E19 [get_ports io_exit] +set_property IOSTANDARD LVCMOS33 [get_ports io_exit] set_property PACKAGE_PIN U2 [get_ports {io_anodes[0]}] set_property PACKAGE_PIN U4 [get_ports {io_anodes[1]}] set_property PACKAGE_PIN V4 [get_ports {io_anodes[2]}] diff --git a/project/target/config-classes/$0dd3447347b5224615e5.cache b/project/target/config-classes/$1b2e4c70cf01ae9e66b4.cache similarity index 100% rename from project/target/config-classes/$0dd3447347b5224615e5.cache rename to project/target/config-classes/$1b2e4c70cf01ae9e66b4.cache diff --git a/project/target/config-classes/$6becda8e2cd53152091b.cache b/project/target/config-classes/$2f10d7978379a0259464.cache similarity index 100% rename from project/target/config-classes/$6becda8e2cd53152091b.cache rename to project/target/config-classes/$2f10d7978379a0259464.cache diff --git a/project/target/config-classes/$afff5d25069ab86e2b89.cache b/project/target/config-classes/$ae36708fca0f6afe50e3.cache similarity index 100% rename from project/target/config-classes/$afff5d25069ab86e2b89.cache rename to project/target/config-classes/$ae36708fca0f6afe50e3.cache diff --git a/project/target/config-classes/$cc949d4e621f82777efc.cache b/project/target/config-classes/$c326be24cfa0b447c75b.cache similarity index 100% rename from project/target/config-classes/$cc949d4e621f82777efc.cache rename to project/target/config-classes/$c326be24cfa0b447c75b.cache diff --git a/src/hex/mem.hex b/src/hex/mem.hex index 1604db9..1898c61 100755 --- a/src/hex/mem.hex +++ b/src/hex/mem.hex @@ -1,32 +1,8 @@ -20 -08 -00 -01 -20 -10 -00 -00 -20 -12 -00 -65 -02 -08 -80 -20 -21 -08 -00 -01 -01 -12 -50 -2A -15 -40 -FF -FC -00 -00 -00 -00 +00 01 08 20 +00 00 10 20 +65 00 12 20 +20 80 08 02 +01 00 08 21 +2A 50 12 01 +FC FF 40 15 +00 00 00 00 diff --git a/src/test/scala/micore/MicoreSpec.scala b/src/test/scala/micore/MicoreSpec.scala index e575df0..dc05731 100755 --- a/src/test/scala/micore/MicoreSpec.scala +++ b/src/test/scala/micore/MicoreSpec.scala @@ -1,7 +1,13 @@ package micore import chisel3._ -import chisel3.experimental.BundleLiterals._ -import chisel3.simulator.EphemeralSimulator._ -import org.scalatest.freespec.AnyFreeSpec -import org.scalatest.matchers.must.Matchers +import org.scalatest.flatspec._ +import chiseltest._ + +class CTest extends AnyFlatSpec with ChiselScalatestTester { + "Micore" should "run the C program" in { + test(new TopOrigin) { c => + while (!c.io.exit.peek().litToBoolean) { c.clock.step(1) } + } + } +} diff --git a/target/scala-2.13/update/update_cache_2.13/inputs b/target/scala-2.13/update/update_cache_2.13/inputs index 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\ No newline at end of file diff --git a/target/streams/compile/bloopGenerate/_global/streams/out b/target/streams/compile/bloopGenerate/_global/streams/out index 7734581..a01d15f 100755 --- a/target/streams/compile/bloopGenerate/_global/streams/out +++ b/target/streams/compile/bloopGenerate/_global/streams/out @@ -1,4 +1,4 @@ [debug] [root] Classpath dependencies List() [debug] [root] Dependencies from configurations List() -[debug] Bloop wrote the configuration of project 'root' to '/home/gh0s7/nfs/project/micore/.bloop/root.json' +[debug] Bloop wrote the configuration of project 'root' to '/run/media/gh0s7/Data/project/ddca2024/micore/.bloop/root.json' [success] Generated .bloop/root.json diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index 297ce60..69ae457 100755 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -1,62 +1,6 @@ [debug] [zinc] IncrementalCompile ----------- [debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 19 products, 5 sources, 2 libraries +[debug] previous = Stamps for: 18 products, 5 sources, 2 libraries [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala) -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Top.scala), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug]  -[debug] Initial source changes: -[debug]  removed: Set() -[debug]  added: Set() -[debug]  modified: Set(${BASE}/src/main/scala/micore/Top.scala) -[debug] Invalidated products: Set() -[debug] External API changes: API Changes: Set() -[debug] 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-deprecation -[debug]  -feature -[debug]  -Xcheckinit -[debug]  -Ymacro-annotations -[debug]  -Xplugin:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel-plugin_2.13.12/6.2.0/chisel-plugin_2.13.12-6.2.0.jar -[debug]  -bootclasspath -[debug]  /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar -[debug]  -classpath -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar -[debug] Invalidating (transitively) by inheritance from micore.TopOrigin... -[debug] Initial set of included nodes: micore.TopOrigin -[debug] Invalidated by transitive inheritance dependency: Set(micore.TopOrigin) -[debug] Change NamesChange(micore.TopOrigin,ModifiedNames(changes = UsedName(getCommands,[Default]), UsedName(notify,[Default]), UsedName(hasAutoSeed,[Default]), UsedName(atModuleBodyEnd,[Default]), UsedName(micore;TopOrigin;init;,[Default]), UsedName(io,[Default]), UsedName(seedOpt,[Default]), UsedName(getModulePortsAndLocators,[Default]), UsedName(_computeName,[Default]), UsedName(suggestName,[Default]), UsedName(forceName,[Default]), UsedName(_closed,[Default]), UsedName(_circuit,[Default]), UsedName(forceName$default$4,[Default]), UsedName(findPort,[Default]), UsedName(_namespace,[Default]), UsedName(_whereIOCreationIsDisallowed,[Default]), UsedName(equals,[Default]), UsedName(override_clock_=,[Default]), UsedName(_parent_=,[Default]), UsedName(pathName,[Default]), UsedName(checkPorts,[Default]), UsedName(hashCode,[Default]), UsedName(IO,[Default]), UsedName(isInstanceOf,[Default]), UsedName(_lastId,[Default]), UsedName(override_clock,[Default]), UsedName(desiredName,[Default]), UsedName(autoSeed,[Default]), UsedName(override_reset_=,[Default]), UsedName(_id,[Default]), UsedName(setRef$default$3,[Default]), UsedName(notifyAll,[Default]), UsedName(getIds,[Default]), UsedName(reset,[Default]), UsedName(portsContains,[Default]), UsedName(clock,[Default]), UsedName(_definitionIdentifier,[Default]), UsedName(endIOCreation,[Default]), UsedName(getModulePorts,[Default]), UsedName(forceAutoSeed,[Default]), UsedName(_errorContext,[Default]), UsedName(circuitName,[Default]), UsedName(override_reset,[Default]), UsedName(reifyTarget,[Default]), UsedName(name,[Default]), UsedName(_circuit_=,[Default]), UsedName(hasSeed,[Default]), UsedName(isFullyClosed,[Default]), UsedName(fullyClosedErrorMessages,[Default]), UsedName(_component,[Default]), UsedName(implicitReset,[Default]), UsedName(getChiselPorts,[Default]), UsedName(eq,[Default]), UsedName(memory,[Default]), UsedName(stagedSecretCommands,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(createSecretIO,[Default]), UsedName(setRef,[Default]), UsedName(_getSourceLocator,[Default]), UsedName(toString,[Default]), UsedName(isIOCreationAllowed,[Default]), UsedName(parentPathName,[Default]), UsedName(ne,[Default]), UsedName(##,[Default]), UsedName(portsSize,[Default]), UsedName(mkReset,[Default]), UsedName(toTarget,[Default]), UsedName($init$,[Default]), UsedName(secretConnection,[Default]), UsedName(secretPorts,[Default]), UsedName(resetType,[Default]), UsedName(disallowIO,[Default]), UsedName(getTarget,[Default]), UsedName(_traitModuleDefinitionIdentifierProposal,[Default]), UsedName(addSecretIO,[Default]), UsedName(==,[Default]), UsedName(definitionIdentifier,[Default]), UsedName(clone,[Default]), UsedName(addId,[Default]), UsedName(wait,[Default]), UsedName(getRef,[Default]), UsedName(implicitClock,[Default]), UsedName(_sourceInfo,[Default]), UsedName(getOptionRef,[Default]), UsedName(synchronized,[Default]), UsedName(_parent,[Default]), UsedName(modulePortsAskedFor,[Default]), UsedName(toRelativeTarget,[Default]), UsedName(_moduleDefinitionIdentifierProposal,[Default]), UsedName(parentModName,[Default]), UsedName(forceName$default$3,[Default]), UsedName(TopOrigin,[Default]), UsedName(asInstanceOf,[Default]), UsedName(finalize,[Default]), UsedName(reifyParent,[Default]), UsedName(isClosed,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(core,[Default]), UsedName(_ids,[Default]), UsedName(exit,[Default]), UsedName(addCommand,[Default]), UsedName(generateComponent,[Default]), UsedName(!=,[Default]), UsedName(initializeInParent,[Default]), UsedName(toNamed,[Default]), UsedName(namePorts,[Default]), UsedName(toDefinitionCalled,[Default]), UsedName(_suggestNameCheck,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(getClass,[Default]), UsedName(instanceName,[Default]))) invalidates 1 classes due to The micore.TopOrigin has the following regular definitions changed: -[debug]  UsedName(getCommands,[Default]), UsedName(notify,[Default]), UsedName(hasAutoSeed,[Default]), UsedName(atModuleBodyEnd,[Default]), UsedName(micore;TopOrigin;init;,[Default]), UsedName(io,[Default]), UsedName(seedOpt,[Default]), UsedName(getModulePortsAndLocators,[Default]), UsedName(_computeName,[Default]), UsedName(suggestName,[Default]), UsedName(forceName,[Default]), UsedName(_closed,[Default]), UsedName(_circuit,[Default]), UsedName(forceName$default$4,[Default]), UsedName(findPort,[Default]), UsedName(_namespace,[Default]), UsedName(_whereIOCreationIsDisallowed,[Default]), UsedName(equals,[Default]), UsedName(override_clock_=,[Default]), UsedName(_parent_=,[Default]), UsedName(pathName,[Default]), UsedName(checkPorts,[Default]), UsedName(hashCode,[Default]), UsedName(IO,[Default]), UsedName(isInstanceOf,[Default]), UsedName(_lastId,[Default]), UsedName(override_clock,[Default]), UsedName(desiredName,[Default]), UsedName(autoSeed,[Default]), UsedName(override_reset_=,[Default]), UsedName(_id,[Default]), UsedName(setRef$default$3,[Default]), UsedName(notifyAll,[Default]), UsedName(getIds,[Default]), UsedName(reset,[Default]), UsedName(portsContains,[Default]), UsedName(clock,[Default]), UsedName(_definitionIdentifier,[Default]), UsedName(endIOCreation,[Default]), UsedName(getModulePorts,[Default]), UsedName(forceAutoSeed,[Default]), UsedName(_errorContext,[Default]), UsedName(circuitName,[Default]), UsedName(override_reset,[Default]), UsedName(reifyTarget,[Default]), UsedName(name,[Default]), UsedName(_circuit_=,[Default]), UsedName(hasSeed,[Default]), UsedName(isFullyClosed,[Default]), UsedName(fullyClosedErrorMessages,[Default]), UsedName(_component,[Default]), UsedName(implicitReset,[Default]), UsedName(getChiselPorts,[Default]), UsedName(eq,[Default]), UsedName(memory,[Default]), UsedName(stagedSecretCommands,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(createSecretIO,[Default]), UsedName(setRef,[Default]), UsedName(_getSourceLocator,[Default]), UsedName(toString,[Default]), UsedName(isIOCreationAllowed,[Default]), UsedName(parentPathName,[Default]), UsedName(ne,[Default]), UsedName(##,[Default]), UsedName(portsSize,[Default]), UsedName(mkReset,[Default]), UsedName(toTarget,[Default]), UsedName($init$,[Default]), UsedName(secretConnection,[Default]), UsedName(secretPorts,[Default]), UsedName(resetType,[Default]), UsedName(disallowIO,[Default]), UsedName(getTarget,[Default]), UsedName(_traitModuleDefinitionIdentifierProposal,[Default]), UsedName(addSecretIO,[Default]), UsedName(==,[Default]), UsedName(definitionIdentifier,[Default]), UsedName(clone,[Default]), UsedName(addId,[Default]), UsedName(wait,[Default]), UsedName(getRef,[Default]), UsedName(implicitClock,[Default]), UsedName(_sourceInfo,[Default]), UsedName(getOptionRef,[Default]), UsedName(synchronized,[Default]), UsedName(_parent,[Default]), UsedName(modulePortsAskedFor,[Default]), UsedName(toRelativeTarget,[Default]), UsedName(_moduleDefinitionIdentifierProposal,[Default]), UsedName(parentModName,[Default]), UsedName(forceName$default$3,[Default]), UsedName(TopOrigin,[Default]), UsedName(asInstanceOf,[Default]), UsedName(finalize,[Default]), UsedName(reifyParent,[Default]), UsedName(isClosed,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(core,[Default]), UsedName(_ids,[Default]), UsedName(exit,[Default]), UsedName(addCommand,[Default]), UsedName(generateComponent,[Default]), UsedName(!=,[Default]), UsedName(initializeInParent,[Default]), UsedName(toNamed,[Default]), UsedName(namePorts,[Default]), UsedName(toDefinitionCalled,[Default]), UsedName(_suggestNameCheck,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(getClass,[Default]), UsedName(instanceName,[Default]). -[debug]  > by transitive inheritance: Set(micore.TopOrigin) -[debug]  >  -[debug]  >  -[debug]   -[debug] Invalidating (transitively) by inheritance from micore.Top... -[debug] Initial set of included nodes: micore.Top -[debug] Invalidated by transitive inheritance dependency: Set(micore.Top) -[debug] Change NamesChange(micore.Top,ModifiedNames(changes = UsedName(getCommands,[Default]), UsedName(notify,[Default]), UsedName(hasAutoSeed,[Default]), UsedName(atModuleBodyEnd,[Default]), UsedName(io,[Default]), UsedName(seedOpt,[Default]), UsedName(getModulePortsAndLocators,[Default]), UsedName(_computeName,[Default]), UsedName(suggestName,[Default]), UsedName(forceName,[Default]), UsedName(_closed,[Default]), UsedName(_circuit,[Default]), UsedName(forceName$default$4,[Default]), UsedName(findPort,[Default]), UsedName(_namespace,[Default]), UsedName(_whereIOCreationIsDisallowed,[Default]), UsedName(equals,[Default]), UsedName(override_clock_=,[Default]), UsedName(_parent_=,[Default]), UsedName(pathName,[Default]), UsedName(checkPorts,[Default]), UsedName(hashCode,[Default]), UsedName(IO,[Default]), UsedName(isInstanceOf,[Default]), UsedName(_lastId,[Default]), UsedName(override_clock,[Default]), UsedName(desiredName,[Default]), UsedName(autoSeed,[Default]), UsedName(override_reset_=,[Default]), UsedName(_id,[Default]), UsedName(setRef$default$3,[Default]), UsedName(notifyAll,[Default]), UsedName(getIds,[Default]), UsedName(reset,[Default]), UsedName(Top,[Default]), UsedName(portsContains,[Default]), UsedName(clock,[Default]), UsedName(_definitionIdentifier,[Default]), UsedName(endIOCreation,[Default]), UsedName(getModulePorts,[Default]), UsedName(forceAutoSeed,[Default]), UsedName(_errorContext,[Default]), UsedName(circuitName,[Default]), UsedName(override_reset,[Default]), UsedName(reifyTarget,[Default]), UsedName(name,[Default]), UsedName(_circuit_=,[Default]), UsedName(hasSeed,[Default]), UsedName(isFullyClosed,[Default]), UsedName(fullyClosedErrorMessages,[Default]), UsedName(_component,[Default]), UsedName(implicitReset,[Default]), UsedName(getChiselPorts,[Default]), UsedName(eq,[Default]), UsedName(memory,[Default]), UsedName(stagedSecretCommands,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(createSecretIO,[Default]), UsedName(setRef,[Default]), UsedName(_getSourceLocator,[Default]), UsedName(toString,[Default]), UsedName(isIOCreationAllowed,[Default]), UsedName(parentPathName,[Default]), UsedName(ne,[Default]), UsedName(##,[Default]), UsedName(portsSize,[Default]), UsedName(mkReset,[Default]), UsedName(micore;Top;init;,[Default]), UsedName(toTarget,[Default]), UsedName($init$,[Default]), UsedName(secretConnection,[Default]), UsedName(secretPorts,[Default]), UsedName(resetType,[Default]), UsedName(disallowIO,[Default]), UsedName(getTarget,[Default]), UsedName(_traitModuleDefinitionIdentifierProposal,[Default]), UsedName(addSecretIO,[Default]), UsedName(==,[Default]), UsedName(definitionIdentifier,[Default]), UsedName(clone,[Default]), UsedName(addId,[Default]), UsedName(wait,[Default]), UsedName(getRef,[Default]), UsedName(implicitClock,[Default]), UsedName(_sourceInfo,[Default]), UsedName(getOptionRef,[Default]), UsedName(synchronized,[Default]), UsedName(_parent,[Default]), UsedName(modulePortsAskedFor,[Default]), UsedName(toRelativeTarget,[Default]), UsedName(_moduleDefinitionIdentifierProposal,[Default]), UsedName(parentModName,[Default]), UsedName(forceName$default$3,[Default]), UsedName(asInstanceOf,[Default]), UsedName(finalize,[Default]), UsedName(reifyParent,[Default]), UsedName(isClosed,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(core,[Default]), UsedName(_ids,[Default]), UsedName(exit,[Default]), UsedName(addCommand,[Default]), UsedName(generateComponent,[Default]), UsedName(!=,[Default]), UsedName(initializeInParent,[Default]), UsedName(toNamed,[Default]), UsedName(namePorts,[Default]), UsedName(toDefinitionCalled,[Default]), UsedName(_suggestNameCheck,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(getClass,[Default]), UsedName(instanceName,[Default]))) invalidates 1 classes due to The micore.Top has the following regular definitions changed: -[debug]  UsedName(getCommands,[Default]), UsedName(notify,[Default]), UsedName(hasAutoSeed,[Default]), UsedName(atModuleBodyEnd,[Default]), UsedName(io,[Default]), UsedName(seedOpt,[Default]), UsedName(getModulePortsAndLocators,[Default]), UsedName(_computeName,[Default]), UsedName(suggestName,[Default]), UsedName(forceName,[Default]), UsedName(_closed,[Default]), UsedName(_circuit,[Default]), UsedName(forceName$default$4,[Default]), UsedName(findPort,[Default]), UsedName(_namespace,[Default]), UsedName(_whereIOCreationIsDisallowed,[Default]), UsedName(equals,[Default]), UsedName(override_clock_=,[Default]), UsedName(_parent_=,[Default]), UsedName(pathName,[Default]), UsedName(checkPorts,[Default]), UsedName(hashCode,[Default]), UsedName(IO,[Default]), UsedName(isInstanceOf,[Default]), UsedName(_lastId,[Default]), UsedName(override_clock,[Default]), UsedName(desiredName,[Default]), UsedName(autoSeed,[Default]), UsedName(override_reset_=,[Default]), UsedName(_id,[Default]), UsedName(setRef$default$3,[Default]), UsedName(notifyAll,[Default]), UsedName(getIds,[Default]), UsedName(reset,[Default]), UsedName(Top,[Default]), UsedName(portsContains,[Default]), UsedName(clock,[Default]), UsedName(_definitionIdentifier,[Default]), UsedName(endIOCreation,[Default]), UsedName(getModulePorts,[Default]), UsedName(forceAutoSeed,[Default]), UsedName(_errorContext,[Default]), UsedName(circuitName,[Default]), UsedName(override_reset,[Default]), UsedName(reifyTarget,[Default]), UsedName(name,[Default]), UsedName(_circuit_=,[Default]), UsedName(hasSeed,[Default]), UsedName(isFullyClosed,[Default]), UsedName(fullyClosedErrorMessages,[Default]), UsedName(_component,[Default]), UsedName(implicitReset,[Default]), UsedName(getChiselPorts,[Default]), UsedName(eq,[Default]), UsedName(memory,[Default]), UsedName(stagedSecretCommands,[Default]), UsedName(_bindIoInPlace,[Default]), UsedName(createSecretIO,[Default]), UsedName(setRef,[Default]), UsedName(_getSourceLocator,[Default]), UsedName(toString,[Default]), UsedName(isIOCreationAllowed,[Default]), UsedName(parentPathName,[Default]), UsedName(ne,[Default]), UsedName(##,[Default]), UsedName(portsSize,[Default]), UsedName(mkReset,[Default]), UsedName(micore;Top;init;,[Default]), UsedName(toTarget,[Default]), UsedName($init$,[Default]), UsedName(secretConnection,[Default]), UsedName(secretPorts,[Default]), UsedName(resetType,[Default]), UsedName(disallowIO,[Default]), UsedName(getTarget,[Default]), UsedName(_traitModuleDefinitionIdentifierProposal,[Default]), UsedName(addSecretIO,[Default]), UsedName(==,[Default]), UsedName(definitionIdentifier,[Default]), UsedName(clone,[Default]), UsedName(addId,[Default]), UsedName(wait,[Default]), UsedName(getRef,[Default]), UsedName(implicitClock,[Default]), UsedName(_sourceInfo,[Default]), UsedName(getOptionRef,[Default]), UsedName(synchronized,[Default]), UsedName(_parent,[Default]), UsedName(modulePortsAskedFor,[Default]), UsedName(toRelativeTarget,[Default]), UsedName(_moduleDefinitionIdentifierProposal,[Default]), UsedName(parentModName,[Default]), UsedName(forceName$default$3,[Default]), UsedName(asInstanceOf,[Default]), UsedName(finalize,[Default]), UsedName(reifyParent,[Default]), UsedName(isClosed,[Default]), UsedName(bindIoInPlace,[Default]), UsedName(core,[Default]), UsedName(_ids,[Default]), UsedName(exit,[Default]), UsedName(addCommand,[Default]), UsedName(generateComponent,[Default]), UsedName(!=,[Default]), UsedName(initializeInParent,[Default]), UsedName(toNamed,[Default]), UsedName(namePorts,[Default]), UsedName(toDefinitionCalled,[Default]), UsedName(_suggestNameCheck,[Default]), UsedName(toAbsoluteTarget,[Default]), UsedName(getClass,[Default]), UsedName(instanceName,[Default]). -[debug]  > by transitive inheritance: Set(micore.Top) -[debug]  >  -[debug]  >  -[debug]   -[debug] New invalidations: -[debug] Initial set of included nodes:  -[debug] Previously invalidated, but (transitively) depend on new invalidations: -[debug] Final step, transitive dependencies: -[debug]  Set() -[debug] No classes were invalidated. -[debug] Scala compilation took 1.610209372 s -[debug] done compiling +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] No changes diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out index 4ea3977..9479f4e 100755 --- a/target/streams/compile/incOptions/_global/streams/out +++ b/target/streams/compile/incOptions/_global/streams/out @@ -1,19 +1,2 @@ [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak -[debug] About to delete class files: -[debug]  TopOrigin$delayedInit$body.class -[debug]  TopOrigin.class -[debug]  Top$$anon$1.class -[debug]  TopOrigin$.class -[debug]  Top.class -[debug] We backup class files: -[debug]  TopOrigin$delayedInit$body.class -[debug]  TopOrigin.class -[debug]  Top$$anon$1.class -[debug]  TopOrigin$.class -[debug]  Top.class -[debug] Registering generated classes: -[debug]  TopOrigin$.class -[debug]  TopOrigin$delayedInit$body.class -[debug]  TopOrigin.class -[debug]  TopOrigin$$anon$1.class [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak diff --git a/target/streams/test/bloopGenerate/_global/streams/out b/target/streams/test/bloopGenerate/_global/streams/out index c960147..e015935 100755 --- a/target/streams/test/bloopGenerate/_global/streams/out +++ b/target/streams/test/bloopGenerate/_global/streams/out @@ -1,4 +1,4 @@ [debug] [root-test] Classpath dependencies List() [debug] [root-test] Dependencies from configurations List(root) -[debug] Bloop wrote the configuration of project 'root-test' to '/home/gh0s7/nfs/project/micore/.bloop/root-test.json' +[debug] Bloop wrote the configuration of project 'root-test' to '/run/media/gh0s7/Data/project/ddca2024/micore/.bloop/root-test.json' [success] Generated .bloop/root-test.json diff --git a/target/streams/test/externalDependencyClasspath/_global/streams/export b/target/streams/test/externalDependencyClasspath/_global/streams/export index 8821bd0..d156c89 100755 --- a/target/streams/test/externalDependencyClasspath/_global/streams/export +++ b/target/streams/test/externalDependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/target/streams/test/managedClasspath/_global/streams/export b/target/streams/test/managedClasspath/_global/streams/export index 8821bd0..d156c89 100755 --- a/target/streams/test/managedClasspath/_global/streams/export +++ b/target/streams/test/managedClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir new file mode 100755 index 0000000..1f38fae --- /dev/null +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -0,0 +1,480 @@ +FIRRTL version 1.2.0 +circuit TopOrigin : + module Core : @[src/main/scala/micore/Core.scala 8:7] + input clock : Clock @[src/main/scala/micore/Core.scala 8:7] + input reset : UInt<1> @[src/main/scala/micore/Core.scala 8:7] + output io_imem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14] + input io_imem_inst : UInt<32> @[src/main/scala/micore/Core.scala 9:14] + output io_dmem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14] + input io_dmem_rdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14] + output io_dmem_wen : UInt<1> @[src/main/scala/micore/Core.scala 9:14] + output io_dmem_wdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14] + output io_exit : UInt<1> @[src/main/scala/micore/Core.scala 9:14] + + mem regfile : @[src/main/scala/micore/Core.scala 16:28] + data-type => UInt<32> + depth => 32 + read-latency => 1 + write-latency => 1 + reader => id_rs1_data_MPORT + reader => id_rs2_data_MPORT + writer => MPORT + read-under-write => undefined + reg id_reg_pc : UInt<32>, clock with : + reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 19:19] + reg id_reg_inst : UInt<32>, clock with : + reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 19:19] + reg exe_reg_pc : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_wb_addr : UInt<5>, clock with : + reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_op1_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_op2_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_rs2_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_exe_fun : UInt<5>, clock with : + reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_mem_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_rf_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_wb_sel : UInt<3>, clock with : + reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 24:20] + reg exe_reg_imm_b_sext : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 24:20] + reg mem_reg_pc : UInt<32>, clock with : + reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_wb_addr : UInt<5>, clock with : + reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_alu_out : UInt<32>, clock with : + reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_rs2_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_rf_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_wb_sel : UInt<3>, clock with : + reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 37:20] + reg mem_reg_mem_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 37:20] + reg wb_reg_wb_addr : UInt<5>, clock with : + reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 47:19] + reg wb_reg_rf_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:19] + reg wb_reg_wb_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:19] + reg if_reg_pc : UInt<32>, clock with : + reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 54:26] + node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 64:31] + node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 64:31] + node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] + node id_rs1_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 86:32] + node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:48] + node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] + node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:73] + node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:57] + node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21] + node id_rs2_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 87:32] + node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:48] + node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32] + node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:73] + node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:57] + node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36] + node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 58:23 95:13] + node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34] + node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 61:25] + node _exe_alu_out_T_37 = eq(UInt<5>("he"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_35 = eq(UInt<5>("h9"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_16 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 206:36] + node _exe_alu_out_T_17 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:62] + node _exe_alu_out_T_18 = lt(_exe_alu_out_T_16, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 206:43] + node _exe_alu_out_T_33 = eq(UInt<5>("h8"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_12 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 205:36] + node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 205:62] + node _exe_alu_out_T_14 = dshr(_exe_alu_out_T_12, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 205:43] + node _exe_alu_out_T_15 = asUInt(_exe_alu_out_T_14) @[src/main/scala/micore/Core.scala 205:70] + node _exe_alu_out_T_31 = eq(UInt<5>("h7"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_10 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:55] + node _exe_alu_out_T_11 = dshr(exe_reg_op1_data, _exe_alu_out_T_10) @[src/main/scala/micore/Core.scala 204:36] + node _exe_alu_out_T_29 = eq(UInt<5>("h6"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_7 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:55] + node _exe_alu_out_T_8 = dshl(exe_reg_op1_data, _exe_alu_out_T_7) @[src/main/scala/micore/Core.scala 203:36] + node _exe_alu_out_T_9 = bits(_exe_alu_out_T_8, 31, 0) @[src/main/scala/micore/Core.scala 203:62] + node _exe_alu_out_T_27 = eq(UInt<5>("h5"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_6 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:36] + node _exe_alu_out_T_25 = eq(UInt<5>("h4"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_5 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:35] + node _exe_alu_out_T_23 = eq(UInt<5>("h3"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_4 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:36] + node _exe_alu_out_T_21 = eq(UInt<5>("h2"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_2 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:36] + node _exe_alu_out_T_3 = tail(_exe_alu_out_T_2, 1) @[src/main/scala/micore/Core.scala 199:36] + node _exe_alu_out_T_19 = eq(UInt<5>("h1"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:36] + node _exe_alu_out_T_1 = tail(_exe_alu_out_T, 1) @[src/main/scala/micore/Core.scala 198:36] + node _exe_alu_out_T_20 = mux(_exe_alu_out_T_19, _exe_alu_out_T_1, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_22 = mux(_exe_alu_out_T_21, _exe_alu_out_T_3, _exe_alu_out_T_20) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_24 = mux(_exe_alu_out_T_23, _exe_alu_out_T_4, _exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_26 = mux(_exe_alu_out_T_25, _exe_alu_out_T_5, _exe_alu_out_T_24) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_28 = mux(_exe_alu_out_T_27, _exe_alu_out_T_6, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_30 = mux(_exe_alu_out_T_29, _exe_alu_out_T_9, _exe_alu_out_T_28) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_32 = mux(_exe_alu_out_T_31, _exe_alu_out_T_11, _exe_alu_out_T_30) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_34 = mux(_exe_alu_out_T_33, _exe_alu_out_T_15, _exe_alu_out_T_32) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, _exe_alu_out_T_18, _exe_alu_out_T_34) @[src/main/scala/micore/Core.scala 196:4] + node _exe_alu_out_T_38 = mux(_exe_alu_out_T_37, exe_reg_op1_data, _exe_alu_out_T_36) @[src/main/scala/micore/Core.scala 196:4] + node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 193:15 62:25] + node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_br_flg_T_4 = eq(UInt<5>("hc"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4] + node _exe_br_flg_T_1 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:35] + node _exe_br_flg_T_2 = eq(UInt<5>("hb"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4] + node _exe_br_flg_T = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:35] + node _exe_br_flg_T_3 = mux(_exe_br_flg_T_2, _exe_br_flg_T, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 214:4] + node _exe_br_flg_T_5 = mux(_exe_br_flg_T_4, _exe_br_flg_T_1, _exe_br_flg_T_3) @[src/main/scala/micore/Core.scala 214:4] + node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 211:14 59:24] + node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 221:31] + node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 221:31] + node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 221:17 60:27] + node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 76:19] + node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 80:19] + node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_wb_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 88:31] + node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21] + node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36] + node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8] + node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:17] + node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20] + node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60] + node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 104:41] + node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:22] + node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:60] + node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 107:42] + node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/micore/Core.scala 106:10] + node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_reg_alu_out, _id_rs1_data_T_7) @[src/main/scala/micore/Core.scala 103:8] + node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/micore/Core.scala 100:24] + node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:17] + node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:20] + node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:60] + node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:41] + node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 120:22] + node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 120:60] + node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 120:42] + node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/micore/Core.scala 119:10] + node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_reg_alu_out, _id_rs2_data_T_7) @[src/main/scala/micore/Core.scala 116:8] + node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/micore/Core.scala 113:24] + node _id_imm_i_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 128:43] + node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 128:31] + node _id_imm_i_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 128:57] + node id_imm_i_sext = cat(_id_imm_i_sext_T_1, _id_imm_i_sext_T_2) @[src/main/scala/micore/Core.scala 128:26] + node _id_imm_b_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 129:43] + node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 129:31] + node _id_imm_b_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 129:57] + node id_imm_b_sext = cat(_id_imm_b_sext_T_1, _id_imm_b_sext_T_2) @[src/main/scala/micore/Core.scala 129:26] + node _csignals_T = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_2 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_4 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_6 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_8 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_10 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_12 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_14 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_16 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_18 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_20 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_21 = eq(UInt<1>("h0"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_22 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_23 = eq(UInt<2>("h2"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_24 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_25 = eq(UInt<2>("h3"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_26 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_27 = eq(UInt<6>("h2a"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_28 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_29 = eq(UInt<31>("h40000000"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_30 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_31 = eq(UInt<31>("h50000000"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_36 = and(id_inst, UInt<33>("h1ffc003ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_37 = eq(UInt<31>("h78000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_38 = and(id_inst, UInt<33>("h1ffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h1"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("he"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("h8"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("h7"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h6"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h2"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h2"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_1 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h3"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h0"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h0"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _id_op1_data_T = eq(csignals_1, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 163:16] + node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 165:20] + node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 165:8] + node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/micore/Core.scala 162:24] + node _id_op2_data_T = bits(id_inst, 25, 25) @[src/main/scala/micore/Core.scala 175:37] + node _id_op2_data_T_1 = mux(_id_op2_data_T, UInt<4>("hf"), UInt<4>("h0")) @[src/main/scala/micore/Core.scala 175:26] + node _id_op2_data_T_2 = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 175:51] + node id_op2_data_hi = cat(_id_op2_data_T_1, _id_op2_data_T_2) @[src/main/scala/micore/Core.scala 175:21] + node _id_op2_data_T_3 = cat(id_op2_data_hi, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 175:21] + node _id_op2_data_T_4 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 176:29] + node _id_op2_data_T_5 = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 176:42] + node _id_op2_data_T_6 = cat(_id_op2_data_T_4, _id_op2_data_T_5) @[src/main/scala/micore/Core.scala 176:21] + node _id_op2_data_T_7 = eq(UInt<3>("h1"), csignals_2) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_8 = mux(_id_op2_data_T_7, id_rs2_data, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_9 = eq(UInt<3>("h2"), csignals_2) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_10 = mux(_id_op2_data_T_9, id_imm_i_sext, _id_op2_data_T_8) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_11 = eq(UInt<3>("h3"), csignals_2) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_12 = mux(_id_op2_data_T_11, id_imm_i_sext, _id_op2_data_T_10) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_13 = eq(UInt<3>("h4"), csignals_2) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_14 = mux(_id_op2_data_T_13, _id_op2_data_T_3, _id_op2_data_T_12) @[src/main/scala/micore/Core.scala 170:4] + node _id_op2_data_T_15 = eq(UInt<3>("h5"), csignals_2) @[src/main/scala/micore/Core.scala 170:4] + node id_op2_data = mux(_id_op2_data_T_15, _id_op2_data_T_6, _id_op2_data_T_14) @[src/main/scala/micore/Core.scala 170:4] + node _mem_wb_data_T = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 244:28] + node _mem_wb_data_T_1 = tail(_mem_wb_data_T, 1) @[src/main/scala/micore/Core.scala 244:28] + node _mem_wb_data_T_2 = eq(UInt<3>("h2"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4] + node _mem_wb_data_T_3 = mux(_mem_wb_data_T_2, io_dmem_rdata, mem_reg_alu_out) @[src/main/scala/micore/Core.scala 241:4] + node _mem_wb_data_T_4 = eq(UInt<3>("h3"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4] + node mem_wb_data = mux(_mem_wb_data_T_4, _mem_wb_data_T_1, _mem_wb_data_T_3) @[src/main/scala/micore/Core.scala 241:4] + node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 254:22] + node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 254:33 255:12] + node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 254:33 255:12] + node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 254:33 255:12 16:28] + node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 254:33 255:29] + node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 254:33 255:29] + node _io_exit_T = eq(id_reg_inst, UInt<32>("hc0000000")) @[src/main/scala/micore/Core.scala 258:27] + io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 55:16] + io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16] + io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15] + io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 236:17] + io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 258:11] + regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 109:16] + regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 86:32] + regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 109:16] + regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:16] + regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 87:32] + regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:16] + regfile.MPORT.addr <= _GEN_0 + regfile.MPORT.en <= _GEN_2 + regfile.MPORT.clk <= _GEN_1 + regfile.MPORT.data <= _GEN_4 + regfile.MPORT.mask <= _GEN_3 + id_reg_pc <= _id_reg_pc_T @[src/main/scala/micore/Core.scala 76:13] + id_reg_inst <= _id_reg_inst_T_2 @[src/main/scala/micore/Core.scala 77:15] + exe_reg_pc <= id_reg_pc @[src/main/scala/micore/Core.scala 181:14] + exe_reg_wb_addr <= id_wb_addr @[src/main/scala/micore/Core.scala 185:19] + exe_reg_op1_data <= id_op1_data @[src/main/scala/micore/Core.scala 182:20] + exe_reg_op2_data <= id_op2_data @[src/main/scala/micore/Core.scala 183:20] + exe_reg_rs2_data <= id_rs2_data @[src/main/scala/micore/Core.scala 184:20] + exe_reg_exe_fun <= csignals_0 @[src/main/scala/micore/Core.scala 190:19] + exe_reg_mem_wen <= csignals_3 @[src/main/scala/micore/Core.scala 187:19] + exe_reg_rf_wen <= csignals_4 @[src/main/scala/micore/Core.scala 188:18] + exe_reg_wb_sel <= csignals_5 @[src/main/scala/micore/Core.scala 186:18] + exe_reg_imm_b_sext <= id_imm_b_sext @[src/main/scala/micore/Core.scala 189:22] + mem_reg_pc <= exe_reg_pc @[src/main/scala/micore/Core.scala 225:14] + mem_reg_wb_addr <= exe_reg_wb_addr @[src/main/scala/micore/Core.scala 226:19] + mem_reg_alu_out <= exe_alu_out @[src/main/scala/micore/Core.scala 227:19] + mem_reg_rs2_data <= exe_reg_rs2_data @[src/main/scala/micore/Core.scala 228:20] + mem_reg_rf_wen <= exe_reg_rf_wen @[src/main/scala/micore/Core.scala 229:18] + mem_reg_wb_sel <= exe_reg_wb_sel @[src/main/scala/micore/Core.scala 230:18] + mem_reg_mem_wen <= exe_reg_mem_wen @[src/main/scala/micore/Core.scala 231:19] + wb_reg_wb_addr <= mem_reg_wb_addr @[src/main/scala/micore/Core.scala 249:18] + wb_reg_rf_wen <= mem_reg_rf_wen @[src/main/scala/micore/Core.scala 250:17] + wb_reg_wb_data <= mem_wb_data @[src/main/scala/micore/Core.scala 251:18] + if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 54:{26,26} 73:13] + + module Memory : @[src/main/scala/micore/Memory.scala 20:7] + input clock : Clock @[src/main/scala/micore/Memory.scala 20:7] + input reset : UInt<1> @[src/main/scala/micore/Memory.scala 20:7] + input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + + mem mem : @[src/main/scala/micore/Memory.scala 27:24] + data-type => UInt<32> + depth => 512 + read-latency => 1 + write-latency => 1 + reader => io_imem_inst_MPORT + reader => io_dmem_rdata_MPORT + writer => MPORT + read-under-write => undefined + node _io_imem_inst_T = shr(io_imem_addr, 2) @[src/main/scala/micore/Memory.scala 31:41] + node _GEN_0 = validif(UInt<1>("h1"), _io_imem_inst_T) @[src/main/scala/micore/Memory.scala 31:{27,27}] + node _io_imem_inst_WIRE = _GEN_0 @[src/main/scala/micore/Memory.scala 31:27] + node _io_imem_inst_T_1 = bits(_io_imem_inst_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 31:27] + node _GEN_1 = mux(UInt<1>("h1"), UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 27:24 31:{27,27}] + node _GEN_2 = validif(UInt<1>("h1"), _io_imem_inst_T_1) @[src/main/scala/micore/Memory.scala 31:{27,27}] + node _GEN_3 = validif(UInt<1>("h1"), clock) @[src/main/scala/micore/Memory.scala 31:{27,27}] + node _io_dmem_rdata_T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 33:42] + node _GEN_4 = validif(UInt<1>("h1"), _io_dmem_rdata_T) @[src/main/scala/micore/Memory.scala 33:{28,28}] + node _io_dmem_rdata_WIRE = _GEN_4 @[src/main/scala/micore/Memory.scala 33:28] + node _io_dmem_rdata_T_1 = bits(_io_dmem_rdata_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 33:28] + node _GEN_5 = validif(UInt<1>("h1"), _io_dmem_rdata_T_1) @[src/main/scala/micore/Memory.scala 33:{28,28}] + node _T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 36:28] + node _T_1 = bits(_T, 8, 0) @[src/main/scala/micore/Memory.scala 36:14] + node _GEN_6 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 35:21 36:14] + node _GEN_7 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 35:21 36:14] + node _GEN_8 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 35:21 36:14 27:24] + node _GEN_9 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 35:21 36:14] + node _GEN_10 = validif(io_dmem_wen, io_dmem_wdata) @[src/main/scala/micore/Memory.scala 35:21 36:14] + io_imem_inst <= mem.io_imem_inst_MPORT.data @[src/main/scala/micore/Memory.scala 31:16] + io_dmem_rdata <= mem.io_dmem_rdata_MPORT.data @[src/main/scala/micore/Memory.scala 33:17] + mem.io_imem_inst_MPORT.addr <= _GEN_2 + mem.io_imem_inst_MPORT.en <= _GEN_1 + mem.io_imem_inst_MPORT.clk <= _GEN_3 + mem.io_dmem_rdata_MPORT.addr <= _GEN_5 + mem.io_dmem_rdata_MPORT.en <= _GEN_1 + mem.io_dmem_rdata_MPORT.clk <= _GEN_3 + mem.MPORT.addr <= _GEN_6 + mem.MPORT.en <= _GEN_8 + mem.MPORT.clk <= _GEN_7 + mem.MPORT.data <= _GEN_10 + mem.MPORT.mask <= _GEN_9 + + module TopOrigin : @[src/main/scala/micore/Top.scala 8:7] + input clock : Clock @[src/main/scala/micore/Top.scala 8:7] + input reset : UInt<1> @[src/main/scala/micore/Top.scala 8:7] + output io_exit : UInt<1> @[src/main/scala/micore/Top.scala 9:14] + + inst core of Core @[src/main/scala/micore/Top.scala 12:20] + inst memory of Memory @[src/main/scala/micore/Top.scala 13:22] + io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 18:11] + core.clock <= clock + core.reset <= reset + core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 15:16] + core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/micore/Top.scala 16:16] + memory.clock <= clock + memory.reset <= reset + memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/micore/Top.scala 15:16] + memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/micore/Top.scala 16:16] + memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/micore/Top.scala 16:16] + memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/micore/Top.scala 16:16] diff --git a/testbench.sv b/testbench.sv new file mode 100755 index 0000000..138f3af --- /dev/null +++ b/testbench.sv @@ -0,0 +1,85 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/28 11:36:13 +// Design Name: +// Module Name: testbench +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + + +module Top_tb; + + // 输入信号 + reg clock; + reg reset; + + // 输出信号 + wire io_exit; + wire [3:0] io_anodes; + wire [6:0] io_segments; + + // 内部信号（用于监视） + wire [31:0] pc; // 程序计数器 + wire [31:0] instruction; // 当前指令 + + // 实例化 Top 模块 + Top uut ( + .clock (clock), + .reset (reset), + .io_exit (io_exit), + .io_anodes (io_anodes), + .io_segments(io_segments) + ); + + // 连接到 Core 模块的内部信号 + assign pc = uut.core.if_reg_pc; // 假设 if_reg_pc 是 Core 模块中的 pc 寄存器 + assign instruction = uut.core.id_reg_inst; // 假设 id_reg_inst 是 Core 模块中的当前指令 + + // 时钟生成 + initial begin + clock = 0; + forever #5 clock = ~clock; // 10ns 周期时钟 + end + + // 测试逻辑 + initial begin + // 初始化信号 + reset = 1; + #20; // 等待 20ns + + // 释放复位信号 + reset = 0; + #200; // 等待 200ns + + // 观察 io_exit 信号 + if (io_exit) begin + $display("Test Passed: io_exit is high."); + end else begin + $display("Test Failed: io_exit is low."); + end + + // 结束仿真 + $finish; + end + + // 监视信号变化 + initial begin + $monitor("Time: %0t | Reset: %b | PC: %h | Instruction: %h | io_exit: %b", + $time, reset, pc, instruction, io_exit); + end + +endmodule