From 7ae5ee8c39015c2c8e6898866fd71af1079f76a2 Mon Sep 17 00:00:00 2001
From: CGH0S7 <776459475@qq.com>
Date: Wed, 1 Jan 2025 23:19:43 +0800
Subject: [PATCH] SystemVerilog Module Complete

---
 Core.sv                                       | 612 +++++++++-------
 display.sv => Display.sv                      |   0
 Memory.sv                                     | 171 +++--
 Regfile.sv                                    |  54 +-
 Top.sv                                        |  44 +-
 TopOrigin.sv                                  | 605 ++++++++++------
 src/main/scala/micore/Core.scala              |  18 +-
 target/scala-2.13/-name-_2.13-0.1.0.jar       | Bin 113378 -> 90878 bytes
 target/scala-2.13/zinc/inc_compile_2.13.zip   | Bin 22045 -> 22033 bytes
 .../compileIncremental/_global/streams/out    |  42 +-
 .../_global/streams/export                    |   2 +-
 .../compile/incOptions/_global/streams/out    |   9 +
 .../compile/packageBin/_global/streams/inputs |   2 +-
 .../compile/packageBin/_global/streams/out    | 100 ++-
 .../compile/packageBin/_global/streams/output |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../TopOrigin.lo.fir                          | 655 ++++++++++++++++++
 testbench.sv                                  | 129 ++--
 21 files changed, 1749 insertions(+), 704 deletions(-)
 rename display.sv => Display.sv (100%)
 create mode 100755 test_run_dir/Micore_should_run_the_test_program/TopOrigin.lo.fir

diff --git a/Core.sv b/Core.sv
index cc6c176..f5f086f 100755
--- a/Core.sv
+++ b/Core.sv
@@ -1,25 +1,24 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
+// Company:
+// Engineer:
+//
 // Create Date: 2024/12/28 11:25:38
-// Design Name: 
+// Design Name:
 // Module Name: Core
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module Core(
         input         clock,
         reset,
@@ -29,10 +28,13 @@ module Core(
         input  [31:0] io_dmem_rdata,
         output        io_dmem_wen,
         output [31:0] io_dmem_wdata,
-        output        io_exit,
-        output [31:0] s0_value
+        output [3:0]  io_anodes,
+        output [6:0]  io_segments,
+        output        io_exit
     );
 
+    wire        exe_jmp_flg;
+    wire        exe_br_flg;
     wire [31:0] _regfile_ext_R0_data;
     wire [31:0] _regfile_ext_R1_data;
     reg  [31:0] id_reg_pc;
@@ -41,275 +43,385 @@ module Core(
     reg  [4:0]  exe_reg_wb_addr;
     reg  [31:0] exe_reg_op1_data;
     reg  [31:0] exe_reg_op2_data;
-    reg  [31:0] exe_reg_rs2_data;
+    reg  [31:0] exe_reg_rt_data;
     reg  [4:0]  exe_reg_exe_fun;
     reg  [1:0]  exe_reg_mem_wen;
     reg  [1:0]  exe_reg_rf_wen;
     reg  [2:0]  exe_reg_wb_sel;
-    reg  [31:0] exe_reg_imm_b_sext;
+    reg  [31:0] exe_reg_imm_i_sext;
     reg  [31:0] mem_reg_pc;
     reg  [4:0]  mem_reg_wb_addr;
-    reg  [31:0] mem_reg_alu_out;
-    reg  [31:0] mem_reg_rs2_data;
+    reg  [31:0] mem_reg_rt_data;
+    reg  [1:0]  mem_reg_mem_wen;
     reg  [1:0]  mem_reg_rf_wen;
     reg  [2:0]  mem_reg_wb_sel;
-    reg  [1:0]  mem_reg_mem_wen;
+    reg  [31:0] mem_reg_alu_out;
     reg  [4:0]  wb_reg_wb_addr;
     reg  [1:0]  wb_reg_rf_wen;
     reg  [31:0] wb_reg_wb_data;
     reg  [31:0] if_reg_pc;
-    wire        _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
-    wire        exe_br_flg =
-                exe_reg_exe_fun == 5'hC
-                ? exe_reg_op1_data != exe_reg_op2_data
-                : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
-    wire        exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+    wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
+    wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
+    wire        stall_flg =
+                _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
+                | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+    wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
+    wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
+    wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
+    wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
+    wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
+    wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
+    wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
+    wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
+    wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
+    wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
+    wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
+    wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
+    wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
+    wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+    wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
+    wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
+    wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
+    wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
+    wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
+    wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
+    wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
+    wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
+    wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
+    wire [31:0] exe_alu_out =
+         _exe_alu_out_T
+         ? _exe_alu_out_T_1
+         : _exe_alu_out_T_3
+         ? _exe_alu_out_T_4
+         : _exe_alu_out_T_6
+         ? _exe_alu_out_T_7
+         : _exe_alu_out_T_8
+         ? _exe_alu_out_T_9
+         : _exe_alu_out_T_10
+         ? _exe_alu_out_T_11
+         : _exe_alu_out_T_12
+         ? _exe_alu_out_T_14[31:0]
+         : _exe_alu_out_T_16
+         ? _exe_alu_out_T_18
+         : _exe_alu_out_T_19
+         ? _exe_alu_out_T_22
+         : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
+    assign exe_br_flg =
+           exe_reg_exe_fun == 5'hB
+           ? exe_reg_op1_data == exe_reg_op2_data
+           : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
+    assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+    wire [31:0] mem_wb_data =
+         mem_reg_wb_sel == 3'h2
+         ? io_dmem_rdata
+         : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
     always @(posedge clock) begin
-        automatic logic        _id_inst_T = exe_br_flg | exe_jmp_flg;
-        automatic logic        _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
-        automatic logic        stall_flg;
-        automatic logic [31:0] id_inst;
-        automatic logic        _id_rs2_data_T_2;
-        automatic logic        _id_rs2_data_T;
-        automatic logic [31:0] _id_rs2_data_T_8;
-        automatic logic [16:0] _GEN;
-        automatic logic        _csignals_T_5;
-        automatic logic [19:0] _GEN_0;
-        automatic logic        _csignals_T_7;
-        automatic logic        _csignals_T_9;
-        automatic logic        _csignals_T_11;
-        automatic logic        _csignals_T_13;
-        automatic logic        _csignals_T_15;
-        automatic logic        _csignals_T_17;
-        automatic logic        _csignals_T_19;
-        automatic logic [16:0] _GEN_1;
-        automatic logic        _csignals_T_21;
-        automatic logic        _csignals_T_23;
-        automatic logic        _csignals_T_25;
-        automatic logic        _csignals_T_27;
-        automatic logic        _csignals_T_29;
-        automatic logic        _csignals_T_31;
-        automatic logic        _csignals_T_33;
-        automatic logic        _csignals_T_35;
-        automatic logic        _csignals_T_37;
-        automatic logic        _csignals_T_39;
-        automatic logic        _GEN_2;
-        automatic logic        _GEN_3;
-        automatic logic [1:0]  csignals_1;
-        automatic logic [2:0]  _csignals_T_95;
-        automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
-        automatic logic [62:0] _exe_alu_out_T_8 =
-                  {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
-        automatic logic [31:0] exe_alu_out;
-        stall_flg =
-            _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
-            & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
-            & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
-        id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
-        _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
-        _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
-        _id_rs2_data_T_8 =
-            id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
-            ? mem_reg_alu_out
-            : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
-            ? wb_reg_wb_data
-            : _regfile_ext_R0_data;
-        _GEN = {id_inst[31:26], id_inst[10:0]};
-        _csignals_T_5 = _GEN == 17'h20;
-        _GEN_0 = {id_inst[31:28], id_inst[15:0]};
-        _csignals_T_7 = _GEN_0 == 20'h80000;
-        _csignals_T_9 = _GEN == 17'h22;
-        _csignals_T_11 = _GEN == 17'h24;
-        _csignals_T_13 = _GEN == 17'h25;
-        _csignals_T_15 = _GEN == 17'h26;
-        _csignals_T_17 = _GEN_0 == 20'hC0000;
-        _csignals_T_19 = _GEN_0 == 20'hD0000;
-        _GEN_1 = {id_inst[30:20], id_inst[5:0]};
-        _csignals_T_21 = _GEN_1 == 17'h0;
-        _csignals_T_23 = _GEN_1 == 17'h2;
-        _csignals_T_25 = _GEN_1 == 17'h3;
-        _csignals_T_27 = _GEN == 17'h2A;
-        _csignals_T_29 = _GEN_0 == 20'h40000;
-        _csignals_T_31 = _GEN_0 == 20'h50000;
-        _csignals_T_33 = id_inst == 32'hC000000;
-        _csignals_T_35 = _GEN_0 == 20'h8;
-        _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
-        _csignals_T_39 = id_inst == 32'h0;
-        _GEN_2 = _csignals_T_29 | _csignals_T_31;
-        _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
-        csignals_1 =
-            _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-            | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
-            ? 2'h0
-            : _csignals_T_33
-            ? 2'h1
-            : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
-        _csignals_T_95 =
-            _csignals_T_5
-            ? 3'h1
-            : _csignals_T_7
-            ? 3'h2
-            : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
-            ? 3'h1
-            : _csignals_T_17 | _csignals_T_19
-            ? 3'h2
-            : _GEN_3
-            ? 3'h1
-            : _csignals_T_33
-            ? 3'h4
-            : _csignals_T_35
-            ? 3'h0
-            : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
-        exe_alu_out =
-            exe_reg_exe_fun == 5'hE
-            ? exe_reg_op1_data
-            : exe_reg_exe_fun == 5'h9
-            ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
-            : exe_reg_exe_fun == 5'h8
-            ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
-            : exe_reg_exe_fun == 5'h7
-            ? exe_reg_op1_data >> _GEN_4
-            : exe_reg_exe_fun == 5'h6
-            ? _exe_alu_out_T_8[31:0]
-            : exe_reg_exe_fun == 5'h5
-            ? exe_reg_op1_data ^ exe_reg_op2_data
-            : exe_reg_exe_fun == 5'h4
-            ? exe_reg_op1_data | exe_reg_op2_data
-            : exe_reg_exe_fun == 5'h3
-            ? exe_reg_op1_data & exe_reg_op2_data
-            : exe_reg_exe_fun == 5'h2
-            ? exe_reg_op1_data - exe_reg_op2_data
-            : exe_reg_exe_fun == 5'h1
-            ? exe_reg_op1_data + exe_reg_op2_data
-            : 32'h0;
-        if (~stall_flg)
-            id_reg_pc <= if_reg_pc;
-        if (_id_inst_T)
+        if (reset) begin
+            id_reg_pc <= 32'h0;
             id_reg_inst <= 32'h0;
-        else if (~stall_flg)
-            id_reg_inst <= io_imem_inst;
-        exe_reg_pc <= id_reg_pc;
-        exe_reg_wb_addr <= id_reg_inst[15:11];
-        if (csignals_1 == 2'h0)
-            exe_reg_op1_data <=
-                             id_reg_inst[25:21] == 5'h0
-                             ? 32'h0
-                             : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
-                             ? mem_reg_alu_out
-                             : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
-                             ? wb_reg_wb_data
-                             : _regfile_ext_R1_data;
-        else if (csignals_1 == 2'h1)
-            exe_reg_op1_data <= id_reg_pc;
-        else
+            exe_reg_pc <= 32'h0;
+            exe_reg_wb_addr <= 5'h0;
             exe_reg_op1_data <= 32'h0;
-        if (_csignals_T_95 == 3'h5)
-            exe_reg_op2_data <= {id_inst[15:0], 16'h0};
-        else if (_csignals_T_95 == 3'h4)
-            exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
-        else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
-            exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
-        else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
             exe_reg_op2_data <= 32'h0;
-        else
-            exe_reg_op2_data <= _id_rs2_data_T_8;
-        exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
-        if (_csignals_T_5 | _csignals_T_7)
-            exe_reg_exe_fun <= 5'h1;
-        else if (_csignals_T_9)
-            exe_reg_exe_fun <= 5'h2;
-        else if (_csignals_T_11)
-            exe_reg_exe_fun <= 5'h3;
-        else if (_csignals_T_13)
-            exe_reg_exe_fun <= 5'h4;
-        else if (_csignals_T_15)
-            exe_reg_exe_fun <= 5'h5;
-        else if (_csignals_T_17)
-            exe_reg_exe_fun <= 5'h3;
-        else if (_csignals_T_19)
-            exe_reg_exe_fun <= 5'h4;
-        else if (_csignals_T_21)
-            exe_reg_exe_fun <= 5'h6;
-        else if (_csignals_T_23)
-            exe_reg_exe_fun <= 5'h7;
-        else if (_csignals_T_25)
-            exe_reg_exe_fun <= 5'h8;
-        else if (_csignals_T_27)
-            exe_reg_exe_fun <= 5'h9;
-        else if (_csignals_T_29)
-            exe_reg_exe_fun <= 5'hB;
-        else if (_csignals_T_31)
-            exe_reg_exe_fun <= 5'hC;
-        else if (_csignals_T_33)
-            exe_reg_exe_fun <= 5'h1;
-        else if (_csignals_T_35)
-            exe_reg_exe_fun <= 5'hE;
-        else
-            exe_reg_exe_fun <= {4'h0, _csignals_T_37};
-        exe_reg_mem_wen <= 2'h0;
-        if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-                | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
-                | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
-            exe_reg_rf_wen <= 2'h1;
-            exe_reg_wb_sel <= 3'h1;
-        end
-        else if (_GEN_2) begin
-            exe_reg_rf_wen <= 2'h0;
-            exe_reg_wb_sel <= 3'h0;
-        end
-        else if (_csignals_T_33) begin
-            exe_reg_rf_wen <= 2'h1;
-            exe_reg_wb_sel <= 3'h3;
-        end
-        else if (_csignals_T_35) begin
+            exe_reg_rt_data <= 32'h0;
+            exe_reg_exe_fun <= 5'h0;
+            exe_reg_mem_wen <= 2'h0;
             exe_reg_rf_wen <= 2'h0;
             exe_reg_wb_sel <= 3'h0;
+            exe_reg_imm_i_sext <= 32'h0;
+            mem_reg_pc <= 32'h0;
+            mem_reg_wb_addr <= 5'h0;
+            mem_reg_rt_data <= 32'h0;
+            mem_reg_mem_wen <= 2'h0;
+            mem_reg_rf_wen <= 2'h0;
+            mem_reg_wb_sel <= 3'h0;
+            mem_reg_alu_out <= 32'h0;
+            wb_reg_wb_addr <= 5'h0;
+            wb_reg_rf_wen <= 2'h0;
+            wb_reg_wb_data <= 32'h0;
+            if_reg_pc <= 32'h0;
         end
         else begin
-            exe_reg_rf_wen <= {1'h0, _csignals_T_37};
-            exe_reg_wb_sel <= {2'h0, _csignals_T_37};
+            automatic logic        _id_rt_data_T_5;
+            automatic logic        _id_rt_data_T;
+            automatic logic        _id_rt_data_T_3;
+            automatic logic        _id_rt_data_T_6;
+            automatic logic        _id_rt_data_T_9;
+            automatic logic [31:0] id_imm_i_sext;
+            automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
+            automatic logic        _csignals_T_3;
+            automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
+            automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
+            automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
+            automatic logic        _csignals_T_9;
+            automatic logic        _csignals_T_11;
+            automatic logic        _csignals_T_13;
+            automatic logic        _csignals_T_15;
+            automatic logic        _csignals_T_17;
+            automatic logic        _csignals_T_19;
+            automatic logic        _csignals_T_21;
+            automatic logic        _csignals_T_23;
+            automatic logic        _csignals_T_25;
+            automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
+            automatic logic        _csignals_T_27;
+            automatic logic        _csignals_T_29;
+            automatic logic        _csignals_T_31;
+            automatic logic        _csignals_T_33;
+            automatic logic        _csignals_T_35;
+            automatic logic        _GEN_3;
+            automatic logic        _GEN_4;
+            automatic logic [1:0]  csignals_1;
+            automatic logic [2:0]  csignals_2;
+            automatic logic        _GEN_5;
+            automatic logic        _GEN_6;
+            _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
+            _id_rt_data_T = id_inst[20:16] == 5'h0;
+            _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
+            _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
+            _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
+            id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
+            _csignals_T_3 = id_inst[31:26] == 6'h2B;
+            _csignals_T_9 = _GEN_1 == 12'h22;
+            _csignals_T_11 = _GEN_1 == 12'h24;
+            _csignals_T_13 = _GEN_1 == 12'h25;
+            _csignals_T_15 = _GEN_1 == 12'h26;
+            _csignals_T_17 = id_inst[31:26] == 6'hC;
+            _csignals_T_19 = id_inst[31:26] == 6'hD;
+            _csignals_T_21 = _GEN_1 == 12'h2A;
+            _csignals_T_23 = id_inst[31:26] == 6'h4;
+            _csignals_T_25 = id_inst[31:26] == 6'h5;
+            _csignals_T_27 = _GEN_2 == 17'h0;
+            _csignals_T_29 = _GEN_2 == 17'h2;
+            _csignals_T_31 = _GEN_2 == 17'h3;
+            _csignals_T_33 = id_inst[31:26] == 6'h3;
+            _csignals_T_35 = _GEN_1 == 12'h8;
+            _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+            _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
+            csignals_1 =
+                _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+                | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
+                | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
+                ? 2'h1
+                : 2'h2;
+            csignals_2 =
+                _csignals_T_1 | _csignals_T_3
+                ? 3'h2
+                : _csignals_T_5
+                ? 3'h1
+                : _csignals_T_7
+                ? 3'h2
+                : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                ? 3'h1
+                : _csignals_T_17 | _csignals_T_19
+                ? 3'h2
+                : _GEN_4
+                ? 3'h1
+                : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+            _GEN_5 = _csignals_T_23 | _csignals_T_25;
+            _GEN_6 =
+                _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+                | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+            if (~stall_flg)
+                id_reg_pc <= if_reg_pc;
+            if (_id_inst_T)
+                id_reg_inst <= 32'h20000000;
+            else if (~stall_flg)
+                id_reg_inst <= io_imem_inst;
+            exe_reg_pc <= id_reg_pc;
+            if ((_csignals_T_1
+                    ? 3'h2
+                    : _csignals_T_3
+                    ? 3'h0
+                    : _GEN_6
+                    ? 3'h1
+                    : _GEN_5
+                    ? 3'h0
+                    : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+                    & id_inst[31:26] == 6'h0)
+                exe_reg_wb_addr <= id_inst[15:11];
+            else if (id_inst[31:26] == 6'h3)
+                exe_reg_wb_addr <= 5'h1F;
+            else
+                exe_reg_wb_addr <= id_inst[20:16];
+            if (csignals_1 == 2'h1) begin
+                if (id_inst[25:21] == 5'h0)
+                    exe_reg_op1_data <= 32'h0;
+                else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+                    if (_exe_alu_out_T)
+                        exe_reg_op1_data <= _exe_alu_out_T_1;
+                    else if (_exe_alu_out_T_3)
+                        exe_reg_op1_data <= _exe_alu_out_T_4;
+                    else if (_exe_alu_out_T_6)
+                        exe_reg_op1_data <= _exe_alu_out_T_7;
+                    else if (_exe_alu_out_T_8)
+                        exe_reg_op1_data <= _exe_alu_out_T_9;
+                    else if (_exe_alu_out_T_10)
+                        exe_reg_op1_data <= _exe_alu_out_T_11;
+                    else if (_exe_alu_out_T_12)
+                        exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+                    else if (_exe_alu_out_T_16)
+                        exe_reg_op1_data <= _exe_alu_out_T_18;
+                    else if (_exe_alu_out_T_19)
+                        exe_reg_op1_data <= _exe_alu_out_T_22;
+                    else if (_exe_alu_out_T_24)
+                        exe_reg_op1_data <= _GEN_0;
+                    else if (~_exe_alu_out_T_28)
+                        exe_reg_op1_data <= 32'h0;
+                end
+                else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
+                    exe_reg_op1_data <= mem_wb_data;
+                else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
+                    exe_reg_op1_data <= wb_reg_wb_data;
+                else
+                    exe_reg_op1_data <= _regfile_ext_R1_data;
+            end
+            else if (csignals_1 == 2'h2)
+                exe_reg_op1_data <= id_reg_pc;
+            else
+                exe_reg_op1_data <= 32'h0;
+            if (csignals_2 == 3'h1) begin
+                if (_id_rt_data_T)
+                    exe_reg_op2_data <= 32'h0;
+                else if (_id_rt_data_T_3) begin
+                    if (_exe_alu_out_T)
+                        exe_reg_op2_data <= _exe_alu_out_T_1;
+                    else if (_exe_alu_out_T_3)
+                        exe_reg_op2_data <= _exe_alu_out_T_4;
+                    else if (_exe_alu_out_T_6)
+                        exe_reg_op2_data <= _exe_alu_out_T_7;
+                    else if (_exe_alu_out_T_8)
+                        exe_reg_op2_data <= _exe_alu_out_T_9;
+                    else if (_exe_alu_out_T_10)
+                        exe_reg_op2_data <= _exe_alu_out_T_11;
+                    else if (_exe_alu_out_T_12)
+                        exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
+                    else if (_exe_alu_out_T_16)
+                        exe_reg_op2_data <= _exe_alu_out_T_18;
+                    else if (_exe_alu_out_T_19)
+                        exe_reg_op2_data <= _exe_alu_out_T_22;
+                    else if (_exe_alu_out_T_24)
+                        exe_reg_op2_data <= _GEN_0;
+                    else
+                        exe_reg_op2_data <= _exe_alu_out_T_29;
+                end
+                else if (_id_rt_data_T_6)
+                    exe_reg_op2_data <= mem_wb_data;
+                else if (_id_rt_data_T_9)
+                    exe_reg_op2_data <= wb_reg_wb_data;
+                else
+                    exe_reg_op2_data <= _regfile_ext_R0_data;
+            end
+            else if (csignals_2 == 3'h2)
+                exe_reg_op2_data <= id_imm_i_sext;
+            else if (csignals_2 == 3'h4)
+                exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+            else
+                exe_reg_op2_data <= 32'h0;
+            exe_reg_rt_data <=
+                            _id_rt_data_T
+                            ? 32'h0
+                            : _id_rt_data_T_3
+                            ? exe_alu_out
+                            : _id_rt_data_T_6
+                            ? mem_wb_data
+                            : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+            if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+                exe_reg_exe_fun <= 5'h1;
+            else if (_csignals_T_9)
+                exe_reg_exe_fun <= 5'h2;
+            else if (_csignals_T_11)
+                exe_reg_exe_fun <= 5'h3;
+            else if (_csignals_T_13)
+                exe_reg_exe_fun <= 5'h4;
+            else if (_csignals_T_15)
+                exe_reg_exe_fun <= 5'h5;
+            else if (_csignals_T_17)
+                exe_reg_exe_fun <= 5'h3;
+            else if (_csignals_T_19)
+                exe_reg_exe_fun <= 5'h4;
+            else if (_csignals_T_21)
+                exe_reg_exe_fun <= 5'h9;
+            else if (_csignals_T_23)
+                exe_reg_exe_fun <= 5'hB;
+            else if (_csignals_T_25)
+                exe_reg_exe_fun <= 5'hC;
+            else if (_csignals_T_27)
+                exe_reg_exe_fun <= 5'h6;
+            else if (_csignals_T_29)
+                exe_reg_exe_fun <= 5'h7;
+            else if (_csignals_T_31)
+                exe_reg_exe_fun <= 5'h8;
+            else if (_csignals_T_33)
+                exe_reg_exe_fun <= 5'h1;
+            else if (_csignals_T_35)
+                exe_reg_exe_fun <= 5'hD;
+            else
+                exe_reg_exe_fun <= 5'h0;
+            exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+            if (_csignals_T_1) begin
+                exe_reg_rf_wen <= 2'h1;
+                exe_reg_wb_sel <= 3'h2;
+            end
+            else if (_csignals_T_3) begin
+                exe_reg_rf_wen <= 2'h0;
+                exe_reg_wb_sel <= 3'h0;
+            end
+            else if (_GEN_6) begin
+                exe_reg_rf_wen <= 2'h1;
+                exe_reg_wb_sel <= 3'h1;
+            end
+            else if (_GEN_5) begin
+                exe_reg_rf_wen <= 2'h0;
+                exe_reg_wb_sel <= 3'h0;
+            end
+            else begin
+                exe_reg_rf_wen <=
+                               {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+                if (_GEN_3)
+                    exe_reg_wb_sel <= 3'h1;
+                else if (_csignals_T_33)
+                    exe_reg_wb_sel <= 3'h3;
+                else
+                    exe_reg_wb_sel <= 3'h0;
+            end
+            exe_reg_imm_i_sext <= id_imm_i_sext;
+            mem_reg_pc <= exe_reg_pc;
+            mem_reg_wb_addr <= exe_reg_wb_addr;
+            mem_reg_rt_data <= exe_reg_rt_data;
+            mem_reg_mem_wen <= exe_reg_mem_wen;
+            mem_reg_rf_wen <= exe_reg_rf_wen;
+            mem_reg_wb_sel <= exe_reg_wb_sel;
+            mem_reg_alu_out <= exe_alu_out;
+            wb_reg_wb_addr <= mem_reg_wb_addr;
+            wb_reg_rf_wen <= mem_reg_rf_wen;
+            wb_reg_wb_data <= mem_wb_data;
+            if (exe_br_flg)
+                if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
+            else if (exe_jmp_flg)
+                if_reg_pc <= exe_alu_out;
+            else if (~stall_flg)
+                if_reg_pc <= if_reg_pc + 32'h4;
         end
-        exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
-        mem_reg_pc <= exe_reg_pc;
-        mem_reg_wb_addr <= exe_reg_wb_addr;
-        mem_reg_alu_out <= exe_alu_out;
-        mem_reg_rs2_data <= exe_reg_rs2_data;
-        mem_reg_rf_wen <= exe_reg_rf_wen;
-        mem_reg_wb_sel <= exe_reg_wb_sel;
-        mem_reg_mem_wen <= exe_reg_mem_wen;
-        wb_reg_wb_addr <= mem_reg_wb_addr;
-        wb_reg_rf_wen <= mem_reg_rf_wen;
-        wb_reg_wb_data <=
-                       mem_reg_wb_sel == 3'h3
-                       ? mem_reg_pc + 32'h4
-                       : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
-        if (reset)
-            if_reg_pc <= 32'h0;
-        else if (exe_br_flg)
-            if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
-        else if (exe_jmp_flg)
-            if_reg_pc <= exe_alu_out;
-        else if (~stall_flg)
-            if_reg_pc <= if_reg_pc + 32'h4;
     end // always @(posedge)
     regfile_32x32 regfile_ext (
-                      .R0_addr (id_reg_inst[20:16]),
+                      .R0_addr (id_inst[20:16]),
                       .R0_en   (1'h1),
                       .R0_clk  (clock),
                       .R0_data (_regfile_ext_R0_data),
-                      .R1_addr (id_reg_inst[25:21]),
+                      .R1_addr (id_inst[25:21]),
                       .R1_en   (1'h1),
                       .R1_clk  (clock),
                       .R1_data (_regfile_ext_R1_data),
                       .W0_addr (wb_reg_wb_addr),
-                      .W0_en   (_id_rs2_data_T_5),
+                      .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
                       .W0_clk  (clock),
+                      .io_anodes (io_anodes),
+                      .io_segments (io_segments),
                       .W0_data (wb_reg_wb_data)
                   );
     assign io_imem_addr = if_reg_pc;
     assign io_dmem_addr = mem_reg_alu_out;
     assign io_dmem_wen = mem_reg_mem_wen[0];
-    assign io_dmem_wdata = mem_reg_rs2_data;
-    assign io_exit = id_reg_inst == 32'h00000000;
-    assign s0_value = _regfile_ext_R0_data;
+    assign io_dmem_wdata = mem_reg_rt_data;
+    assign io_exit = id_reg_inst == 32'h114514;
 endmodule
diff --git a/display.sv b/Display.sv
similarity index 100%
rename from display.sv
rename to Display.sv
diff --git a/Memory.sv b/Memory.sv
index 1ee13a7..32e9c87 100755
--- a/Memory.sv
+++ b/Memory.sv
@@ -1,64 +1,98 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
+// Company:
+// Engineer:
+//
 // Create Date: 2024/12/28 11:28:52
-// Design Name: 
+// Design Name:
 // Module Name: Regfile
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
-
-
-module mem_512x32(
-        input  [8:0]  R0_addr,
+module mem_4096x8(
+        input  [11:0] R0_addr,
         input         R0_en,
         R0_clk,
-        output [31:0] R0_data,
-        input  [8:0]  R1_addr,
+        output [7:0]  R0_data,
+        input  [11:0] R1_addr,
         input         R1_en,
         R1_clk,
-        output [31:0] R1_data,
-        input  [8:0]  W0_addr,
+        output [7:0]  R1_data,
+        input  [11:0] R2_addr,
+        input         R2_en,
+        R2_clk,
+        output [7:0]  R2_data,
+        input  [11:0] R3_addr,
+        input         R3_en,
+        R3_clk,
+        output [7:0]  R3_data,
+        input  [11:0] R4_addr,
+        input         R4_en,
+        R4_clk,
+        output [7:0]  R4_data,
+        input  [11:0] R5_addr,
+        input         R5_en,
+        R5_clk,
+        output [7:0]  R5_data,
+        input  [11:0] R6_addr,
+        input         R6_en,
+        R6_clk,
+        output [7:0]  R6_data,
+        input  [11:0] R7_addr,
+        input         R7_en,
+        R7_clk,
+        output [7:0]  R7_data,
+        input  [11:0] W0_addr,
         input         W0_en,
         W0_clk,
-        input  [31:0] W0_data
+        input  [7:0]  W0_data,
+        input  [11:0] W1_addr,
+        input         W1_en,
+        W1_clk,
+        input  [7:0]  W1_data,
+        input  [11:0] W2_addr,
+        input         W2_en,
+        W2_clk,
+        input  [7:0]  W2_data,
+        input  [11:0] W3_addr,
+        input         W3_en,
+        W3_clk,
+        input  [7:0]  W3_data
     );
 
-    reg [31:0] Memory[0:511];
-    reg        _R0_en_d0;
-    reg [8:0]  _R0_addr_d0;
-    always @(posedge R0_clk) begin
-        _R0_en_d0 <= R0_en;
-        _R0_addr_d0 <= R0_addr;
-    end // always @(posedge)
-    reg        _R1_en_d0;
-    reg [8:0]  _R1_addr_d0;
-    always @(posedge R1_clk) begin
-        _R1_en_d0 <= R1_en;
-        _R1_addr_d0 <= R1_addr;
-    end // always @(posedge)
+    reg [7:0] Memory[0:4095];
     always @(posedge W0_clk) begin
         if (W0_en & 1'h1)
             Memory[W0_addr] <= W0_data;
+        if (W1_en & 1'h1)
+            Memory[W1_addr] <= W1_data;
+        if (W2_en & 1'h1)
+            Memory[W2_addr] <= W2_data;
+        if (W3_en & 1'h1)
+            Memory[W3_addr] <= W3_data;
     end // always @(posedge)
 `ifdef ENABLE_INITIAL_MEM_
     initial
         $readmemh("src/hex/mem.hex", Memory);
 `endif // ENABLE_INITIAL_MEM_
 
-    assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-    assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
+    assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
+    assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
+    assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
+    assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
+    assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
+    assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
+    assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
+    assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
 endmodule
 
 module Memory(
@@ -71,18 +105,69 @@ module Memory(
         input  [31:0] io_dmem_wdata
     );
 
-    mem_512x32 mem_ext (
-                   .R0_addr (io_imem_addr[10:2]),
+    wire [7:0]  _mem_ext_R0_data;
+    wire [7:0]  _mem_ext_R1_data;
+    wire [7:0]  _mem_ext_R2_data;
+    wire [7:0]  _mem_ext_R3_data;
+    wire [7:0]  _mem_ext_R4_data;
+    wire [7:0]  _mem_ext_R5_data;
+    wire [7:0]  _mem_ext_R6_data;
+    wire [7:0]  _mem_ext_R7_data;
+    wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
+    wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
+    wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
+    mem_4096x8 mem_ext (
+                   .R0_addr (io_imem_addr[11:0]),
                    .R0_en   (1'h1),
                    .R0_clk  (clock),
-                   .R0_data (io_imem_inst),
-                   .R1_addr (io_dmem_addr[10:2]),
+                   .R0_data (_mem_ext_R0_data),
+                   .R1_addr (io_imem_addr[11:0] + 12'h1),
                    .R1_en   (1'h1),
                    .R1_clk  (clock),
-                   .R1_data (io_dmem_rdata),
-                   .W0_addr (io_dmem_addr[10:2]),
+                   .R1_data (_mem_ext_R1_data),
+                   .R2_addr (io_imem_addr[11:0] + 12'h2),
+                   .R2_en   (1'h1),
+                   .R2_clk  (clock),
+                   .R2_data (_mem_ext_R2_data),
+                   .R3_addr (io_imem_addr[11:0] + 12'h3),
+                   .R3_en   (1'h1),
+                   .R3_clk  (clock),
+                   .R3_data (_mem_ext_R3_data),
+                   .R4_addr (io_dmem_addr[11:0]),
+                   .R4_en   (1'h1),
+                   .R4_clk  (clock),
+                   .R4_data (_mem_ext_R4_data),
+                   .R5_addr (_io_dmem_rdata_T_6),
+                   .R5_en   (1'h1),
+                   .R5_clk  (clock),
+                   .R5_data (_mem_ext_R5_data),
+                   .R6_addr (_io_dmem_rdata_T_3),
+                   .R6_en   (1'h1),
+                   .R6_clk  (clock),
+                   .R6_data (_mem_ext_R6_data),
+                   .R7_addr (_io_dmem_rdata_T),
+                   .R7_en   (1'h1),
+                   .R7_clk  (clock),
+                   .R7_data (_mem_ext_R7_data),
+                   .W0_addr (_io_dmem_rdata_T),
                    .W0_en   (io_dmem_wen),
                    .W0_clk  (clock),
-                   .W0_data (io_dmem_wdata)
+                   .W0_data (io_dmem_wdata[31:24]),
+                   .W1_addr (_io_dmem_rdata_T_3),
+                   .W1_en   (io_dmem_wen),
+                   .W1_clk  (clock),
+                   .W1_data (io_dmem_wdata[23:16]),
+                   .W2_addr (_io_dmem_rdata_T_6),
+                   .W2_en   (io_dmem_wen),
+                   .W2_clk  (clock),
+                   .W2_data (io_dmem_wdata[15:8]),
+                   .W3_addr (io_dmem_addr[11:0]),
+                   .W3_en   (io_dmem_wen),
+                   .W3_clk  (clock),
+                   .W3_data (io_dmem_wdata[7:0])
                );
+    assign io_imem_inst =
+           {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
+    assign io_dmem_rdata =
+           {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
 endmodule
diff --git a/Regfile.sv b/Regfile.sv
index 27e1e0d..f9781d6 100755
--- a/Regfile.sv
+++ b/Regfile.sv
@@ -1,25 +1,23 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
+// Company:
+// Engineer:
+//
 // Create Date: 2024/12/28 11:28:52
-// Design Name: 
+// Design Name:
 // Module Name: Regfile
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
-
-
 module regfile_32x32(
         input  [4:0]  R0_addr,
         input         R0_en,
@@ -32,27 +30,25 @@ module regfile_32x32(
         input  [4:0]  W0_addr,
         input         W0_en,
         W0_clk,
+        output [3:0]  io_anodes,
+        output [6:0]  io_segments,
         input  [31:0] W0_data
     );
 
     reg [31:0] Memory[0:31];
-    reg        _R0_en_d0;
-    reg [4:0]  _R0_addr_d0;
-    always @(posedge R0_clk) begin
-        _R0_en_d0 <= R0_en;
-        _R0_addr_d0 <= R0_addr;
-    end // always @(posedge)
-    reg        _R1_en_d0;
-    reg [4:0]  _R1_addr_d0;
-    always @(posedge R1_clk) begin
-        _R1_en_d0 <= R1_en;
-        _R1_addr_d0 <= R1_addr;
-    end // always @(posedge)
     always @(posedge W0_clk) begin
         if (W0_en & 1'h1)
             Memory[W0_addr] <= W0_data;
     end // always @(posedge)
-    assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-    assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
-
+    assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
+    assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+    wire [31:0] reg16_value = Memory[16];
+    DynamicDisplay display (
+                       .clock        (W0_clk),
+                       .reset        (1'b0),
+                       .reg_result   (reg16_value),
+                       .io_anodes    (io_anodes),
+                       .io_segments  (io_segments)
+                   );
 endmodule
+
diff --git a/Top.sv b/Top.sv
index 0dcb976..fdd56e8 100755
--- a/Top.sv
+++ b/Top.sv
@@ -1,31 +1,30 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
+// Company:
+// Engineer:
+//
 // Create Date: 2024/12/28 11:25:38
-// Design Name: 
+// Design Name:
 // Module Name: Core
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module Top(
         input  clock,
         reset,
         output io_exit,
-        output [3:0] io_anodes,    // 新增：七段显示器的阳极控制信号
-        output [6:0] io_segments   // 新增：七段显示器的段控制信号
+        output [3:0] io_anodes,
+        output [6:0] io_segments
     );
 
     wire [31:0] _memory_io_imem_inst;
@@ -34,7 +33,6 @@ module Top(
     wire [31:0] _core_io_dmem_addr;
     wire        _core_io_dmem_wen;
     wire [31:0] _core_io_dmem_wdata;
-    wire [31:0] _core_s0_value;
     Core core (
              .clock         (clock),
              .reset         (reset),
@@ -44,8 +42,9 @@ module Top(
              .io_dmem_rdata (_memory_io_dmem_rdata),
              .io_dmem_wen   (_core_io_dmem_wen),
              .io_dmem_wdata (_core_io_dmem_wdata),
-             .io_exit       (io_exit),
-             .s0_value      (_core_s0_value)
+             .io_anodes     (io_anodes),
+             .io_segments   (io_segments),
+             .io_exit       (io_exit)
          );
     Memory memory (
                .clock         (clock),
@@ -56,13 +55,4 @@ module Top(
                .io_dmem_wen   (_core_io_dmem_wen),
                .io_dmem_wdata (_core_io_dmem_wdata)
            );
-        // 实例化 DynamicDisplay 模块
-    DynamicDisplay display (
-        .clock      (clock),
-        .reset      (reset),
-        .reg_result (_core_s0_value), // 连接 $s0 的值
-        .io_anodes  (io_anodes),      // 连接七段显示器的阳极控制信号
-        .io_segments(io_segments)     // 连接七段显示器的段控制信号
-    );
 endmodule
-
diff --git a/TopOrigin.sv b/TopOrigin.sv
index cebee7d..fd6fcc3 100755
--- a/TopOrigin.sv
+++ b/TopOrigin.sv
@@ -1,15 +1,4 @@
 // Generated by CIRCT firtool-1.62.0
-// Standard header to adapt well known macros for prints and assertions.
-
-// Users can define 'PRINTF_COND' to add an extra gate to prints.
-`ifndef PRINTF_COND_
-  `ifdef PRINTF_COND
-    `define PRINTF_COND_ (`PRINTF_COND)
-  `else  // PRINTF_COND
-    `define PRINTF_COND_ 1
-  `endif // PRINTF_COND
-`endif // not def PRINTF_COND_
-
 // VCS coverage exclude_file
 module regfile_32x32(
   input  [4:0]  R0_addr,
@@ -47,239 +36,395 @@ module Core(
   output        io_exit
 );
 
+  wire        exe_jmp_flg;
+  wire        exe_br_flg;
   wire [31:0] _regfile_ext_R0_data;
   wire [31:0] _regfile_ext_R1_data;
-  reg  [31:0] pc_reg;
-  wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
-  wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
-  wire        jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
-  wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
-  wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
-  wire        _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
-  wire        _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
-  wire        _csignals_T_5 = _GEN == 12'h20;
-  wire        _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
-  wire        _csignals_T_9 = _GEN == 12'h22;
-  wire        _csignals_T_11 = _GEN == 12'h24;
-  wire        _csignals_T_13 = _GEN == 12'h25;
-  wire        _csignals_T_15 = _GEN == 12'h26;
-  wire        _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
-  wire        _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
-  wire        _csignals_T_21 = _GEN == 12'h2A;
-  wire        _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
-  wire        _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
-  wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
-  wire        _csignals_T_27 = _GEN_0 == 17'h0;
-  wire        _csignals_T_29 = _GEN_0 == 17'h2;
-  wire        _csignals_T_31 = _GEN_0 == 17'h3;
-  wire        _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
-  wire        _csignals_T_35 = _GEN == 12'h8;
-  wire [4:0]  csignals_0 =
-    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
-      ? 5'h1
-      : _csignals_T_9
-          ? 5'h2
-          : _csignals_T_11
-              ? 5'h3
-              : _csignals_T_13
-                  ? 5'h4
-                  : _csignals_T_15
-                      ? 5'h5
-                      : _csignals_T_17
-                          ? 5'h3
-                          : _csignals_T_19
-                              ? 5'h4
-                              : _csignals_T_21
-                                  ? 5'h9
-                                  : _csignals_T_23
-                                      ? 5'hB
-                                      : _csignals_T_25
-                                          ? 5'hC
-                                          : _csignals_T_27
-                                              ? 5'h6
-                                              : _csignals_T_29
-                                                  ? 5'h7
-                                                  : _csignals_T_31
-                                                      ? 5'h8
-                                                      : _csignals_T_33
-                                                          ? 5'h1
-                                                          : _csignals_T_35 ? 5'hD : 5'h0;
-  wire        _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
-  wire        _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
-  wire [1:0]  csignals_1 =
-    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
-    | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
-    | _GEN_2 | ~_csignals_T_33
-      ? 2'h1
-      : 2'h2;
-  wire [2:0]  csignals_2 =
-    _csignals_T_1 | _csignals_T_3
-      ? 3'h2
-      : _csignals_T_5
-          ? 3'h1
-          : _csignals_T_7
-              ? 3'h2
-              : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
-                  ? 3'h1
-                  : _csignals_T_17 | _csignals_T_19
-                      ? 3'h2
-                      : _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
-  wire        _GEN_3 = _csignals_T_23 | _csignals_T_25;
-  wire        _GEN_4 =
-    _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-    | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
-  wire [1:0]  csignals_4 =
-    _csignals_T_1
-      ? 2'h1
-      : _csignals_T_3
-          ? 2'h0
-          : _GEN_4
-              ? 2'h1
-              : _GEN_3
-                  ? 2'h0
-                  : {1'h0,
-                     _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
-  wire [2:0]  csignals_5 =
-    _csignals_T_1
-      ? 3'h2
-      : _csignals_T_3
-          ? 3'h0
-          : _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
-  wire        _op1_data_T = csignals_1 == 2'h1;
-  wire        _op1_data_T_1 = csignals_1 == 2'h2;
-  wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
-  wire [31:0] op2_data =
-    csignals_2 == 3'h1
-      ? rt_data
-      : csignals_2 == 3'h2
-          ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
-          : csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
-  wire        _alu_out_T = csignals_0 == 5'h1;
-  wire [31:0] _alu_out_T_1 = op1_data + op2_data;
-  wire        _alu_out_T_3 = csignals_0 == 5'h2;
-  wire [31:0] _alu_out_T_4 = op1_data - op2_data;
-  wire        _alu_out_T_6 = csignals_0 == 5'h3;
-  wire [31:0] _alu_out_T_7 = op1_data & op2_data;
-  wire        _alu_out_T_8 = csignals_0 == 5'h4;
-  wire [31:0] _alu_out_T_9 = op1_data | op2_data;
-  wire        _alu_out_T_10 = csignals_0 == 5'h5;
-  wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
-  wire        _alu_out_T_12 = csignals_0 == 5'h6;
-  wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
-  wire        _alu_out_T_16 = csignals_0 == 5'h7;
-  wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
-  wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
-  wire        _alu_out_T_19 = csignals_0 == 5'h8;
-  wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
-  wire        _alu_out_T_24 = csignals_0 == 5'h9;
-  wire        _alu_out_T_28 = csignals_0 == 5'hD;
-  wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
-  wire [31:0] alu_out =
-    _alu_out_T
-      ? _alu_out_T_1
-      : _alu_out_T_3
-          ? _alu_out_T_4
-          : _alu_out_T_6
-              ? _alu_out_T_7
-              : _alu_out_T_8
-                  ? _alu_out_T_9
-                  : _alu_out_T_10
-                      ? _alu_out_T_11
-                      : _alu_out_T_12
-                          ? _alu_out_T_14[31:0]
-                          : _alu_out_T_16
-                              ? _alu_out_T_18
-                              : _alu_out_T_19
-                                  ? _alu_out_T_22
-                                  : _alu_out_T_24
-                                      ? _GEN_6
-                                      : _alu_out_T_28 ? op1_data : 32'h0;
-  wire        _br_flg_T_3 = op1_data == op2_data;
-  wire        br_flg =
-    csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
-  wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
-  wire [31:0] wb_data =
-    csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
-  wire [4:0]  wb_addr =
-    csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
-      ? io_imem_inst[15:11]
-      : io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
-  `ifndef SYNTHESIS
-    always @(posedge clock) begin
-      if ((`PRINTF_COND_) & ~reset) begin
-        $fwrite(32'h80000002, "---------------\n");
-        $fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
-        $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
-        $fwrite(32'h80000002, "pc_next: 0x%x\n",
-                br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
-        $fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
-        $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
-        $fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
-        $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
-        $fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
-        $fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
-        $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
-        $fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
-        $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
-        $fwrite(32'h80000002, "---------------\n");
-      end
-    end // always @(posedge)
-  `endif // not def SYNTHESIS
+  reg  [31:0] id_reg_pc;
+  reg  [31:0] id_reg_inst;
+  reg  [31:0] exe_reg_pc;
+  reg  [4:0]  exe_reg_wb_addr;
+  reg  [31:0] exe_reg_op1_data;
+  reg  [31:0] exe_reg_op2_data;
+  reg  [31:0] exe_reg_rt_data;
+  reg  [4:0]  exe_reg_exe_fun;
+  reg  [1:0]  exe_reg_mem_wen;
+  reg  [1:0]  exe_reg_rf_wen;
+  reg  [2:0]  exe_reg_wb_sel;
+  reg  [31:0] exe_reg_imm_i_sext;
+  reg  [31:0] mem_reg_pc;
+  reg  [4:0]  mem_reg_wb_addr;
+  reg  [31:0] mem_reg_rt_data;
+  reg  [1:0]  mem_reg_mem_wen;
+  reg  [1:0]  mem_reg_rf_wen;
+  reg  [2:0]  mem_reg_wb_sel;
+  reg  [31:0] mem_reg_alu_out;
+  reg  [4:0]  wb_reg_wb_addr;
+  reg  [1:0]  wb_reg_rf_wen;
+  reg  [31:0] wb_reg_wb_data;
+  reg  [31:0] if_reg_pc;
+  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
+  wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
+  wire        stall_flg =
+    _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
+    | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
+  wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
+  wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
+  wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
+  wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
+  wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
+  wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
+  wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
+  wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
+  wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
+  wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
+  wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
+  wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
+  wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+  wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
+  wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
+  wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
+  wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
+  wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
+  wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
+  wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
+  wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
+  wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
+  wire [31:0] exe_alu_out =
+    _exe_alu_out_T
+      ? _exe_alu_out_T_1
+      : _exe_alu_out_T_3
+          ? _exe_alu_out_T_4
+          : _exe_alu_out_T_6
+              ? _exe_alu_out_T_7
+              : _exe_alu_out_T_8
+                  ? _exe_alu_out_T_9
+                  : _exe_alu_out_T_10
+                      ? _exe_alu_out_T_11
+                      : _exe_alu_out_T_12
+                          ? _exe_alu_out_T_14[31:0]
+                          : _exe_alu_out_T_16
+                              ? _exe_alu_out_T_18
+                              : _exe_alu_out_T_19
+                                  ? _exe_alu_out_T_22
+                                  : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
+  assign exe_br_flg =
+    exe_reg_exe_fun == 5'hB
+      ? exe_reg_op1_data == exe_reg_op2_data
+      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
+  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+  wire [31:0] mem_wb_data =
+    mem_reg_wb_sel == 3'h2
+      ? io_dmem_rdata
+      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
   always @(posedge clock) begin
-    if (reset)
-      pc_reg <= 32'h0;
-    else if (br_flg)
-      pc_reg <= br_target;
-    else if (jmp_flg) begin
-      if (_alu_out_T)
-        pc_reg <= _alu_out_T_1;
-      else if (_alu_out_T_3)
-        pc_reg <= _alu_out_T_4;
-      else if (_alu_out_T_6)
-        pc_reg <= _alu_out_T_7;
-      else if (_alu_out_T_8)
-        pc_reg <= _alu_out_T_9;
-      else if (_alu_out_T_10)
-        pc_reg <= _alu_out_T_11;
-      else if (_alu_out_T_12)
-        pc_reg <= _alu_out_T_14[31:0];
-      else if (_alu_out_T_16)
-        pc_reg <= _alu_out_T_18;
-      else if (_alu_out_T_19)
-        pc_reg <= _alu_out_T_22;
-      else if (_alu_out_T_24)
-        pc_reg <= _GEN_6;
-      else if (_alu_out_T_28) begin
-        if (_op1_data_T)
-          pc_reg <= rs_data;
-        else if (~_op1_data_T_1)
-          pc_reg <= 32'h0;
-      end
-      else
-        pc_reg <= 32'h0;
+    if (reset) begin
+      id_reg_pc <= 32'h0;
+      id_reg_inst <= 32'h0;
+      exe_reg_pc <= 32'h0;
+      exe_reg_wb_addr <= 5'h0;
+      exe_reg_op1_data <= 32'h0;
+      exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <= 32'h0;
+      exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= 2'h0;
+      exe_reg_rf_wen <= 2'h0;
+      exe_reg_wb_sel <= 3'h0;
+      exe_reg_imm_i_sext <= 32'h0;
+      mem_reg_pc <= 32'h0;
+      mem_reg_wb_addr <= 5'h0;
+      mem_reg_rt_data <= 32'h0;
+      mem_reg_mem_wen <= 2'h0;
+      mem_reg_rf_wen <= 2'h0;
+      mem_reg_wb_sel <= 3'h0;
+      mem_reg_alu_out <= 32'h0;
+      wb_reg_wb_addr <= 5'h0;
+      wb_reg_rf_wen <= 2'h0;
+      wb_reg_wb_data <= 32'h0;
+      if_reg_pc <= 32'h0;
+    end
+    else begin
+      automatic logic        _id_rt_data_T_5;
+      automatic logic        _id_rt_data_T;
+      automatic logic        _id_rt_data_T_3;
+      automatic logic        _id_rt_data_T_6;
+      automatic logic        _id_rt_data_T_9;
+      automatic logic [31:0] id_imm_i_sext;
+      automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
+      automatic logic        _csignals_T_3;
+      automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
+      automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
+      automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
+      automatic logic        _csignals_T_9;
+      automatic logic        _csignals_T_11;
+      automatic logic        _csignals_T_13;
+      automatic logic        _csignals_T_15;
+      automatic logic        _csignals_T_17;
+      automatic logic        _csignals_T_19;
+      automatic logic        _csignals_T_21;
+      automatic logic        _csignals_T_23;
+      automatic logic        _csignals_T_25;
+      automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
+      automatic logic        _csignals_T_27;
+      automatic logic        _csignals_T_29;
+      automatic logic        _csignals_T_31;
+      automatic logic        _csignals_T_33;
+      automatic logic        _csignals_T_35;
+      automatic logic        _GEN_3;
+      automatic logic        _GEN_4;
+      automatic logic [1:0]  csignals_1;
+      automatic logic [2:0]  csignals_2;
+      automatic logic        _GEN_5;
+      automatic logic        _GEN_6;
+      _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
+      _id_rt_data_T = id_inst[20:16] == 5'h0;
+      _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
+      _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
+      _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
+      id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
+      _csignals_T_3 = id_inst[31:26] == 6'h2B;
+      _csignals_T_9 = _GEN_1 == 12'h22;
+      _csignals_T_11 = _GEN_1 == 12'h24;
+      _csignals_T_13 = _GEN_1 == 12'h25;
+      _csignals_T_15 = _GEN_1 == 12'h26;
+      _csignals_T_17 = id_inst[31:26] == 6'hC;
+      _csignals_T_19 = id_inst[31:26] == 6'hD;
+      _csignals_T_21 = _GEN_1 == 12'h2A;
+      _csignals_T_23 = id_inst[31:26] == 6'h4;
+      _csignals_T_25 = id_inst[31:26] == 6'h5;
+      _csignals_T_27 = _GEN_2 == 17'h0;
+      _csignals_T_29 = _GEN_2 == 17'h2;
+      _csignals_T_31 = _GEN_2 == 17'h3;
+      _csignals_T_33 = id_inst[31:26] == 6'h3;
+      _csignals_T_35 = _GEN_1 == 12'h8;
+      _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+      _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
+      csignals_1 =
+        _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+        | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
+        | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
+          ? 2'h1
+          : 2'h2;
+      csignals_2 =
+        _csignals_T_1 | _csignals_T_3
+          ? 3'h2
+          : _csignals_T_5
+              ? 3'h1
+              : _csignals_T_7
+                  ? 3'h2
+                  : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                      ? 3'h1
+                      : _csignals_T_17 | _csignals_T_19
+                          ? 3'h2
+                          : _GEN_4
+                              ? 3'h1
+                              : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+      _GEN_5 = _csignals_T_23 | _csignals_T_25;
+      _GEN_6 =
+        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+      if (~stall_flg)
+        id_reg_pc <= if_reg_pc;
+      if (_id_inst_T)
+        id_reg_inst <= 32'h20000000;
+      else if (~stall_flg)
+        id_reg_inst <= io_imem_inst;
+      exe_reg_pc <= id_reg_pc;
+      if ((_csignals_T_1
+             ? 3'h2
+             : _csignals_T_3
+                 ? 3'h0
+                 : _GEN_6
+                     ? 3'h1
+                     : _GEN_5
+                         ? 3'h0
+                         : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+          & id_inst[31:26] == 6'h0)
+        exe_reg_wb_addr <= id_inst[15:11];
+      else if (id_inst[31:26] == 6'h3)
+        exe_reg_wb_addr <= 5'h1F;
+      else
+        exe_reg_wb_addr <= id_inst[20:16];
+      if (csignals_1 == 2'h1) begin
+        if (id_inst[25:21] == 5'h0)
+          exe_reg_op1_data <= 32'h0;
+        else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+          if (_exe_alu_out_T)
+            exe_reg_op1_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op1_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op1_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op1_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op1_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op1_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op1_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op1_data <= _GEN_0;
+          else if (~_exe_alu_out_T_28)
+            exe_reg_op1_data <= 32'h0;
+        end
+        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
+          exe_reg_op1_data <= mem_wb_data;
+        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
+          exe_reg_op1_data <= wb_reg_wb_data;
+        else
+          exe_reg_op1_data <= _regfile_ext_R1_data;
+      end
+      else if (csignals_1 == 2'h2)
+        exe_reg_op1_data <= id_reg_pc;
+      else
+        exe_reg_op1_data <= 32'h0;
+      if (csignals_2 == 3'h1) begin
+        if (_id_rt_data_T)
+          exe_reg_op2_data <= 32'h0;
+        else if (_id_rt_data_T_3) begin
+          if (_exe_alu_out_T)
+            exe_reg_op2_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op2_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op2_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op2_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op2_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op2_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op2_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op2_data <= _GEN_0;
+          else
+            exe_reg_op2_data <= _exe_alu_out_T_29;
+        end
+        else if (_id_rt_data_T_6)
+          exe_reg_op2_data <= mem_wb_data;
+        else if (_id_rt_data_T_9)
+          exe_reg_op2_data <= wb_reg_wb_data;
+        else
+          exe_reg_op2_data <= _regfile_ext_R0_data;
+      end
+      else if (csignals_2 == 3'h2)
+        exe_reg_op2_data <= id_imm_i_sext;
+      else if (csignals_2 == 3'h4)
+        exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+      else
+        exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <=
+        _id_rt_data_T
+          ? 32'h0
+          : _id_rt_data_T_3
+              ? exe_alu_out
+              : _id_rt_data_T_6
+                  ? mem_wb_data
+                  : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+      if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_9)
+        exe_reg_exe_fun <= 5'h2;
+      else if (_csignals_T_11)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_13)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_15)
+        exe_reg_exe_fun <= 5'h5;
+      else if (_csignals_T_17)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_19)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_21)
+        exe_reg_exe_fun <= 5'h9;
+      else if (_csignals_T_23)
+        exe_reg_exe_fun <= 5'hB;
+      else if (_csignals_T_25)
+        exe_reg_exe_fun <= 5'hC;
+      else if (_csignals_T_27)
+        exe_reg_exe_fun <= 5'h6;
+      else if (_csignals_T_29)
+        exe_reg_exe_fun <= 5'h7;
+      else if (_csignals_T_31)
+        exe_reg_exe_fun <= 5'h8;
+      else if (_csignals_T_33)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_35)
+        exe_reg_exe_fun <= 5'hD;
+      else
+        exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+      if (_csignals_T_1) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h2;
+      end
+      else if (_csignals_T_3) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else if (_GEN_6) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h1;
+      end
+      else if (_GEN_5) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else begin
+        exe_reg_rf_wen <=
+          {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+        if (_GEN_3)
+          exe_reg_wb_sel <= 3'h1;
+        else if (_csignals_T_33)
+          exe_reg_wb_sel <= 3'h3;
+        else
+          exe_reg_wb_sel <= 3'h0;
+      end
+      exe_reg_imm_i_sext <= id_imm_i_sext;
+      mem_reg_pc <= exe_reg_pc;
+      mem_reg_wb_addr <= exe_reg_wb_addr;
+      mem_reg_rt_data <= exe_reg_rt_data;
+      mem_reg_mem_wen <= exe_reg_mem_wen;
+      mem_reg_rf_wen <= exe_reg_rf_wen;
+      mem_reg_wb_sel <= exe_reg_wb_sel;
+      mem_reg_alu_out <= exe_alu_out;
+      wb_reg_wb_addr <= mem_reg_wb_addr;
+      wb_reg_rf_wen <= mem_reg_rf_wen;
+      wb_reg_wb_data <= mem_wb_data;
+      if (exe_br_flg)
+        if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
+      else if (exe_jmp_flg)
+        if_reg_pc <= exe_alu_out;
+      else if (~stall_flg)
+        if_reg_pc <= if_reg_pc + 32'h4;
     end
-    else
-      pc_reg <= _pc_plus4_T;
   end // always @(posedge)
   regfile_32x32 regfile_ext (
-    .R0_addr (io_imem_inst[25:21]),
+    .R0_addr (id_inst[20:16]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
     .R0_data (_regfile_ext_R0_data),
-    .R1_addr (io_imem_inst[20:16]),
+    .R1_addr (id_inst[25:21]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
     .R1_data (_regfile_ext_R1_data),
-    .W0_addr (wb_addr),
-    .W0_en   (csignals_4 == 2'h1 & (|wb_addr)),
+    .W0_addr (wb_reg_wb_addr),
+    .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
     .W0_clk  (clock),
-    .W0_data (wb_data)
+    .W0_data (wb_reg_wb_data)
   );
-  assign io_imem_addr = pc_reg;
-  assign io_dmem_addr = alu_out;
-  assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
-  assign io_dmem_wdata = rt_data;
-  assign io_exit = io_imem_inst == 32'h114514;
+  assign io_imem_addr = if_reg_pc;
+  assign io_dmem_addr = mem_reg_alu_out;
+  assign io_dmem_wen = mem_reg_mem_wen[0];
+  assign io_dmem_wdata = mem_reg_rt_data;
+  assign io_exit = id_reg_inst == 32'h114514;
 endmodule
 
 // VCS coverage exclude_file
diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala
index b20ca87..b154be6 100755
--- a/src/main/scala/micore/Core.scala
+++ b/src/main/scala/micore/Core.scala
@@ -276,24 +276,24 @@ class Core extends Module {
   printf(p"id_rs_addr: 0x${Hexadecimal(id_rs_addr)}\n")
   printf(p"id_rt_addr: 0x${Hexadecimal(id_rt_addr)}\n")
   printf(p"id_rd_addr: 0x${Hexadecimal(id_rd_addr)}\n")
-  // printf(p"id_imm_i_sext: 0x${Hexadecimal(id_imm_i_sext)}\n")
-  // printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n")
-  // printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n")
-  // printf(p"id_rs_data_hazard: 0x${Hexadecimal(id_rs_data_hazard)}\n")
-  // printf(p"id_rt_data_hazard: 0x${Hexadecimal(id_rt_data_hazard)}\n")
+  printf(p"id_imm_i_sext: 0x${Hexadecimal(id_imm_i_sext)}\n")
+  printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n")
+  printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n")
+  printf(p"id_rs_data_hazard: 0x${Hexadecimal(id_rs_data_hazard)}\n")
+  printf(p"id_rt_data_hazard: 0x${Hexadecimal(id_rt_data_hazard)}\n")
   printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n")
   printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n")
   printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n")
   printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n")
   printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n")
-  // printf(p"exe_br_target: 0x${Hexadecimal(exe_br_target)}\n")
+  printf(p"exe_br_target: 0x${Hexadecimal(exe_br_target)}\n")
   printf(p"exe_reg_wb_addr: 0x${Hexadecimal(exe_reg_wb_addr)}\n")
   printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n")
   printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n")
   printf(p"wb_reg_wb_addr: 0x${Hexadecimal(wb_reg_wb_addr)}\n")
   printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n")
-  printf(p"regfile s0: 0x${(regfile(16.U))}\n")
-  printf(p"regfile s2: 0x${(regfile(18.U))}\n")
-  printf(p"regfile t0: 0x${(regfile(8.U))}\n")
+  printf(p"regfile s0: ${(regfile(16.U))}\n")
+  printf(p"regfile s2: ${(regfile(18.U))}\n")
+  printf(p"regfile t0: ${(regfile(8.U))}\n")
   printf(p"---------------\n")
 }
diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar
index 0003785efa764c80e760c2b918ca1ca6359df208..6794396f2173f673ddae48339a6a010e500336d5 100755
GIT binary patch
delta 33226
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diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip
index 2a881a4ae3ed3ebb37c27d92b26d299986735e5c..e37d9ee9e6263e1892922dd1e1ae943b409618d7 100755
GIT binary patch
delta 8130
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diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out
index 2a8d6f7..97ee044 100755
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
@@ -2,5 +2,43 @@
 [debug] IncrementalCompile.incrementalCompile
 [debug] previous = Stamps for: 24 products, 8 sources, 3 libraries
 [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/sicore/Top.scala, ${BASE}/src/main/scala/sicore/Memory.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/sicore/Core.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala)
-[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
-[debug] No changes
+[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set())
+[debug] 
+[debug] Initial source changes:
+[debug] 	removed: Set()
+[debug] 	added: Set()
+[debug] 	modified: Set(${BASE}/src/main/scala/micore/Core.scala)
+[debug] Invalidated products: Set()
+[debug] External API changes: API Changes: Set()
+[debug] Modified binary dependencies: Set()
+[debug] Initial directly invalidated classes: Set(micore.Core)
+[debug] Sources indirectly invalidated by:
+[debug] 	product: Set()
+[debug] 	binary dep: Set()
+[debug] 	external source: Set()
+[debug] All initially invalidated classes: Set(micore.Core)
+[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/micore/Core.scala)
+[debug] Initial set of included nodes: micore.Core
+[debug] compilation cycle 1
+[info] compiling 1 Scala source to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ...
+[debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar.
+[debug] [zinc] Running cached compiler 3fcbb45f for Scala compiler version 2.13.12
+[debug] [zinc] The Scala compiler is invoked with:
+[debug] 	-language:reflectiveCalls
+[debug] 	-deprecation
+[debug] 	-feature
+[debug] 	-Xcheckinit
+[debug] 	-Ymacro-annotations
+[debug] 	-Xplugin:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel-plugin_2.13.12/6.2.0/chisel-plugin_2.13.12-6.2.0.jar
+[debug] 	-bootclasspath
+[debug] 	/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar
+[debug] 	-classpath
+[debug] 	/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
+[debug] New invalidations:
+[debug] Initial set of included nodes: 
+[debug] Previously invalidated, but (transitively) depend on new invalidations:
+[debug] Final step, transitive dependencies:
+[debug] 	Set()
+[debug] No classes were invalidated.
+[debug] Scala compilation took 2.825691095 s
+[debug] done compiling
diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export
index 26fe379..671555b 100755
--- a/target/streams/compile/exportedProductJars/_global/streams/export
+++ b/target/streams/compile/exportedProductJars/_global/streams/export
@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out
index 9479f4e..8460bc7 100755
--- a/target/streams/compile/incOptions/_global/streams/out
+++ b/target/streams/compile/incOptions/_global/streams/out
@@ -1,2 +1,11 @@
 [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
+[debug] About to delete class files:
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
+[debug] We backup class files:
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
+[debug] Registering generated classes:
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
 [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs
index f25655c..4ae948c 100755
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@@ -1 +1 @@
-160837087
\ No newline at end of file
+-18168398
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out
index e08e3d0..873cb34 100755
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@@ -1,73 +1,57 @@
-[debug] Packaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
+[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
 [debug] Input file mappings:
-[debug] 	gcd
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd
-[debug] 	gcd/GcdInputBundle.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class
-[debug] 	gcd/GcdOutputBundle.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class
-[debug] 	gcd/DecoupledGcd.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class
-[debug] 	gcd/GCD.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class
-[debug] 	gcd/GCD$.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class
-[debug] 	gcd/GCD$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class
-[debug] 	gcd/GCD$delayedInit$body.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class
 [debug] 	common
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common
 [debug] 	common/Consts$.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class
 [debug] 	common/Consts.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class
 [debug] 	common/Instructions$.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class
 [debug] 	common/Instructions.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class
 [debug] 	micore
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore
-[debug] 	micore/Core.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore
 [debug] 	micore/Core$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
-[debug] 	micore/TopOrigin.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class
-[debug] 	micore/TopOrigin$.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class
-[debug] 	micore/TopOrigin$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class
-[debug] 	micore/TopOrigin$delayedInit$body.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class
-[debug] 	micore/ImemPortIo.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
+[debug] 	micore/Core.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class
 [debug] 	micore/DmemPortIo.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class
-[debug] 	micore/Memory.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class
+[debug] 	micore/ImemPortIo.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class
 [debug] 	micore/Memory$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
+[debug] 	micore/Memory.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class
+[debug] 	micore/TopOrigin$$anon$1.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class
+[debug] 	micore/TopOrigin$.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class
+[debug] 	micore/TopOrigin$delayedInit$body.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class
+[debug] 	micore/TopOrigin.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class
 [debug] 	sicore
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore
-[debug] 	sicore/TopOrigin.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin.class
-[debug] 	sicore/TopOrigin$.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$.class
-[debug] 	sicore/TopOrigin$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class
-[debug] 	sicore/TopOrigin$delayedInit$body.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class
-[debug] 	sicore/Core.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore
 [debug] 	sicore/Core$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class
-[debug] 	sicore/ImemPortIo.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/ImemPortIo.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class
+[debug] 	sicore/Core.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core.class
 [debug] 	sicore/DmemPortIo.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/DmemPortIo.class
-[debug] 	sicore/Memory.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/DmemPortIo.class
+[debug] 	sicore/ImemPortIo.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/ImemPortIo.class
 [debug] 	sicore/Memory$$anon$1.class
-[debug] 	  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class
+[debug] 	sicore/Memory.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory.class
+[debug] 	sicore/TopOrigin$$anon$1.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class
+[debug] 	sicore/TopOrigin$.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$.class
+[debug] 	sicore/TopOrigin$delayedInit$body.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class
+[debug] 	sicore/TopOrigin.class
+[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin.class
 [debug] Done packaging.
diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output
index 4e9041f..ccc866e 100755
--- a/target/streams/compile/packageBin/_global/streams/output
+++ b/target/streams/compile/packageBin/_global/streams/output
@@ -1 +1 @@
-1488086236
\ No newline at end of file
+-1359482768
\ No newline at end of file
diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
index ddc45ce..112ae53 100755
--- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
@@ -1 +1 @@
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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export
index 26fe379..671555b 100755
--- a/target/streams/runtime/exportedProductJars/_global/streams/export
+++ b/target/streams/runtime/exportedProductJars/_global/streams/export
@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export
index ddc45ce..112ae53 100755
--- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export
@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export
index 26fe379..671555b 100755
--- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export
+++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export
@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/test_run_dir/Micore_should_run_the_test_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_test_program/TopOrigin.lo.fir
new file mode 100755
index 0000000..69c7fd4
--- /dev/null
+++ b/test_run_dir/Micore_should_run_the_test_program/TopOrigin.lo.fir
@@ -0,0 +1,655 @@
+FIRRTL version 1.2.0
+circuit TopOrigin :
+  module Core : @[src/main/scala/micore/Core.scala 8:7]
+    input clock : Clock @[src/main/scala/micore/Core.scala 8:7]
+    input reset : UInt<1> @[src/main/scala/micore/Core.scala 8:7]
+    output io_imem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    input io_imem_inst : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_addr : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    input io_dmem_rdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_wen : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
+    output io_dmem_wdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
+    output io_exit : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
+
+    mem regfile : @[src/main/scala/micore/Core.scala 15:20]
+      data-type => UInt<32>
+      depth => 32
+      read-latency => 0
+      write-latency => 1
+      reader => id_rs_data_MPORT
+      reader => id_rt_data_MPORT
+      reader => MPORT_1
+      reader => MPORT_2
+      reader => MPORT_3
+      writer => MPORT
+      read-under-write => undefined
+    reg id_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 19:26]
+    reg id_reg_inst : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 20:28]
+    reg exe_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 23:27]
+    reg exe_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 24:32]
+    reg exe_reg_op1_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 25:33]
+    reg exe_reg_op2_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 26:33]
+    reg exe_reg_rt_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 27:32]
+    reg exe_reg_exe_fun : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 28:32]
+    reg exe_reg_mem_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 29:32]
+    reg exe_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 30:31]
+    reg exe_reg_wb_sel : UInt<3>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 31:31]
+    reg exe_reg_imm_i_sext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 32:35]
+    reg exe_reg_imm_j : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 33:30]
+    reg mem_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 36:27]
+    reg mem_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:32]
+    reg mem_reg_rt_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 38:32]
+    reg mem_reg_mem_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 39:32]
+    reg mem_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 40:31]
+    reg mem_reg_wb_sel : UInt<3>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 41:31]
+    reg mem_reg_alu_out : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 42:32]
+    reg wb_reg_wb_addr : UInt<5>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 45:31]
+    reg wb_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 46:30]
+    reg wb_reg_wb_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:31]
+    reg if_reg_pc : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 50:26]
+    node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 60:31]
+    node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 60:31]
+    node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 87:21]
+    node id_rs_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 82:33]
+    node _id_rs_data_hazard_T_1 = neq(id_rs_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 87:49]
+    node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 87:32]
+    node _id_rs_data_hazard_T_3 = eq(id_rs_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 87:75]
+    node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 87:58]
+    node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21]
+    node id_rt_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 83:33]
+    node _id_rt_data_hazard_T_1 = neq(id_rt_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:49]
+    node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32]
+    node _id_rt_data_hazard_T_3 = eq(id_rt_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:75]
+    node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:58]
+    node _stall_flg_T = or(id_rs_data_hazard, id_rt_data_hazard) @[src/main/scala/micore/Core.scala 90:35]
+    node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 54:23 90:13]
+    node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 231:34]
+    node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 231:15 57:25]
+    node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 198:24]
+    node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:58]
+    node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 198:58]
+    node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 199:24]
+    node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:58]
+    node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 199:58]
+    node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 200:24]
+    node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:58]
+    node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 201:24]
+    node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:57]
+    node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 202:24]
+    node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:58]
+    node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 203:24]
+    node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:77]
+    node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 203:58]
+    node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 206:9]
+    node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 207:24]
+    node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 207:77]
+    node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 207:58]
+    node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 211:24]
+    node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 211:58]
+    node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 211:84]
+    node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 211:65]
+    node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 214:10]
+    node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 215:24]
+    node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 215:58]
+    node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:84]
+    node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 215:65]
+    node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 216:24]
+    node _exe_alu_out_T_29 = mux(_exe_alu_out_T_28, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_30 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_31 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_32 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_33 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_34 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_35 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 195:15 58:25]
+    node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 223:24]
+    node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:57]
+    node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 224:24]
+    node _exe_br_flg_T_3 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 224:57]
+    node _exe_br_flg_T_4 = mux(_exe_br_flg_T_2, _exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_br_flg_T_5 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 220:14 55:24]
+    node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 228:53]
+    node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 228:31]
+    node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 228:31]
+    node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 228:17 56:27]
+    node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 72:19]
+    node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 76:19]
+    node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 93:21]
+    node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 93:36]
+    node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 93:8]
+    node id_rs_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 95:27]
+    node id_rt_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 96:27]
+    node id_rd_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 97:27]
+    node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 103:19]
+    node _id_rs_data_T_1 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20]
+    node _id_rs_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60]
+    node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 104:41]
+    node _id_rs_data_T_4 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 105:20]
+    node _id_rs_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 105:60]
+    node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 105:41]
+    node _id_rs_data_T_7 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:21]
+    node _id_rs_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:59]
+    node _id_rs_data_T_9 = and(_id_rs_data_T_7, _id_rs_data_T_8) @[src/main/scala/micore/Core.scala 107:41]
+    node _id_rs_data_T_10 = mux(_id_rs_data_T_9, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 250:23]
+    node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 251:23]
+    node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 251:49]
+    node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 251:49]
+    node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 247:15 99:25]
+    node _id_rs_data_T_11 = mux(_id_rs_data_T_6, mem_wb_data, _id_rs_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rs_data_T_12 = mux(_id_rs_data_T_3, exe_alu_out, _id_rs_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:19]
+    node _id_rt_data_T_1 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 115:20]
+    node _id_rt_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 115:60]
+    node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 115:41]
+    node _id_rt_data_T_4 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 116:20]
+    node _id_rt_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 116:60]
+    node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 116:41]
+    node _id_rt_data_T_7 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21]
+    node _id_rt_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59]
+    node _id_rt_data_T_9 = and(_id_rt_data_T_7, _id_rt_data_T_8) @[src/main/scala/micore/Core.scala 118:41]
+    node _id_rt_data_T_10 = mux(_id_rt_data_T_9, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rt_data_T_11 = mux(_id_rt_data_T_6, mem_wb_data, _id_rt_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rt_data_T_12 = mux(_id_rt_data_T_3, exe_alu_out, _id_rt_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 123:25]
+    node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 124:44]
+    node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 124:31]
+    node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 124:26]
+    node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 125:29]
+    node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 125:42]
+    node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 125:21]
+    node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_3 = eq(UInt<32>("hac000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_4 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_6 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_7 = eq(UInt<30>("h20000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_8 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_10 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_12 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_14 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_16 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_17 = eq(UInt<30>("h30000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_18 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_19 = eq(UInt<30>("h34000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_20 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_22 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_23 = eq(UInt<29>("h10000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_24 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_25 = eq(UInt<29>("h14000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_26 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_28 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_32 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_34 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_38 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_39 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_40 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_41 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_42 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_43 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_44 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_45 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_46 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_47 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_48 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_49 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_50 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_56 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_57 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_58 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_59 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_60 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_61 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_62 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_63 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_64 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_65 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_66 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_67 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_71 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_72 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_73 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_74 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_75 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_76 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_77 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_78 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_79 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_80 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_81 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_82 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_83 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_84 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_90 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_91 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_92 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_93 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_94 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_95 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_96 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_97 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_98 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_99 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_100 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_101 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_102 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_103 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_104 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_105 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_106 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_107 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_108 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_109 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_110 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_111 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_112 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_113 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_114 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_115 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_116 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_117 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_118 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_119 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_120 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_121 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_122 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_123 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_124 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_125 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_126 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_127 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_128 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_129 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_130 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_131 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_132 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_133 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_134 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_135 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 158:19]
+    node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 159:19]
+    node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_op1_data = mux(_id_op1_data_T, id_rs_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 166:19]
+    node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 167:19]
+    node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 168:19]
+    node _id_op2_data_T_3 = mux(_id_op2_data_T_2, id_imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T_4 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_op2_data = mux(_id_op2_data_T, id_rt_data, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 180:18]
+    node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 180:39]
+    node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 183:9]
+    node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 180:29]
+    node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 184:16]
+    node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 184:16]
+    node _exe_reg_wb_addr_T_6 = mux(_exe_reg_wb_addr_T_5, UInt<5>("h1f"), id_rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_reg_wb_addr_T_7 = mux(_exe_reg_wb_addr_T_3, id_rd_addr, _exe_reg_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 261:22]
+    node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:50]
+    node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 261:32]
+    node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 261:59 262:12]
+    node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 261:59 262:12]
+    node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:59 262:12 15:20]
+    node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 261:59 262:29]
+    node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 261:59 262:29]
+    node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 265:27]
+    node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9]
+    node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9]
+    node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 269:9]
+    node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 269:9]
+    node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 270:9]
+    node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 270:9]
+    node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 271:9]
+    node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 271:9]
+    node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 272:9]
+    node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 272:9]
+    node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 273:9]
+    node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 273:9]
+    node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 274:9]
+    node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 274:9]
+    node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9]
+    node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9]
+    node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9]
+    node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9]
+    node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9]
+    node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9]
+    node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9]
+    node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9]
+    node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9]
+    node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9]
+    node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9]
+    node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9]
+    node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9]
+    node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9]
+    node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9]
+    node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9]
+    node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9]
+    node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9]
+    node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9]
+    node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9]
+    node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9]
+    node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9]
+    node _T_39 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9]
+    node _T_40 = eq(_T_39, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9]
+    node _T_41 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9]
+    node _T_42 = eq(_T_41, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9]
+    node _T_43 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9]
+    node _T_44 = eq(_T_43, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
+    node _T_45 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9]
+    node _T_46 = eq(_T_45, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9]
+    node _T_47 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
+    node _T_48 = eq(_T_47, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
+    node _T_49 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9]
+    node _T_50 = eq(_T_49, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9]
+    node _T_51 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9]
+    node _T_52 = eq(_T_51, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9]
+    node _T_53 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9]
+    node _T_54 = eq(_T_53, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9]
+    node _T_55 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9]
+    node _T_56 = eq(_T_55, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9]
+    node _T_57 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9]
+    node _T_58 = eq(_T_57, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9]
+    node _T_59 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9]
+    node _T_60 = eq(_T_59, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9]
+    node _T_61 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9]
+    node _T_62 = eq(_T_61, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9]
+    node _T_63 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9]
+    node _T_64 = eq(_T_63, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9]
+    io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 51:16]
+    io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 243:16]
+    io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 244:15]
+    io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 245:17]
+    io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 265:11]
+    regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 101:12]
+    regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 101:12]
+    regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 101:12]
+    regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 112:12]
+    regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 112:12]
+    regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 112:12]
+    regfile.MPORT_1.addr <= UInt<5>("h10") @[src/main/scala/micore/Core.scala 295:34]
+    regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 295:34]
+    regfile.MPORT_1.clk <= clock @[src/main/scala/micore/Core.scala 295:34]
+    regfile.MPORT_2.addr <= UInt<5>("h12") @[src/main/scala/micore/Core.scala 296:34]
+    regfile.MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 296:34]
+    regfile.MPORT_2.clk <= clock @[src/main/scala/micore/Core.scala 296:34]
+    regfile.MPORT_3.addr <= UInt<5>("h8") @[src/main/scala/micore/Core.scala 297:34]
+    regfile.MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 297:34]
+    regfile.MPORT_3.clk <= clock @[src/main/scala/micore/Core.scala 297:34]
+    regfile.MPORT.addr <= _GEN_0
+    regfile.MPORT.en <= _GEN_2
+    regfile.MPORT.clk <= _GEN_1
+    regfile.MPORT.data <= _GEN_4
+    regfile.MPORT.mask <= _GEN_3
+    id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 72:13]
+    id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 73:15]
+    exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 173:14 23:{27,27}]
+    exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 177:19 24:{32,32}]
+    exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 174:20 25:{33,33}]
+    exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 175:20 26:{33,33}]
+    exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 176:19 27:{32,32}]
+    exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 192:19 28:{32,32}]
+    exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 188:19 29:{32,32}]
+    exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 189:18 30:{31,31}]
+    exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 187:18 31:{31,31}]
+    exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 190:22 32:{35,35}]
+    exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 191:17 33:{30,30}]
+    mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 234:14 36:{27,27}]
+    mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 236:19 37:{32,32}]
+    mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 235:19 38:{32,32}]
+    mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 240:19 39:{32,32}]
+    mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 238:18 40:{31,31}]
+    mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 239:18 41:{31,31}]
+    mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 237:19 42:{32,32}]
+    wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 258:18 45:{31,31}]
+    wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 257:17 46:{30,30}]
+    wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 256:18 47:{31,31}]
+    if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 50:{26,26} 69:13]
+    printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 268:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/micore/Core.scala 269:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 270:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_3 @[src/main/scala/micore/Core.scala 271:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_4 @[src/main/scala/micore/Core.scala 272:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_5 @[src/main/scala/micore/Core.scala 273:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs_data: 0x%x\n", id_rs_data) : printf_6 @[src/main/scala/micore/Core.scala 274:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_rt_data: 0x%x\n", id_rt_data) : printf_7 @[src/main/scala/micore/Core.scala 275:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_rs_addr: 0x%x\n", id_rs_addr) : printf_8 @[src/main/scala/micore/Core.scala 276:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_rt_addr: 0x%x\n", id_rt_addr) : printf_9 @[src/main/scala/micore/Core.scala 277:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "id_rd_addr: 0x%x\n", id_rd_addr) : printf_10 @[src/main/scala/micore/Core.scala 278:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "id_imm_i_sext: 0x%x\n", id_imm_i_sext) : printf_11 @[src/main/scala/micore/Core.scala 279:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_br_flg: 0x%x\n", exe_br_flg) : printf_12 @[src/main/scala/micore/Core.scala 280:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_jmp_flg: 0x%x\n", exe_jmp_flg) : printf_13 @[src/main/scala/micore/Core.scala 281:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "id_rs_data_hazard: 0x%x\n", id_rs_data_hazard) : printf_14 @[src/main/scala/micore/Core.scala 282:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "id_rt_data_hazard: 0x%x\n", id_rt_data_hazard) : printf_15 @[src/main/scala/micore/Core.scala 283:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "stall_flg: 0x%x\n", stall_flg) : printf_16 @[src/main/scala/micore/Core.scala 284:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_17 @[src/main/scala/micore/Core.scala 285:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_40), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", exe_reg_op1_data) : printf_18 @[src/main/scala/micore/Core.scala 286:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_42), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", exe_reg_op2_data) : printf_19 @[src/main/scala/micore/Core.scala 287:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_44), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_20 @[src/main/scala/micore/Core.scala 288:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_46), UInt<1>("h1")), "exe_br_target: 0x%x\n", exe_br_target) : printf_21 @[src/main/scala/micore/Core.scala 289:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_48), UInt<1>("h1")), "exe_reg_wb_addr: 0x%x\n", exe_reg_wb_addr) : printf_22 @[src/main/scala/micore/Core.scala 290:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_50), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_23 @[src/main/scala/micore/Core.scala 291:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_52), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_24 @[src/main/scala/micore/Core.scala 292:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_54), UInt<1>("h1")), "wb_reg_wb_addr: 0x%x\n", wb_reg_wb_addr) : printf_25 @[src/main/scala/micore/Core.scala 293:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_56), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_26 @[src/main/scala/micore/Core.scala 294:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_58), UInt<1>("h1")), "regfile s0: %d\n", regfile.MPORT_1.data) : printf_27 @[src/main/scala/micore/Core.scala 295:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_60), UInt<1>("h1")), "regfile s2: %d\n", regfile.MPORT_2.data) : printf_28 @[src/main/scala/micore/Core.scala 296:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_62), UInt<1>("h1")), "regfile t0: %d\n", regfile.MPORT_3.data) : printf_29 @[src/main/scala/micore/Core.scala 297:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_64), UInt<1>("h1")), "---------------\n") : printf_30 @[src/main/scala/micore/Core.scala 298:9]
+
+  module Memory : @[src/main/scala/micore/Memory.scala 20:7]
+    input clock : Clock @[src/main/scala/micore/Memory.scala 20:7]
+    input reset : UInt<1> @[src/main/scala/micore/Memory.scala 20:7]
+    input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 21:14]
+    input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+
+    mem mem : @[src/main/scala/micore/Memory.scala 26:16]
+      data-type => UInt<8>
+      depth => 4096
+      read-latency => 0
+      write-latency => 1
+      reader => io_imem_inst_MPORT
+      reader => io_imem_inst_MPORT_1
+      reader => io_imem_inst_MPORT_2
+      reader => io_imem_inst_MPORT_3
+      reader => io_dmem_rdata_MPORT
+      reader => io_dmem_rdata_MPORT_1
+      reader => io_dmem_rdata_MPORT_2
+      reader => io_dmem_rdata_MPORT_3
+      writer => MPORT
+      writer => MPORT_1
+      writer => MPORT_2
+      writer => MPORT_3
+      read-under-write => undefined
+    node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 31:22]
+    node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 31:22]
+    node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 31:8]
+    node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 32:22]
+    node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 32:22]
+    node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 32:8]
+    node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 33:22]
+    node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 33:22]
+    node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 33:8]
+    node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 34:8]
+    node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 30:22]
+    node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 30:22]
+    node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 30:22]
+    node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 38:22]
+    node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 38:22]
+    node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 38:8]
+    node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 39:22]
+    node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 39:22]
+    node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 39:8]
+    node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 40:22]
+    node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 40:22]
+    node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 40:8]
+    node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 41:8]
+    node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 37:23]
+    node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 37:23]
+    node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 37:23]
+    node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 45:8]
+    node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 45:39]
+    node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 46:22]
+    node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 46:22]
+    node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 46:8]
+    node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 46:57]
+    node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 47:22]
+    node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 47:22]
+    node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 47:8]
+    node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 47:57]
+    node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 48:22]
+    node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 48:22]
+    node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 48:8]
+    node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 48:57]
+    node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 44:21 45:8]
+    node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 44:21 45:8]
+    node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 26:16 44:21 45:8]
+    node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 44:21 45:23]
+    node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 44:21 45:23]
+    node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 44:21 46:8]
+    node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 44:21 46:41]
+    node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 44:21 47:8]
+    node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 44:21 47:41]
+    node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 44:21 48:8]
+    node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 44:21 48:41]
+    io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 30:16]
+    io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 37:17]
+    mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 31:8]
+    mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 31:8]
+    mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 31:8]
+    mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 32:8]
+    mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 32:8]
+    mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 32:8]
+    mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 33:8]
+    mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 33:8]
+    mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 33:8]
+    mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 34:8]
+    mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 34:8]
+    mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 34:8]
+    mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 38:8]
+    mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 38:8]
+    mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 38:8]
+    mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 41:8]
+    mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8]
+    mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 41:8]
+    mem.MPORT.addr <= _GEN_0
+    mem.MPORT.en <= _GEN_2
+    mem.MPORT.clk <= _GEN_1
+    mem.MPORT.data <= _GEN_4
+    mem.MPORT.mask <= _GEN_3
+    mem.MPORT_1.addr <= _GEN_5
+    mem.MPORT_1.en <= _GEN_2
+    mem.MPORT_1.clk <= _GEN_1
+    mem.MPORT_1.data <= _GEN_6
+    mem.MPORT_1.mask <= _GEN_3
+    mem.MPORT_2.addr <= _GEN_7
+    mem.MPORT_2.en <= _GEN_2
+    mem.MPORT_2.clk <= _GEN_1
+    mem.MPORT_2.data <= _GEN_8
+    mem.MPORT_2.mask <= _GEN_3
+    mem.MPORT_3.addr <= _GEN_9
+    mem.MPORT_3.en <= _GEN_2
+    mem.MPORT_3.clk <= _GEN_1
+    mem.MPORT_3.data <= _GEN_10
+    mem.MPORT_3.mask <= _GEN_3
+
+  module TopOrigin : @[src/main/scala/micore/Top.scala 8:7]
+    input clock : Clock @[src/main/scala/micore/Top.scala 8:7]
+    input reset : UInt<1> @[src/main/scala/micore/Top.scala 8:7]
+    output io_exit : UInt<1> @[src/main/scala/micore/Top.scala 9:14]
+
+    inst core of Core @[src/main/scala/micore/Top.scala 12:20]
+    inst memory of Memory @[src/main/scala/micore/Top.scala 13:22]
+    io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 16:11]
+    core.clock <= clock
+    core.reset <= reset
+    core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 14:16]
+    core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/micore/Top.scala 15:16]
+    memory.clock <= clock
+    memory.reset <= reset
+    memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/micore/Top.scala 14:16]
+    memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/micore/Top.scala 15:16]
+    memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/micore/Top.scala 15:16]
+    memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/micore/Top.scala 15:16]
diff --git a/testbench.sv b/testbench.sv
index 138f3af..d50f81d 100755
--- a/testbench.sv
+++ b/testbench.sv
@@ -1,85 +1,116 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
+// Company:
+// Engineer:
+//
 // Create Date: 2024/12/28 11:36:13
-// Design Name: 
+// Design Name:
 // Module Name: testbench
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
-// 
+//
 //////////////////////////////////////////////////////////////////////////////////
 
 
+module tb_Top();
 
-module Top_tb;
-
-    // 输入信号
     reg clock;
     reg reset;
 
-    // 输出信号
     wire io_exit;
     wire [3:0] io_anodes;
     wire [6:0] io_segments;
 
-    // 内部信号（用于监视）
-    wire [31:0] pc;          // 程序计数器
-    wire [31:0] instruction; // 当前指令
-
-    // 实例化 Top 模块
     Top uut (
-        .clock      (clock),
-        .reset      (reset),
-        .io_exit    (io_exit),
-        .io_anodes  (io_anodes),
-        .io_segments(io_segments)
-    );
+            .clock(clock),
+            .reset(reset),
+            .io_exit(io_exit),
+            .io_anodes(io_anodes),
+            .io_segments(io_segments)
+        );
 
-    // 连接到 Core 模块的内部信号
-    assign pc = uut.core.if_reg_pc; // 假设 if_reg_pc 是 Core 模块中的 pc 寄存器
-    assign instruction = uut.core.id_reg_inst; // 假设 id_reg_inst 是 Core 模块中的当前指令
-
-    // 时钟生成
     initial begin
         clock = 0;
-        forever #5 clock = ~clock; // 10ns 周期时钟
+        forever
+            #5 clock = ~clock; // 10ns周期，50MHz时钟
     end
 
-    // 测试逻辑
     initial begin
-        // 初始化信号
         reset = 1;
-        #20; // 等待 20ns
-
-        // 释放复位信号
+        #20;
         reset = 0;
-        #200; // 等待 200ns
 
-        // 观察 io_exit 信号
-        if (io_exit) begin
-            $display("Test Passed: io_exit is high.");
-        end else begin
-            $display("Test Failed: io_exit is low.");
-        end
+        #1000;
 
-        // 结束仿真
+        $display("Simulation finished.");
         $finish;
     end
 
-    // 监视信号变化
+    always @(posedge clock) begin
+        if (!reset) begin
+            // 打印当前PC值和指令
+            if (uut.core.io_imem_inst !== 32'hx) begin
+                $display("Time: %0t | PC: %h | Instruction: %h", $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
+            end
+
+            // 打印ALU输入操作数和计算结果
+            if (uut.core.exe_alu_out !== 32'hx) begin
+                $display("Time: %0t | ALU Op1: %h | ALU Op2: %h | ALU Result: %h | ALU Fun: %h",
+                         $time, uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data,
+                         uut.core.exe_alu_out, uut.core.exe_reg_exe_fun);
+            end
+
+            // 打印寄存器文件读写操作
+            if (uut.core.regfile_ext.W0_en && uut.core.regfile_ext.W0_addr !== 5'hx) begin
+                $display("Time: %0t | RegFile Write | Addr: %h | Data: %h",
+                         $time, uut.core.regfile_ext.W0_addr, uut.core.regfile_ext.W0_data);
+            end
+            if (uut.core.regfile_ext.R0_en && uut.core.regfile_ext.R0_addr !== 5'hx) begin
+                $display("Time: %0t | RegFile Read R0 | Addr: %h | Data: %h",
+                         $time, uut.core.regfile_ext.R0_addr, uut.core.regfile_ext.R0_data);
+            end
+            if (uut.core.regfile_ext.R1_en && uut.core.regfile_ext.R1_addr !== 5'hx) begin
+                $display("Time: %0t | RegFile Read R1 | Addr: %h | Data: %h",
+                         $time, uut.core.regfile_ext.R1_addr, uut.core.regfile_ext.R1_data);
+            end
+
+            // 打印内存读写操作
+            if (uut.memory.io_dmem_wen) begin
+                $display("Time: %0t | Memory Write | Addr: %h | Data: %h",
+                         $time, uut.memory.io_dmem_addr, uut.memory.io_dmem_wdata);
+            end
+            if (uut.memory.io_dmem_rdata !== 32'hx) begin
+                $display("Time: %0t | Memory Read | Addr: %h | Data: %h",
+                         $time, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
+            end
+
+            // 打印流水线各阶段的状态
+            $display("Time: %0t | IF Stage | PC: %h | Instruction: %h",
+                     $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
+            $display("Time: %0t | ID Stage | PC: %h | Instruction: %h | Op1: %h | Op2: %h",
+                     $time, uut.core.id_reg_pc, uut.core.id_reg_inst,
+                     uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data);
+            $display("Time: %0t | EXE Stage | PC: %h | ALU Result: %h",
+                     $time, uut.core.exe_reg_pc, uut.core.exe_alu_out);
+            $display("Time: %0t | MEM Stage | PC: %h | Mem Addr: %h | Mem Data: %h",
+                     $time, uut.core.mem_reg_pc, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
+            $display("Time: %0t | WB Stage | PC: %h | WB Addr: %h | WB Data: %h",
+                     $time, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_data);
+        end
+    end
+
     initial begin
-        $monitor("Time: %0t | Reset: %b | PC: %h | Instruction: %h | io_exit: %b",
-                 $time, reset, pc, instruction, io_exit);
+        $dumpfile("waveform.vcd");
+        $dumpvars(0, tb_Top); // 记录所有信号
     end
 
 endmodule
+