From 7d9846b4a6c69a03e02b707dd4fb617791f918c6 Mon Sep 17 00:00:00 2001
From: CGH0S7 <776459475@qq.com>
Date: Fri, 27 Dec 2024 23:35:23 +0800
Subject: [PATCH] Chisel code optimized

---
 .gitignore                                    |   1 +
 Top.sv                                        | 625 ++++++++----------
 .../streams/update_cache_2.12/output_dsp      |   2 +-
 .../_global/update/_global/streams/out        |  11 +-
 .../_global/_global/compileOutputs/previous   |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../compile/incOptions/_global/streams/out    |   6 +-
 .../_global/streams/export                    |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../fullClasspath/_global/streams/export      |   2 +-
 .../_global/streams/export                    |   2 +-
 .../streams/update_cache_2.12/output_dsp      |   2 +-
 .../updateClassifiers/_global/streams/out     |   9 +-
 .../_global/_global/compileOutputs/previous   |   2 +-
 .../compile/bloopGenerate/_global/streams/out |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../compile/incOptions/_global/streams/out    |   6 +-
 .../_global/streams/export                    |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../fullClasspath/_global/streams/export      |   2 +-
 .../_global/streams/export                    |   2 +-
 .../streams/update_cache_2.12/output_dsp      |   2 +-
 .../_global/_global/compileOutputs/previous   |   2 +-
 .../compile/bloopGenerate/_global/streams/out |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../compile/incOptions/_global/streams/out    |   6 +-
 .../_global/streams/export                    |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../fullClasspath/_global/streams/export      |   2 +-
 .../_global/streams/export                    |   2 +-
 src/main/scala/micore/Core.scala              | 373 +++++------
 src/main/scala/micore/Memory.scala            |  22 +-
 src/main/scala/micore/Top.scala               |   7 +-
 target/scala-2.13/-name-_2.13-0.1.0.jar       | Bin 57006 -> 66137 bytes
 target/scala-2.13/zinc/inc_compile_2.13.zip   | Bin 14938 -> 14428 bytes
 .../_global/_global/compileOutputs/previous   |   2 +-
 .../compile/bloopGenerate/_global/streams/out |   2 +-
 .../compileIncremental/_global/streams/out    |  29 +-
 .../_global/streams/export                    |   2 +-
 .../exportedProducts/_global/streams/export   |   2 +-
 .../compile/incOptions/_global/streams/out    |  48 +-
 .../compile/packageBin/_global/streams/inputs |   2 +-
 .../compile/packageBin/_global/streams/out    |  54 +-
 .../compile/packageBin/_global/streams/output |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../_global/streams/export                    |   2 +-
 .../test/bloopGenerate/_global/streams/out    |   2 +-
 49 files changed, 603 insertions(+), 662 deletions(-)
 mode change 100755 => 100644 target/scala-2.13/-name-_2.13-0.1.0.jar
 mode change 100755 => 100644 target/scala-2.13/zinc/inc_compile_2.13.zip

diff --git a/.gitignore b/.gitignore
index 0025be6..1b6a23e 100755
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@
 .scalafmt.conf
 *.code-workspace
 target
+.vscode
 
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*
diff --git a/Top.sv b/Top.sv
index 675e6ae..e25dbb8 100755
--- a/Top.sv
+++ b/Top.sv
@@ -16,12 +16,24 @@ module regfile_32x32(
 );
 
   reg [31:0] Memory[0:31];
+  reg        _R0_en_d0;
+  reg [4:0]  _R0_addr_d0;
+  always @(posedge R0_clk) begin
+    _R0_en_d0 <= R0_en;
+    _R0_addr_d0 <= R0_addr;
+  end // always @(posedge)
+  reg        _R1_en_d0;
+  reg [4:0]  _R1_addr_d0;
+  always @(posedge R1_clk) begin
+    _R1_en_d0 <= R1_en;
+    _R1_addr_d0 <= R1_addr;
+  end // always @(posedge)
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr] <= W0_data;
   end // always @(posedge)
-  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
-  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+  assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
+  assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
 endmodule
 
 module Core(
@@ -36,8 +48,6 @@ module Core(
   output        io_exit
 );
 
-  wire        exe_jmp_flg;
-  wire        exe_br_flg;
   wire [31:0] _regfile_ext_R0_data;
   wire [31:0] _regfile_ext_R1_data;
   reg  [31:0] id_reg_pc;
@@ -54,269 +64,249 @@ module Core(
   reg  [31:0] exe_reg_imm_b_sext;
   reg  [31:0] mem_reg_pc;
   reg  [4:0]  mem_reg_wb_addr;
+  reg  [31:0] mem_reg_alu_out;
   reg  [31:0] mem_reg_rs2_data;
-  reg  [1:0]  mem_reg_mem_wen;
   reg  [1:0]  mem_reg_rf_wen;
   reg  [2:0]  mem_reg_wb_sel;
-  reg  [31:0] mem_reg_alu_out;
+  reg  [1:0]  mem_reg_mem_wen;
   reg  [4:0]  wb_reg_wb_addr;
   reg  [1:0]  wb_reg_rf_wen;
   reg  [31:0] wb_reg_wb_data;
   reg  [31:0] if_reg_pc;
-  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
-  wire        _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
-  wire        stall_flg =
-    _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
-    & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
-    & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
-  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
   wire        _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
-  assign exe_br_flg =
-    exe_reg_exe_fun == 5'hB
-      ? exe_reg_op1_data == exe_reg_op2_data
-      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
-  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
-  wire [31:0] mem_wb_data =
-    mem_reg_wb_sel == 3'h2
-      ? io_dmem_rdata
-      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
+  wire        exe_br_flg =
+    exe_reg_exe_fun == 5'hC
+      ? exe_reg_op1_data != exe_reg_op2_data
+      : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
+  wire        exe_jmp_flg = exe_reg_wb_sel == 3'h3;
   always @(posedge clock) begin
-    if (reset) begin
-      id_reg_pc <= 32'h0;
+    automatic logic        _id_inst_T = exe_br_flg | exe_jmp_flg;
+    automatic logic        _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
+    automatic logic        stall_flg;
+    automatic logic [31:0] id_inst;
+    automatic logic        _id_rs2_data_T_2;
+    automatic logic        _id_rs2_data_T;
+    automatic logic [31:0] _id_rs2_data_T_8;
+    automatic logic [16:0] _GEN;
+    automatic logic        _csignals_T_5;
+    automatic logic [19:0] _GEN_0;
+    automatic logic        _csignals_T_7;
+    automatic logic        _csignals_T_9;
+    automatic logic        _csignals_T_11;
+    automatic logic        _csignals_T_13;
+    automatic logic        _csignals_T_15;
+    automatic logic        _csignals_T_17;
+    automatic logic        _csignals_T_19;
+    automatic logic [16:0] _GEN_1;
+    automatic logic        _csignals_T_21;
+    automatic logic        _csignals_T_23;
+    automatic logic        _csignals_T_25;
+    automatic logic        _csignals_T_27;
+    automatic logic        _csignals_T_29;
+    automatic logic        _csignals_T_31;
+    automatic logic        _csignals_T_33;
+    automatic logic        _csignals_T_35;
+    automatic logic        _csignals_T_37;
+    automatic logic        _GEN_2;
+    automatic logic        _GEN_3;
+    automatic logic [1:0]  csignals_1;
+    automatic logic [2:0]  _csignals_T_90;
+    automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
+    automatic logic [62:0] _exe_alu_out_T_8 =
+      {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+    automatic logic [31:0] exe_alu_out;
+    stall_flg =
+      _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
+      & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
+      & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+    id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
+    _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
+    _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
+    _id_rs2_data_T_8 =
+      id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
+        ? mem_reg_alu_out
+        : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
+            ? wb_reg_wb_data
+            : _regfile_ext_R0_data;
+    _GEN = {id_inst[31:26], id_inst[10:0]};
+    _csignals_T_5 = _GEN == 17'h20;
+    _GEN_0 = {id_inst[31:28], id_inst[15:0]};
+    _csignals_T_7 = _GEN_0 == 20'h80000;
+    _csignals_T_9 = _GEN == 17'h22;
+    _csignals_T_11 = _GEN == 17'h24;
+    _csignals_T_13 = _GEN == 17'h25;
+    _csignals_T_15 = _GEN == 17'h26;
+    _csignals_T_17 = _GEN_0 == 20'hC0000;
+    _csignals_T_19 = _GEN_0 == 20'hD0000;
+    _GEN_1 = {id_inst[30:20], id_inst[5:0]};
+    _csignals_T_21 = _GEN_1 == 17'h0;
+    _csignals_T_23 = _GEN_1 == 17'h2;
+    _csignals_T_25 = _GEN_1 == 17'h3;
+    _csignals_T_27 = _GEN == 17'h2A;
+    _csignals_T_29 = _GEN_0 == 20'h40000;
+    _csignals_T_31 = _GEN_0 == 20'h50000;
+    _csignals_T_33 = id_inst == 32'hC000000;
+    _csignals_T_35 = _GEN_0 == 20'h8;
+    _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
+    _GEN_2 = _csignals_T_29 | _csignals_T_31;
+    _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
+    csignals_1 =
+      _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+      | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
+        ? 2'h0
+        : _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
+    _csignals_T_90 =
+      _csignals_T_5
+        ? 3'h1
+        : _csignals_T_7
+            ? 3'h2
+            : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                ? 3'h1
+                : _csignals_T_17 | _csignals_T_19
+                    ? 3'h2
+                    : _GEN_3
+                        ? 3'h1
+                        : _csignals_T_33
+                            ? 3'h4
+                            : _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1};
+    exe_alu_out =
+      exe_reg_exe_fun == 5'hE
+        ? exe_reg_op1_data
+        : exe_reg_exe_fun == 5'h9
+            ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
+            : exe_reg_exe_fun == 5'h8
+                ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
+                : exe_reg_exe_fun == 5'h7
+                    ? exe_reg_op1_data >> _GEN_4
+                    : exe_reg_exe_fun == 5'h6
+                        ? _exe_alu_out_T_8[31:0]
+                        : exe_reg_exe_fun == 5'h5
+                            ? exe_reg_op1_data ^ exe_reg_op2_data
+                            : exe_reg_exe_fun == 5'h4
+                                ? exe_reg_op1_data | exe_reg_op2_data
+                                : exe_reg_exe_fun == 5'h3
+                                    ? exe_reg_op1_data & exe_reg_op2_data
+                                    : exe_reg_exe_fun == 5'h2
+                                        ? exe_reg_op1_data - exe_reg_op2_data
+                                        : exe_reg_exe_fun == 5'h1
+                                            ? exe_reg_op1_data + exe_reg_op2_data
+                                            : 32'h0;
+    if (~stall_flg)
+      id_reg_pc <= if_reg_pc;
+    if (_id_inst_T)
       id_reg_inst <= 32'h0;
-      exe_reg_pc <= 32'h0;
-      exe_reg_wb_addr <= 5'h0;
+    else if (~stall_flg)
+      id_reg_inst <= io_imem_inst;
+    exe_reg_pc <= id_reg_pc;
+    exe_reg_wb_addr <= id_reg_inst[15:11];
+    if (csignals_1 == 2'h0)
+      exe_reg_op1_data <=
+        id_reg_inst[25:21] == 5'h0
+          ? 32'h0
+          : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
+              ? mem_reg_alu_out
+              : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
+                  ? wb_reg_wb_data
+                  : _regfile_ext_R1_data;
+    else if (csignals_1 == 2'h1)
+      exe_reg_op1_data <= id_reg_pc;
+    else
       exe_reg_op1_data <= 32'h0;
+    if (_csignals_T_90 == 3'h5)
+      exe_reg_op2_data <= {id_inst[15:0], 16'h0};
+    else if (_csignals_T_90 == 3'h4)
+      exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
+    else if (_csignals_T_90 == 3'h3 | _csignals_T_90 == 3'h2)
+      exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
+    else if (_csignals_T_90 != 3'h1 | _id_rs2_data_T)
       exe_reg_op2_data <= 32'h0;
-      exe_reg_rs2_data <= 32'h0;
-      exe_reg_exe_fun <= 5'h0;
-      exe_reg_mem_wen <= 2'h0;
+    else
+      exe_reg_op2_data <= _id_rs2_data_T_8;
+    exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
+    if (_csignals_T_5 | _csignals_T_7)
+      exe_reg_exe_fun <= 5'h1;
+    else if (_csignals_T_9)
+      exe_reg_exe_fun <= 5'h2;
+    else if (_csignals_T_11)
+      exe_reg_exe_fun <= 5'h3;
+    else if (_csignals_T_13)
+      exe_reg_exe_fun <= 5'h4;
+    else if (_csignals_T_15)
+      exe_reg_exe_fun <= 5'h5;
+    else if (_csignals_T_17)
+      exe_reg_exe_fun <= 5'h3;
+    else if (_csignals_T_19)
+      exe_reg_exe_fun <= 5'h4;
+    else if (_csignals_T_21)
+      exe_reg_exe_fun <= 5'h6;
+    else if (_csignals_T_23)
+      exe_reg_exe_fun <= 5'h7;
+    else if (_csignals_T_25)
+      exe_reg_exe_fun <= 5'h8;
+    else if (_csignals_T_27)
+      exe_reg_exe_fun <= 5'h9;
+    else if (_csignals_T_29)
+      exe_reg_exe_fun <= 5'hB;
+    else if (_csignals_T_31)
+      exe_reg_exe_fun <= 5'hC;
+    else if (_csignals_T_33)
+      exe_reg_exe_fun <= 5'h1;
+    else if (_csignals_T_35)
+      exe_reg_exe_fun <= 5'hE;
+    else
+      exe_reg_exe_fun <= {4'h0, _csignals_T_37};
+    exe_reg_mem_wen <= 2'h0;
+    if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
+        | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
+      exe_reg_rf_wen <= 2'h1;
+      exe_reg_wb_sel <= 3'h1;
+    end
+    else if (_GEN_2) begin
+      exe_reg_rf_wen <= 2'h0;
+      exe_reg_wb_sel <= 3'h0;
+    end
+    else if (_csignals_T_33) begin
+      exe_reg_rf_wen <= 2'h1;
+      exe_reg_wb_sel <= 3'h3;
+    end
+    else if (_csignals_T_35) begin
       exe_reg_rf_wen <= 2'h0;
       exe_reg_wb_sel <= 3'h0;
-      exe_reg_imm_b_sext <= 32'h0;
-      mem_reg_pc <= 32'h0;
-      mem_reg_wb_addr <= 5'h0;
-      mem_reg_rs2_data <= 32'h0;
-      mem_reg_mem_wen <= 2'h0;
-      mem_reg_rf_wen <= 2'h0;
-      mem_reg_wb_sel <= 3'h0;
-      mem_reg_alu_out <= 32'h0;
-      wb_reg_wb_addr <= 5'h0;
-      wb_reg_rf_wen <= 2'h0;
-      wb_reg_wb_data <= 32'h0;
-      if_reg_pc <= 32'h0;
     end
     else begin
-      automatic logic             _id_rs2_data_T_2;
-      automatic logic [31:0]      id_rs2_data;
-      automatic logic [16:0]      _GEN = {id_inst[31:26], id_inst[10:0]};
-      automatic logic             _csignals_T_5 = _GEN == 17'h20;
-      automatic logic [19:0]      _GEN_0 = {id_inst[31:28], id_inst[15:0]};
-      automatic logic             _csignals_T_7 = _GEN_0 == 20'h80000;
-      automatic logic             _csignals_T_9;
-      automatic logic             _csignals_T_11;
-      automatic logic             _csignals_T_13;
-      automatic logic             _csignals_T_15;
-      automatic logic             _csignals_T_17;
-      automatic logic             _csignals_T_19;
-      automatic logic [16:0]      _GEN_1 = {id_inst[30:20], id_inst[5:0]};
-      automatic logic             _csignals_T_21;
-      automatic logic             _csignals_T_23;
-      automatic logic             _csignals_T_25;
-      automatic logic             _csignals_T_27;
-      automatic logic             _csignals_T_29;
-      automatic logic             _csignals_T_31;
-      automatic logic             _csignals_T_33;
-      automatic logic             _csignals_T_35;
-      automatic logic             _csignals_T_37;
-      automatic logic             _GEN_2;
-      automatic logic             _GEN_3;
-      automatic logic [1:0]       csignals_1;
-      automatic logic [31:0]      _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
-      automatic logic [62:0]      _exe_alu_out_T_14 =
-        {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
-      automatic logic [31:0]      exe_alu_out;
-      automatic logic [7:0][31:0] _GEN_5;
-      _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
-      id_rs2_data =
-        id_inst[20:16] == 5'h0
-          ? 32'h0
-          : id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
-              ? mem_wb_data
-              : id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
-                  ? wb_reg_wb_data
-                  : _regfile_ext_R0_data;
-      _csignals_T_9 = _GEN == 17'h22;
-      _csignals_T_11 = _GEN == 17'h24;
-      _csignals_T_13 = _GEN == 17'h25;
-      _csignals_T_15 = _GEN == 17'h26;
-      _csignals_T_17 = _GEN_0 == 20'hC0000;
-      _csignals_T_19 = _GEN_0 == 20'hD0000;
-      _csignals_T_21 = _GEN_1 == 17'h0;
-      _csignals_T_23 = _GEN_1 == 17'h2;
-      _csignals_T_25 = _GEN_1 == 17'h3;
-      _csignals_T_27 = _GEN == 17'h2A;
-      _csignals_T_29 = _GEN_0 == 20'h40000;
-      _csignals_T_31 = _GEN_0 == 20'h50000;
-      _csignals_T_33 = id_inst == 32'hC000000;
-      _csignals_T_35 = _GEN_0 == 20'h8;
-      _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
-      _GEN_2 = _csignals_T_29 | _csignals_T_31;
-      _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
-      csignals_1 =
-        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
-          ? 2'h0
-          : _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
-      exe_alu_out =
-        exe_reg_exe_fun == 5'h1
-          ? exe_reg_op1_data + exe_reg_op2_data
-          : exe_reg_exe_fun == 5'h2
-              ? exe_reg_op1_data - exe_reg_op2_data
-              : exe_reg_exe_fun == 5'h3
-                  ? exe_reg_op1_data & exe_reg_op2_data
-                  : exe_reg_exe_fun == 5'h4
-                      ? exe_reg_op1_data | exe_reg_op2_data
-                      : exe_reg_exe_fun == 5'h5
-                          ? exe_reg_op1_data ^ exe_reg_op2_data
-                          : exe_reg_exe_fun == 5'h6
-                              ? _exe_alu_out_T_14[31:0]
-                              : exe_reg_exe_fun == 5'h7
-                                  ? exe_reg_op1_data >> _GEN_4
-                                  : exe_reg_exe_fun == 5'h8
-                                      ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
-                                      : exe_reg_exe_fun == 5'h9
-                                          ? {31'h0,
-                                             $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
-                                          : exe_reg_exe_fun == 5'hE
-                                              ? exe_reg_op1_data
-                                              : 32'h0;
-      if (~stall_flg)
-        id_reg_pc <= if_reg_pc;
-      if (_id_inst_T)
-        id_reg_inst <= 32'h0;
-      else if (~stall_flg)
-        id_reg_inst <= io_imem_inst;
-      exe_reg_pc <= id_reg_pc;
-      exe_reg_wb_addr <= id_inst[15:11];
-      if (csignals_1 == 2'h0) begin
-        if (id_inst[25:21] == 5'h0)
-          exe_reg_op1_data <= 32'h0;
-        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2)
-          exe_reg_op1_data <= mem_wb_data;
-        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5)
-          exe_reg_op1_data <= wb_reg_wb_data;
-        else
-          exe_reg_op1_data <= _regfile_ext_R1_data;
-      end
-      else if (csignals_1 == 2'h1)
-        exe_reg_op1_data <= id_reg_pc;
-      else
-        exe_reg_op1_data <= 32'h0;
-      _GEN_5 =
-        {{32'h0},
-         {32'h0},
-         {{id_inst[15:0], 16'h0}},
-         {{{4{id_inst[25]}}, id_inst[25:0], 2'h0}},
-         {{{16{id_inst[15]}}, id_inst[15:0]}},
-         {{{16{id_inst[15]}}, id_inst[15:0]}},
-         {id_rs2_data},
-         {32'h0}};
-      exe_reg_op2_data <=
-        _GEN_5[_csignals_T_5
-                 ? 3'h1
-                 : _csignals_T_7
-                     ? 3'h2
-                     : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
-                         ? 3'h1
-                         : _csignals_T_17 | _csignals_T_19
-                             ? 3'h2
-                             : _GEN_3
-                                 ? 3'h1
-                                 : _csignals_T_33
-                                     ? 3'h4
-                                     : _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1}];
-      exe_reg_rs2_data <= id_rs2_data;
-      if (_csignals_T_5 | _csignals_T_7)
-        exe_reg_exe_fun <= 5'h1;
-      else if (_csignals_T_9)
-        exe_reg_exe_fun <= 5'h2;
-      else if (_csignals_T_11)
-        exe_reg_exe_fun <= 5'h3;
-      else if (_csignals_T_13)
-        exe_reg_exe_fun <= 5'h4;
-      else if (_csignals_T_15)
-        exe_reg_exe_fun <= 5'h5;
-      else if (_csignals_T_17)
-        exe_reg_exe_fun <= 5'h3;
-      else if (_csignals_T_19)
-        exe_reg_exe_fun <= 5'h4;
-      else if (_csignals_T_21)
-        exe_reg_exe_fun <= 5'h6;
-      else if (_csignals_T_23)
-        exe_reg_exe_fun <= 5'h7;
-      else if (_csignals_T_25)
-        exe_reg_exe_fun <= 5'h8;
-      else if (_csignals_T_27)
-        exe_reg_exe_fun <= 5'h9;
-      else if (_csignals_T_29)
-        exe_reg_exe_fun <= 5'hB;
-      else if (_csignals_T_31)
-        exe_reg_exe_fun <= 5'hC;
-      else if (_csignals_T_33)
-        exe_reg_exe_fun <= 5'h1;
-      else if (_csignals_T_35)
-        exe_reg_exe_fun <= 5'hE;
-      else
-        exe_reg_exe_fun <= {4'h0, _csignals_T_37};
-      exe_reg_mem_wen <= 2'h0;
-      if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-          | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
-          | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
-        exe_reg_rf_wen <= 2'h1;
-        exe_reg_wb_sel <= 3'h1;
-      end
-      else if (_GEN_2) begin
-        exe_reg_rf_wen <= 2'h0;
-        exe_reg_wb_sel <= 3'h0;
-      end
-      else if (_csignals_T_33) begin
-        exe_reg_rf_wen <= 2'h1;
-        exe_reg_wb_sel <= 3'h3;
-      end
-      else if (_csignals_T_35) begin
-        exe_reg_rf_wen <= 2'h0;
-        exe_reg_wb_sel <= 3'h0;
-      end
-      else begin
-        exe_reg_rf_wen <= {1'h0, _csignals_T_37};
-        exe_reg_wb_sel <= {2'h0, _csignals_T_37};
-      end
-      exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
-      mem_reg_pc <= exe_reg_pc;
-      mem_reg_wb_addr <= exe_reg_wb_addr;
-      mem_reg_rs2_data <= exe_reg_rs2_data;
-      mem_reg_mem_wen <= exe_reg_mem_wen;
-      mem_reg_rf_wen <= exe_reg_rf_wen;
-      mem_reg_wb_sel <= exe_reg_wb_sel;
-      mem_reg_alu_out <= exe_alu_out;
-      wb_reg_wb_addr <= mem_reg_wb_addr;
-      wb_reg_rf_wen <= mem_reg_rf_wen;
-      wb_reg_wb_data <= mem_wb_data;
-      if (exe_br_flg)
-        if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
-      else if (exe_jmp_flg)
-        if_reg_pc <= exe_alu_out;
-      else if (~stall_flg)
-        if_reg_pc <= if_reg_pc + 32'h4;
+      exe_reg_rf_wen <= {1'h0, _csignals_T_37};
+      exe_reg_wb_sel <= {2'h0, _csignals_T_37};
     end
+    exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
+    mem_reg_pc <= exe_reg_pc;
+    mem_reg_wb_addr <= exe_reg_wb_addr;
+    mem_reg_alu_out <= exe_alu_out;
+    mem_reg_rs2_data <= exe_reg_rs2_data;
+    mem_reg_rf_wen <= exe_reg_rf_wen;
+    mem_reg_wb_sel <= exe_reg_wb_sel;
+    mem_reg_mem_wen <= exe_reg_mem_wen;
+    wb_reg_wb_addr <= mem_reg_wb_addr;
+    wb_reg_rf_wen <= mem_reg_rf_wen;
+    wb_reg_wb_data <=
+      mem_reg_wb_sel == 3'h3
+        ? mem_reg_pc + 32'h4
+        : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
+    if (reset)
+      if_reg_pc <= 32'h0;
+    else if (exe_br_flg)
+      if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
+    else if (exe_jmp_flg)
+      if_reg_pc <= exe_alu_out;
+    else if (~stall_flg)
+      if_reg_pc <= if_reg_pc + 32'h4;
   end // always @(posedge)
   regfile_32x32 regfile_ext (
-    .R0_addr (id_inst[20:16]),
+    .R0_addr (id_reg_inst[20:16]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
     .R0_data (_regfile_ext_R0_data),
-    .R1_addr (id_inst[25:21]),
+    .R1_addr (id_reg_inst[25:21]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
     .R1_data (_regfile_ext_R1_data),
@@ -333,80 +323,44 @@ module Core(
 endmodule
 
 // VCS coverage exclude_file
-module mem_8192x8(
-  input  [12:0] R0_addr,
+module mem_512x32(
+  input  [8:0]  R0_addr,
   input         R0_en,
                 R0_clk,
-  output [7:0]  R0_data,
-  input  [12:0] R1_addr,
+  output [31:0] R0_data,
+  input  [8:0]  R1_addr,
   input         R1_en,
                 R1_clk,
-  output [7:0]  R1_data,
-  input  [12:0] R2_addr,
-  input         R2_en,
-                R2_clk,
-  output [7:0]  R2_data,
-  input  [12:0] R3_addr,
-  input         R3_en,
-                R3_clk,
-  output [7:0]  R3_data,
-  input  [12:0] R4_addr,
-  input         R4_en,
-                R4_clk,
-  output [7:0]  R4_data,
-  input  [12:0] R5_addr,
-  input         R5_en,
-                R5_clk,
-  output [7:0]  R5_data,
-  input  [12:0] R6_addr,
-  input         R6_en,
-                R6_clk,
-  output [7:0]  R6_data,
-  input  [12:0] R7_addr,
-  input         R7_en,
-                R7_clk,
-  output [7:0]  R7_data,
-  input  [12:0] W0_addr,
+  output [31:0] R1_data,
+  input  [8:0]  W0_addr,
   input         W0_en,
                 W0_clk,
-  input  [7:0]  W0_data,
-  input  [12:0] W1_addr,
-  input         W1_en,
-                W1_clk,
-  input  [7:0]  W1_data,
-  input  [12:0] W2_addr,
-  input         W2_en,
-                W2_clk,
-  input  [7:0]  W2_data,
-  input  [12:0] W3_addr,
-  input         W3_en,
-                W3_clk,
-  input  [7:0]  W3_data
+  input  [31:0] W0_data
 );
 
-  reg [7:0] Memory[0:8191];
+  reg [31:0] Memory[0:511];
+  reg        _R0_en_d0;
+  reg [8:0]  _R0_addr_d0;
+  always @(posedge R0_clk) begin
+    _R0_en_d0 <= R0_en;
+    _R0_addr_d0 <= R0_addr;
+  end // always @(posedge)
+  reg        _R1_en_d0;
+  reg [8:0]  _R1_addr_d0;
+  always @(posedge R1_clk) begin
+    _R1_en_d0 <= R1_en;
+    _R1_addr_d0 <= R1_addr;
+  end // always @(posedge)
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr] <= W0_data;
-    if (W1_en & 1'h1)
-      Memory[W1_addr] <= W1_data;
-    if (W2_en & 1'h1)
-      Memory[W2_addr] <= W2_data;
-    if (W3_en & 1'h1)
-      Memory[W3_addr] <= W3_data;
   end // always @(posedge)
   `ifdef ENABLE_INITIAL_MEM_
     initial
       $readmemh("src/hex/mem.hex", Memory);
   `endif // ENABLE_INITIAL_MEM_
-  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
-  assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
-  assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
-  assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
-  assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
-  assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
-  assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
-  assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
+  assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
+  assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
 endmodule
 
 module Memory(
@@ -419,71 +373,20 @@ module Memory(
   input  [31:0] io_dmem_wdata
 );
 
-  wire [7:0]  _mem_ext_R0_data;
-  wire [7:0]  _mem_ext_R1_data;
-  wire [7:0]  _mem_ext_R2_data;
-  wire [7:0]  _mem_ext_R3_data;
-  wire [7:0]  _mem_ext_R4_data;
-  wire [7:0]  _mem_ext_R5_data;
-  wire [7:0]  _mem_ext_R6_data;
-  wire [7:0]  _mem_ext_R7_data;
-  wire [12:0] _io_dmem_rdata_T_1 = io_dmem_addr[12:0] + 13'h1;
-  wire [12:0] _io_dmem_rdata_T_4 = io_dmem_addr[12:0] + 13'h2;
-  wire [12:0] _io_dmem_rdata_T_7 = io_dmem_addr[12:0] + 13'h3;
-  mem_8192x8 mem_ext (
-    .R0_addr (io_imem_addr[12:0] + 13'h3),
+  mem_512x32 mem_ext (
+    .R0_addr (io_imem_addr[10:2]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
-    .R0_data (_mem_ext_R0_data),
-    .R1_addr (io_imem_addr[12:0] + 13'h2),
+    .R0_data (io_imem_inst),
+    .R1_addr (io_dmem_addr[10:2]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
-    .R1_data (_mem_ext_R1_data),
-    .R2_addr (io_imem_addr[12:0] + 13'h1),
-    .R2_en   (1'h1),
-    .R2_clk  (clock),
-    .R2_data (_mem_ext_R2_data),
-    .R3_addr (io_imem_addr[12:0]),
-    .R3_en   (1'h1),
-    .R3_clk  (clock),
-    .R3_data (_mem_ext_R3_data),
-    .R4_addr (_io_dmem_rdata_T_7),
-    .R4_en   (1'h1),
-    .R4_clk  (clock),
-    .R4_data (_mem_ext_R4_data),
-    .R5_addr (_io_dmem_rdata_T_4),
-    .R5_en   (1'h1),
-    .R5_clk  (clock),
-    .R5_data (_mem_ext_R5_data),
-    .R6_addr (_io_dmem_rdata_T_1),
-    .R6_en   (1'h1),
-    .R6_clk  (clock),
-    .R6_data (_mem_ext_R6_data),
-    .R7_addr (io_dmem_addr[12:0]),
-    .R7_en   (1'h1),
-    .R7_clk  (clock),
-    .R7_data (_mem_ext_R7_data),
-    .W0_addr (_io_dmem_rdata_T_7),
+    .R1_data (io_dmem_rdata),
+    .W0_addr (io_dmem_addr[10:2]),
     .W0_en   (io_dmem_wen),
     .W0_clk  (clock),
-    .W0_data (io_dmem_wdata[7:0]),
-    .W1_addr (_io_dmem_rdata_T_4),
-    .W1_en   (io_dmem_wen),
-    .W1_clk  (clock),
-    .W1_data (io_dmem_wdata[15:8]),
-    .W2_addr (_io_dmem_rdata_T_1),
-    .W2_en   (io_dmem_wen),
-    .W2_clk  (clock),
-    .W2_data (io_dmem_wdata[23:16]),
-    .W3_addr (io_dmem_addr[12:0]),
-    .W3_en   (io_dmem_wen),
-    .W3_clk  (clock),
-    .W3_data (io_dmem_wdata[31:24])
+    .W0_data (io_dmem_wdata)
   );
-  assign io_imem_inst =
-    {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
-  assign io_dmem_rdata =
-    {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
 endmodule
 
 module Top(
diff --git a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
index 1e3ad44..6c5ef9b 100755
--- a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
+++ b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
diff --git a/project/project/project/target/streams/_global/update/_global/streams/out b/project/project/project/target/streams/_global/update/_global/streams/out
index fb56c45..1ed207b 100755
--- a/project/project/project/target/streams/_global/update/_global/streams/out
+++ b/project/project/project/target/streams/_global/update/_global/streams/out
@@ -1,3 +1,8 @@
-[debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")
+[warn] sbt-bloop_2.12_1.0-2.0.6.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar
+[debug] not up to date. inChanged = false, force = false
+[debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")...
+[info] Updating 
+[info] Resolved  dependencies
+[info] Fetching artifacts of 
+[info] Fetched artifacts of 
+[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")
diff --git a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous
index d3be71e..0be10d1 100755
--- a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
diff --git a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export
index 8d01fa8..ddad066 100755
--- a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export
+++ b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/project/target/streams/compile/incOptions/_global/streams/out
index 7231079..e050d1c 100755
--- a/project/project/project/target/streams/compile/incOptions/_global/streams/out
+++ b/project/project/project/target/streams/compile/incOptions/_global/streams/out
@@ -1,5 +1,5 @@
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
 [debug] About to delete class files:
 [debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
diff --git a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
index aef0f5a..c9f71f1 100755
--- a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
+++ b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
@@ -1 +1 @@
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diff --git a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export
index 8d01fa8..ddad066 100755
--- a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export
+++ b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export
index aef0f5a..c9f71f1 100755
--- a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export
+++ b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export
@@ -1 +1 @@
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jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar
diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
index 8d01fa8..ddad066 100755
--- a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
+++ b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
index 07ec83b..44ce294 100755
--- a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
+++ b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
diff --git a/project/project/target/streams/_global/updateClassifiers/_global/streams/out b/project/project/target/streams/_global/updateClassifiers/_global/streams/out
index 6743020..4d9a95a 100755
--- a/project/project/target/streams/_global/updateClassifiers/_global/streams/out
+++ b/project/project/target/streams/_global/updateClassifiers/_global/streams/out
@@ -1,3 +1,6 @@
-[debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")
+[warn] sbt-bloop_2.12_1.0-2.0.6-sources.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6-sources.jar
+[debug] not up to date. inChanged = false, force = false
+[debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")...
+[info] Fetching artifacts of 
+[info] Fetched artifacts of 
+[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")
diff --git a/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/target/streams/compile/_global/_global/compileOutputs/previous
index 29633ad..f4b289d 100755
--- a/project/project/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/project/project/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
diff --git a/project/project/target/streams/compile/bloopGenerate/_global/streams/out b/project/project/target/streams/compile/bloopGenerate/_global/streams/out
index c6e9ce7..a178d26 100755
--- a/project/project/target/streams/compile/bloopGenerate/_global/streams/out
+++ b/project/project/target/streams/compile/bloopGenerate/_global/streams/out
@@ -1,4 +1,4 @@
 [debug] [micore-build-build] Classpath dependencies List()
 [debug] [micore-build-build] Dependencies from configurations List()
-[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'
+[debug] Bloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/nfs/project/micore/project/project/.bloop/micore-build-build.json'
 [success] Generated .bloop/micore-build-build.json
diff --git a/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/target/streams/compile/exportedProducts/_global/streams/export
index 454272b..ebfe31c 100755
--- a/project/project/target/streams/compile/exportedProducts/_global/streams/export
+++ b/project/project/target/streams/compile/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/target/streams/compile/incOptions/_global/streams/out
index 66abc73..d6cce43 100755
--- a/project/project/target/streams/compile/incOptions/_global/streams/out
+++ b/project/project/target/streams/compile/incOptions/_global/streams/out
@@ -1,5 +1,5 @@
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
 [debug] About to delete class files:
 [debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
diff --git a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
index bde13f8..9fcd8a5 100755
--- a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
+++ b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
+/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
diff --git a/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/target/streams/runtime/exportedProducts/_global/streams/export
index 454272b..ebfe31c 100755
--- a/project/project/target/streams/runtime/exportedProducts/_global/streams/export
+++ b/project/project/target/streams/runtime/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/target/streams/runtime/fullClasspath/_global/streams/export
index bde13f8..9fcd8a5 100755
--- a/project/project/target/streams/runtime/fullClasspath/_global/streams/export
+++ b/project/project/target/streams/runtime/fullClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
+/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
diff --git a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
index 454272b..ebfe31c 100755
--- a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
+++ b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
index 00763b6..cbf7781 100755
--- a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
+++ b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp
@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/nfs/project/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
\ No newline at end of file
diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous
index 3f53060..7c8379a 100755
--- a/project/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/project/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
\ No newline at end of file
diff --git a/project/target/streams/compile/bloopGenerate/_global/streams/out b/project/target/streams/compile/bloopGenerate/_global/streams/out
index 0816633..75e1bc0 100755
--- a/project/target/streams/compile/bloopGenerate/_global/streams/out
+++ b/project/target/streams/compile/bloopGenerate/_global/streams/out
@@ -1,4 +1,4 @@
 [debug] [micore-build] Classpath dependencies List()
 [debug] [micore-build] Dependencies from configurations List()
-[debug] Bloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json'
+[debug] Bloop wrote the configuration of project 'micore-build' to '/home/gh0s7/nfs/project/micore/project/.bloop/micore-build.json'
 [success] Generated .bloop/micore-build.json
diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export
index 4006493..98fdd50 100755
--- a/project/target/streams/compile/exportedProducts/_global/streams/export
+++ b/project/target/streams/compile/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out
index 44649e0..b45e303 100755
--- a/project/target/streams/compile/incOptions/_global/streams/out
+++ b/project/target/streams/compile/incOptions/_global/streams/out
@@ -1,5 +1,5 @@
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
 [debug] About to delete class files:
 [debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes.bak
diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export
index b0b5605..8839bfe 100755
--- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export
+++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
+/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export
index 4006493..98fdd50 100755
--- a/project/target/streams/runtime/exportedProducts/_global/streams/export
+++ b/project/target/streams/runtime/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export
index b0b5605..8839bfe 100755
--- a/project/target/streams/runtime/fullClasspath/_global/streams/export
+++ b/project/target/streams/runtime/fullClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
+/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar
diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
index 4006493..98fdd50 100755
--- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
+++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes
+/home/gh0s7/nfs/project/micore/project/target/scala-2.12/sbt-1.0/classes
diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala
index 2d4b000..d4d4799 100755
--- a/src/main/scala/micore/Core.scala
+++ b/src/main/scala/micore/Core.scala
@@ -4,7 +4,6 @@ import chisel3._
 import chisel3.util._
 import common.Consts._
 import common.Instructions._
-import os.list
 
 class Core extends Module {
   val io = IO(new Bundle {
@@ -13,253 +12,245 @@ class Core extends Module {
     val exit = Output(Bool())
   })
 
-  val regfile = Mem(32, UInt(WORD_LEN.W))
+  // Block RAM for data memory
+  val regfile = SyncReadMem(32, UInt(WORD_LEN.W))
 
   // ********* Pipeline Registers *********
-  // IF/ID state
-  val id_reg_pc = RegInit(0.U(WORD_LEN.W))
-  val id_reg_inst = RegInit(0.U(WORD_LEN.W))
+  val id_reg = Reg(new Bundle {
+    val pc = UInt(WORD_LEN.W)
+    val inst = UInt(WORD_LEN.W)
+  })
 
-  // ID/EX state
-  val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-  val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
-  val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
-  val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-  val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
-  val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W))
-  val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W))
+  val exe_reg = Reg(new Bundle {
+    val pc = UInt(WORD_LEN.W)
+    val wb_addr = UInt(ADDR_LEN.W)
+    val op1_data = UInt(WORD_LEN.W)
+    val op2_data = UInt(WORD_LEN.W)
+    val rs2_data = UInt(WORD_LEN.W)
+    val exe_fun = UInt(EXE_FUN_LEN.W)
+    val mem_wen = UInt(MEN_LEN.W)
+    val rf_wen = UInt(REN_LEN.W)
+    val wb_sel = UInt(WB_SEL_LEN.W)
+    val imm_b_sext = UInt(WORD_LEN.W)
+  })
 
-  // EX/MEM state
-  val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
-  val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-  val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W))
-  val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
-  val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
-  val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-  val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
-  val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
+  val mem_reg = Reg(new Bundle {
+    val pc = UInt(WORD_LEN.W)
+    val wb_addr = UInt(ADDR_LEN.W)
+    val alu_out = UInt(WORD_LEN.W)
+    val rs2_data = UInt(WORD_LEN.W)
+    val rf_wen = UInt(REN_LEN.W)
+    val wb_sel = UInt(WB_SEL_LEN.W)
+    val mem_wen = UInt(MEN_LEN.W)
+  })
 
-  // MEM/WB state
-  val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
-  val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
-  val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
+  val wb_reg = Reg(new Bundle {
+    val wb_addr = UInt(ADDR_LEN.W)
+    val rf_wen = UInt(REN_LEN.W)
+    val wb_data = UInt(WORD_LEN.W)
+  })
 
   // ********* Instruction Fetch (IF) Stage *********
   val if_reg_pc = RegInit(START_ADDR)
   io.imem.addr := if_reg_pc
   val if_inst = io.imem.inst
 
-  val stall_flg = Wire(Bool()) // 停顿标志
-  val exe_br_flg = Wire(Bool()) // 跳转标志
-  val exe_br_target = Wire(UInt(WORD_LEN.W)) // 跳转目标地址
-  val exe_jmp_flg = Wire(Bool()) // 跳转标志
-  val exe_alu_out = Wire(UInt(WORD_LEN.W)) // ALU输出
+  val stall_flg = Wire(Bool()) 
+  val exe_br_flg = Wire(Bool()) 
+  val exe_br_target = Wire(UInt(WORD_LEN.W))
+  val exe_jmp_flg = Wire(Bool())
+  val exe_alu_out = Wire(UInt(WORD_LEN.W))
 
   val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W)
-  val if_pc_next =
-    MuxCase(
-      if_pc_plus4,
-      Seq(
-        exe_br_flg -> exe_br_target,
-        exe_jmp_flg -> exe_alu_out,
-        stall_flg -> if_reg_pc
-      )
+  val if_pc_next = MuxCase(
+    if_pc_plus4,
+    Seq(
+      exe_br_flg -> exe_br_target,
+      exe_jmp_flg -> exe_alu_out,
+      stall_flg -> if_reg_pc
     )
+  )
   if_reg_pc := if_pc_next
 
   // ********* IF/ID Stage *********
-  id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc)
-  id_reg_inst := MuxCase(
+  id_reg.pc := Mux(stall_flg, id_reg.pc, if_reg_pc)
+  id_reg.inst := MuxCase(
     if_inst,
     Seq(
       (exe_br_flg || exe_jmp_flg) -> BUBBLE,
-      stall_flg -> id_reg_inst
+      stall_flg -> id_reg.inst
     )
   )
 
   // ********* Decode (ID) Stage *********
-  val id_rs1_addr_b = id_reg_inst(25, 21)
-  val id_rs2_addr_b = id_reg_inst(20, 16)
+  val id_rs1_addr = id_reg.inst(25, 21)
+  val id_rs2_addr = id_reg.inst(20, 16)
+  val id_wb_addr = id_reg.inst(15, 11)
 
-  // 与EX数据冒险
+  // Data Hazard
   val id_rs1_data_hazard =
-    (exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr)
+    (exe_reg.rf_wen === REN_S) && (id_rs1_addr =/= 0.U) && (id_rs1_addr === exe_reg.wb_addr)
   val id_rs2_data_hazard =
-    (exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr)
+    (exe_reg.rf_wen === REN_S) && (id_rs2_addr =/= 0.U) && (id_rs2_addr === exe_reg.wb_addr)
   stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
 
-  val id_inst =
-    Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
+  val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
 
-  val id_rs1_addr = id_inst(25, 21)
-  val id_rs2_addr = id_inst(20, 16)
-  val id_wb_addr = id_inst(15, 11)
-  val mem_wb_data = Wire(UInt(WORD_LEN.W))
-  val id_rs1_data = MuxCase(
-    regfile(id_rs1_addr),
-    Seq(
-      (id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W),
-      ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
-      ((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
-    )
-  )
-  val id_rs2_data = MuxCase(
-    regfile(id_rs2_addr),
-    Seq(
-      (id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W),
-      ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
-      ((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
-    )
-  )
-
-  val id_imm_i = id_inst(15, 0)
-  val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
-  val id_imm_s = id_inst(15, 0)
-  val id_imm_s_sext = Cat(Fill(16, id_imm_s(15)), id_imm_s)
-  val id_imm_b = id_inst(15, 0)
-  val id_imm_b_sext = Cat(Fill(16, id_imm_b(15)), id_imm_b)
-  val id_imm_j = id_inst(25, 0)
-  val id_imm_j_sext = Cat(Fill(4, id_imm_j(25)), id_imm_j, 0.U(2.W))
-  val id_imm_u = id_inst(15, 0)
-  val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U(1.W)))
-
-  val csignals =
-    ListLookup(
-      id_inst,
-      List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-      Array(
-        LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
-        SW -> List(ALU_ADD, OP1_RS1, OP2_IMS, MEN_S, REN_X, WB_X),
-        ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-        SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-        ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-        SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-        BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-        BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-        JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
-        JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
-        LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
+  val id_rs1_data = Mux(
+    id_rs1_addr === 0.U,
+    0.U(WORD_LEN.W),
+    Mux(
+      (id_rs1_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
+      mem_reg.alu_out,
+      Mux(
+        (id_rs1_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
+        wb_reg.wb_data,
+        regfile(id_rs1_addr)
       )
     )
-
-  val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
-    csignals
-
-  val id_op1_data = MuxCase(
+  )
+  val id_rs2_data = Mux(
+    id_rs2_addr === 0.U,
     0.U(WORD_LEN.W),
-    Seq(
-      (id_op1_sel === OP1_RS1) -> id_rs1_data,
-      (id_op1_sel === OP1_PC) -> id_reg_pc
+    Mux(
+      (id_rs2_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
+      mem_reg.alu_out,
+      Mux(
+        (id_rs2_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
+        wb_reg.wb_data,
+        regfile(id_rs2_addr)
+      )
     )
   )
-  val id_op2_data = MuxCase(
-    0.U(WORD_LEN.W),
+
+  // 立即数扩展
+  val id_imm_i_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
+  val id_imm_b_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
+
+  // 控制信号解码
+  val csignals = ListLookup(
+    id_inst,
+    List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
+    Array(
+      LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
+      SW -> List(ALU_ADD, OP1_RS1, OP2_IMS, MEN_S, REN_X, WB_X),
+      ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
+      BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
+      BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
+      JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
+      JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
+      LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
+    )
+  )
+
+  val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = csignals
+
+  val id_op1_data = Mux(
+    id_op1_sel === OP1_RS1,
+    id_rs1_data,
+    Mux(id_op1_sel === OP1_PC, id_reg.pc, 0.U(WORD_LEN.W))
+  )
+  val id_op2_data = MuxLookup(
+    id_op2_sel,
+    0.U(WORD_LEN.W)
+  )(
     Seq(
-      (id_op2_sel === OP2_RS2) -> id_rs2_data,
-      (id_op2_sel === OP2_IMI) -> id_imm_i_sext,
-      (id_op2_sel === OP2_IMS) -> id_imm_s_sext,
-      (id_op2_sel === OP2_IMJ) -> id_imm_j_sext,
-      (id_op2_sel === OP2_IMU) -> id_imm_u_shifted
+      OP2_RS2 -> id_rs2_data,
+      OP2_IMI -> id_imm_i_sext,
+      OP2_IMS -> id_imm_i_sext,
+      OP2_IMJ -> Cat(Fill(4, id_inst(25)), id_inst(25, 0), 0.U(2.W)),
+      OP2_IMU -> Cat(id_inst(15, 0), Fill(16, 0.U))
     )
   )
 
   // ********* Decode/Execute (ID/EX) Stage *********
-  exe_reg_pc := id_reg_pc
-  exe_reg_op1_data := id_op1_data
-  exe_reg_op2_data := id_op2_data
-  exe_reg_rs2_data := id_rs2_data
-  exe_reg_wb_addr := id_wb_addr
-  exe_reg_wb_sel := id_wb_sel
-  exe_reg_mem_wen := id_mem_wen
-  exe_reg_rf_wen := id_rf_wen
-  exe_reg_imm_b_sext := id_imm_b_sext
-  exe_reg_imm_i_sext := id_imm_i_sext
-  exe_reg_imm_s_sext := id_imm_s_sext
-  exe_reg_imm_u_shifted := id_imm_u_shifted
-  exe_reg_exe_fun := id_exe_fun
+  exe_reg.pc := id_reg.pc
+  exe_reg.op1_data := id_op1_data
+  exe_reg.op2_data := id_op2_data
+  exe_reg.rs2_data := id_rs2_data
+  exe_reg.wb_addr := id_wb_addr
+  exe_reg.wb_sel := id_wb_sel
+  exe_reg.mem_wen := id_mem_wen
+  exe_reg.rf_wen := id_rf_wen
+  exe_reg.imm_b_sext := id_imm_b_sext
+  exe_reg.exe_fun := id_exe_fun
 
   // ********* Execute (EX) Stage *********
-  exe_alu_out := MuxCase(
-    0.U(WORD_LEN.W),
+  exe_alu_out := MuxLookup(
+    exe_reg.exe_fun,
+    0.U(WORD_LEN.W)
+  )(
     Seq(
-      (exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data),
-      (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(
-        4,
-        0
-      ))(31, 0),
-      (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(
-        4,
-        0
-      )).asUInt,
-      (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
-        4,
-        0
-      )).asUInt,
-      (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
-      (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
+      ALU_ADD -> (exe_reg.op1_data + exe_reg.op2_data),
+      ALU_SUB -> (exe_reg.op1_data - exe_reg.op2_data),
+      ALU_AND -> (exe_reg.op1_data & exe_reg.op2_data),
+      ALU_OR  -> (exe_reg.op1_data | exe_reg.op2_data),
+      ALU_XOR -> (exe_reg.op1_data ^ exe_reg.op2_data),
+      ALU_SLL -> (exe_reg.op1_data << exe_reg.op2_data(4, 0))(31, 0),
+      ALU_SRL -> (exe_reg.op1_data >> exe_reg.op2_data(4, 0)).asUInt,
+      ALU_SRA -> (exe_reg.op1_data.asSInt >> exe_reg.op2_data(4, 0)).asUInt,
+      ALU_SLT -> (exe_reg.op1_data.asSInt < exe_reg.op2_data.asSInt).asUInt,
+      ALU_COPY1 -> exe_reg.op1_data
     )
   )
 
-  exe_br_flg := MuxCase(
-    false.B,
+  exe_br_flg := MuxLookup(
+    exe_reg.exe_fun,
+    false.B
+  )(
     Seq(
-      (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data),
-      (exe_reg_exe_fun === BR_BNE) -> (exe_reg_op1_data =/= exe_reg_op2_data)
+      BR_BEQ -> (exe_reg.op1_data === exe_reg.op2_data),
+      BR_BNE -> (exe_reg.op1_data =/= exe_reg.op2_data)
     )
   )
 
-  exe_br_target := exe_reg_pc + exe_reg_imm_b_sext
+  exe_br_target := exe_reg.pc + exe_reg.imm_b_sext
+  exe_jmp_flg := (exe_reg.wb_sel === WB_PC)
 
-  exe_jmp_flg := (exe_reg_wb_sel === WB_PC)
+  // ********* Execute/Memory (EX/MEM) Stage *********
+  mem_reg.pc := exe_reg.pc
+  mem_reg.wb_addr := exe_reg.wb_addr
+  mem_reg.alu_out := exe_alu_out
+  mem_reg.rs2_data := exe_reg.rs2_data
+  mem_reg.rf_wen := exe_reg.rf_wen
+  mem_reg.wb_sel := exe_reg.wb_sel
+  mem_reg.mem_wen := exe_reg.mem_wen
 
-  // ********** Execute/Memory (EX/MEM) Stage ***********
-  mem_reg_pc := exe_reg_pc
-  mem_reg_op1_data := exe_reg_op1_data
-  mem_reg_rs2_data := exe_reg_rs2_data
-  mem_reg_wb_addr := exe_reg_wb_addr
-  mem_reg_alu_out := exe_alu_out
-  mem_reg_rf_wen := exe_reg_rf_wen
-  mem_reg_wb_sel := exe_reg_wb_sel
-  mem_reg_mem_wen := exe_reg_mem_wen
+  // ********* Memory (MEM) Stage *********
+  io.dmem.addr := mem_reg.alu_out
+  io.dmem.wen := mem_reg.mem_wen
+  io.dmem.wdata := mem_reg.rs2_data
 
-  // ********* Memory (MEM) Stage ***********
-  io.dmem.addr := mem_reg_alu_out
-  io.dmem.wen := mem_reg_mem_wen
-  io.dmem.wdata := mem_reg_rs2_data
-
-  mem_wb_data := MuxCase(
-    mem_reg_alu_out,
+  val mem_wb_data = MuxLookup(
+    mem_reg.wb_sel,
+    mem_reg.alu_out
+  )(
     Seq(
-      (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata,
-      (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W))
+      WB_MEM -> io.dmem.rdata,
+      WB_PC -> (mem_reg.pc + 4.U(WORD_LEN.W))
     )
   )
-  // ********** Memory/Write Back (MEM/WB) Stage ***********
-  wb_reg_wb_data := mem_wb_data
-  wb_reg_rf_wen := mem_reg_rf_wen
-  wb_reg_wb_addr := mem_reg_wb_addr
+
+  // ********* Memory/Write Back (MEM/WB) Stage *********
+  wb_reg.wb_addr := mem_reg.wb_addr
+  wb_reg.rf_wen := mem_reg.rf_wen
+  wb_reg.wb_data := mem_wb_data
 
   // ********* Write Back (WB) Stage *********
-  when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data }
-
-  io.exit := (id_reg_inst === UNIMP)
+  when(wb_reg.rf_wen === REN_S) {
+    regfile(wb_reg.wb_addr) := wb_reg.wb_data
+  }
 
+  io.exit := (id_reg.inst === UNIMP)
 }
diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala
index a5b2b51..0bc8045 100755
--- a/src/main/scala/micore/Memory.scala
+++ b/src/main/scala/micore/Memory.scala
@@ -23,28 +23,16 @@ class Memory extends Module {
     val dmem = new DmemPortIo
   })
 
-  val mem = Mem(8192, UInt(8.W))
+  // val mem = Mem(8192, UInt(8.W))
+  val mem = SyncReadMem(512, UInt(WORD_LEN.W))
 
   loadMemoryFromFileInline(mem, "src/hex/mem.hex")
 
-  io.imem.inst := Cat(
-    mem(io.imem.addr),
-    mem(io.imem.addr + 1.U(WORD_LEN.W)),
-    mem(io.imem.addr + 2.U(WORD_LEN.W)),
-    mem(io.imem.addr + 3.U(WORD_LEN.W))
-  )
+  io.imem.inst := mem.read(io.imem.addr >> 2) 
 
-  io.dmem.rdata := Cat(
-    mem(io.dmem.addr),
-    mem(io.dmem.addr + 1.U(WORD_LEN.W)),
-    mem(io.dmem.addr + 2.U(WORD_LEN.W)),
-    mem(io.dmem.addr + 3.U(WORD_LEN.W))
-  )
+  io.dmem.rdata := mem.read(io.dmem.addr >> 2) 
 
   when(io.dmem.wen) {
-    mem(io.dmem.addr) := io.dmem.wdata(31, 24)
-    mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
-    mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
-    mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(7, 0)
+    mem.write(io.dmem.addr >> 2, io.dmem.wdata) 
   }
 }
diff --git a/src/main/scala/micore/Top.scala b/src/main/scala/micore/Top.scala
index 342e1a4..39d092e 100755
--- a/src/main/scala/micore/Top.scala
+++ b/src/main/scala/micore/Top.scala
@@ -23,6 +23,11 @@ class Top extends Module {
 object Top extends App {
   ChiselStage.emitSystemVerilogFile(
     new Top,
-    firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
+   firtoolOpts = Array(
+      "--disable-all-randomization", 
+      "--strip-debug-info",
+      "--O=release",
+      "--mlir-timing"
+    )
   )
 }
diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar
old mode 100755
new mode 100644
index 39c4b6d1d63a77f64bca79d3be1b0e545f5d5515..7978f8a255a2d5e6a957ee66e29d87428b4f9b94
GIT binary patch
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diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip
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diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous
index 69717ff..b6a8aad 100755
--- a/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class","/home/gh0s7/nfs/project/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
\ No newline at end of file
diff --git a/target/streams/compile/bloopGenerate/_global/streams/out b/target/streams/compile/bloopGenerate/_global/streams/out
index 64564fd..7734581 100755
--- a/target/streams/compile/bloopGenerate/_global/streams/out
+++ b/target/streams/compile/bloopGenerate/_global/streams/out
@@ -1,4 +1,4 @@
 [debug] [root] Classpath dependencies List()
 [debug] [root] Dependencies from configurations List()
-[debug] Bloop wrote the configuration of project 'root' to '/home/gh0s7/project/ddca/micore/.bloop/root.json'
+[debug] Bloop wrote the configuration of project 'root' to '/home/gh0s7/nfs/project/micore/.bloop/root.json'
 [success] Generated .bloop/root.json
diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out
index 0ef30ff..324a162 100755
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
@@ -1,28 +1,29 @@
 [debug] [zinc] IncrementalCompile -----------
 [debug] IncrementalCompile.incrementalCompile
-[debug] previous = Stamps for: 14 products, 5 sources, 3 libraries
+[debug] previous = Stamps for: 18 products, 5 sources, 2 libraries
 [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala)
-[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Memory.scala), unmodified = ...),Set(),Set(),API Changes: Set())
+[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala), unmodified = ...),Set(),Set(),API Changes: Set())
 [debug] 
 [debug] Initial source changes:
 [debug] 	removed: Set()
 [debug] 	added: Set()
-[debug] 	modified: Set(${BASE}/src/main/scala/micore/Memory.scala)
+[debug] 	modified: Set(${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala)
 [debug] Invalidated products: Set()
 [debug] External API changes: API Changes: Set()
 [debug] Modified binary dependencies: Set()
-[debug] Initial directly invalidated classes: Set(micore.ImemPortIo, micore.Memory, micore.DmemPortIo)
+[debug] Initial directly invalidated classes: Set(micore.ImemPortIo, micore.Core, micore.Memory, micore.Top, micore.DmemPortIo)
 [debug] Sources indirectly invalidated by:
 [debug] 	product: Set()
 [debug] 	binary dep: Set()
 [debug] 	external source: Set()
-[debug] All initially invalidated classes: Set(micore.ImemPortIo, micore.Memory, micore.DmemPortIo)
-[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/micore/Memory.scala)
-[debug] Initial set of included nodes: micore.ImemPortIo, micore.Memory, micore.DmemPortIo
+[debug] All initially invalidated classes: Set(micore.ImemPortIo, micore.Core, micore.Memory, micore.Top, micore.DmemPortIo)
+[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala)
+[debug] Initial set of included nodes: micore.ImemPortIo, micore.Core, micore.Memory, micore.Top, micore.DmemPortIo
+[debug] Recompiling all sources: number of invalidated sources > 50.0 percent of all sources
 [debug] compilation cycle 1
-[info] compiling 1 Scala source to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ...
+[info] compiling 5 Scala sources to /home/gh0s7/nfs/project/micore/target/scala-2.13/classes ...
 [debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar.
-[debug] [zinc] Running cached compiler 312cd0f5 for Scala compiler version 2.13.12
+[debug] [zinc] Running cached compiler 5718a57a for Scala compiler version 2.13.12
 [debug] [zinc] The Scala compiler is invoked with:
 [debug] 	-language:reflectiveCalls
 [debug] 	-deprecation
@@ -33,12 +34,6 @@
 [debug] 	-bootclasspath
 [debug] 	/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar
 [debug] 	-classpath
-[debug] 	/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
-[debug] New invalidations:
-[debug] Initial set of included nodes: 
-[debug] Previously invalidated, but (transitively) depend on new invalidations:
-[debug] Final step, transitive dependencies:
-[debug] 	Set()
-[debug] No classes were invalidated.
-[debug] Scala compilation took 1.708813195 s
+[debug] 	/home/gh0s7/nfs/project/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
+[debug] Scala compilation took 4.734495736 s
 [debug] done compiling
diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export
index 671555b..d173bb5 100755
--- a/target/streams/compile/exportedProductJars/_global/streams/export
+++ b/target/streams/compile/exportedProductJars/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export
index 21cdc14..48eb7f1 100755
--- a/target/streams/compile/exportedProducts/_global/streams/export
+++ b/target/streams/compile/exportedProducts/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes
+/home/gh0s7/nfs/project/micore/target/scala-2.13/classes
diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out
index 204a305..7d21078 100755
--- a/target/streams/compile/incOptions/_global/streams/out
+++ b/target/streams/compile/incOptions/_global/streams/out
@@ -1,17 +1,59 @@
-[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak
 [debug] About to delete class files:
+[debug] 	Core$$anon$1.class
+[debug] 	Consts$.class
+[debug] 	Instructions$.class
+[debug] 	Core$$anon$4.class
+[debug] 	Core$$anon$2.class
+[debug] 	Top$.class
 [debug] 	Memory$$anon$1.class
 [debug] 	ImemPortIo.class
+[debug] 	Core.class
+[debug] 	Core$$anon$5.class
+[debug] 	Consts.class
+[debug] 	Core$$anon$3.class
 [debug] 	DmemPortIo.class
+[debug] 	Top$delayedInit$body.class
 [debug] 	Memory.class
+[debug] 	Top$$anon$1.class
+[debug] 	Instructions.class
+[debug] 	Top.class
 [debug] We backup class files:
+[debug] 	Core$$anon$1.class
+[debug] 	Consts$.class
+[debug] 	Instructions$.class
+[debug] 	Core$$anon$4.class
+[debug] 	Core$$anon$2.class
+[debug] 	Top$.class
 [debug] 	Memory$$anon$1.class
 [debug] 	ImemPortIo.class
+[debug] 	Core.class
+[debug] 	Core$$anon$5.class
+[debug] 	Consts.class
+[debug] 	Core$$anon$3.class
 [debug] 	DmemPortIo.class
+[debug] 	Top$delayedInit$body.class
 [debug] 	Memory.class
+[debug] 	Top$$anon$1.class
+[debug] 	Instructions.class
+[debug] 	Top.class
 [debug] Registering generated classes:
-[debug] 	DmemPortIo.class
+[debug] 	Core$$anon$1.class
+[debug] 	Consts$.class
+[debug] 	Instructions$.class
+[debug] 	Core$$anon$4.class
+[debug] 	Core$$anon$2.class
+[debug] 	Top$.class
 [debug] 	Memory$$anon$1.class
 [debug] 	ImemPortIo.class
+[debug] 	Core.class
+[debug] 	Core$$anon$5.class
+[debug] 	Consts.class
+[debug] 	Core$$anon$3.class
+[debug] 	DmemPortIo.class
+[debug] 	Top$delayedInit$body.class
 [debug] 	Memory.class
-[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
+[debug] 	Top$$anon$1.class
+[debug] 	Instructions.class
+[debug] 	Top.class
+[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/nfs/project/micore/target/scala-2.13/classes.bak
diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs
index 41081fe..b12e6c3 100755
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@@ -1 +1 @@
--686303872
\ No newline at end of file
+-1409454022
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out
index e093500..d1041b8 100755
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@@ -1,35 +1,43 @@
-[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
+[debug] Packaging /home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
 [debug] Input file mappings:
 [debug] 	common
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common
 [debug] 	common/Consts$.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts$.class
 [debug] 	common/Consts.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Consts.class
 [debug] 	common/Instructions$.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions$.class
 [debug] 	common/Instructions.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/common/Instructions.class
 [debug] 	micore
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore
-[debug] 	micore/Core$$anon$1.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore
 [debug] 	micore/Core.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class
-[debug] 	micore/DmemPortIo.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core.class
+[debug] 	micore/Core$$anon$1.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
+[debug] 	micore/Core$$anon$2.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$2.class
+[debug] 	micore/Core$$anon$3.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$3.class
+[debug] 	micore/Core$$anon$4.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$4.class
+[debug] 	micore/Core$$anon$5.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Core$$anon$5.class
 [debug] 	micore/ImemPortIo.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class
-[debug] 	micore/Memory$$anon$1.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/ImemPortIo.class
+[debug] 	micore/DmemPortIo.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/DmemPortIo.class
 [debug] 	micore/Memory.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class
-[debug] 	micore/Top$$anon$1.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class
-[debug] 	micore/Top$.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class
-[debug] 	micore/Top$delayedInit$body.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory.class
+[debug] 	micore/Memory$$anon$1.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
 [debug] 	micore/Top.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top.class
+[debug] 	micore/Top$.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$.class
+[debug] 	micore/Top$$anon$1.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$$anon$1.class
+[debug] 	micore/Top$delayedInit$body.class
+[debug] 	  /home/gh0s7/nfs/project/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
 [debug] Done packaging.
diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output
index ccc866e..4b88d9a 100755
--- a/target/streams/compile/packageBin/_global/streams/output
+++ b/target/streams/compile/packageBin/_global/streams/output
@@ -1 +1 @@
--1359482768
\ No newline at end of file
+210211276
\ No newline at end of file
diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
index 112ae53..67820d5 100755
--- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export
index 671555b..d173bb5 100755
--- a/target/streams/runtime/exportedProductJars/_global/streams/export
+++ b/target/streams/runtime/exportedProductJars/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export
index 112ae53..67820d5 100755
--- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export
+++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
+/home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export
index 671555b..d173bb5 100755
--- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export
+++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export
@@ -1 +1 @@
-/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
+/home/gh0s7/nfs/project/micore/target/scala-2.13/-name-_2.13-0.1.0.jar
diff --git a/target/streams/test/bloopGenerate/_global/streams/out b/target/streams/test/bloopGenerate/_global/streams/out
index 270c78b..c960147 100755
--- a/target/streams/test/bloopGenerate/_global/streams/out
+++ b/target/streams/test/bloopGenerate/_global/streams/out
@@ -1,4 +1,4 @@
 [debug] [root-test] Classpath dependencies List()
 [debug] [root-test] Dependencies from configurations List(root)
-[debug] Bloop wrote the configuration of project 'root-test' to '/home/gh0s7/project/ddca/micore/.bloop/root-test.json'
+[debug] Bloop wrote the configuration of project 'root-test' to '/home/gh0s7/nfs/project/micore/.bloop/root-test.json'
 [success] Generated .bloop/root-test.json