From 99703db0dbc2070f2ac5de805e5338607014b446 Mon Sep 17 00:00:00 2001 From: CGH0S7 <776459475@qq.com> Date: Wed, 1 Jan 2025 23:17:04 +0800 Subject: [PATCH] Quest Completed! --- log.txt | 54104 +++++++++++++++- project/project/metals.sbt | 8 + project/project/project/metals.sbt | 8 + .../$57f93b93490ea1894b63.cache} | 0 .../$534d41cbf8671b3d9a73.cache} | 0 .../scala-2.12/sbt-1.0/sync/copy-resource | 1 + .../sbt-1.0/update/update_cache_2.12/inputs | 1 + .../sbt-1.0/update/update_cache_2.12/output | 1 + .../_global/_global/_global/streams/out | 0 .../csrConfiguration/_global/streams/out | 0 .../_global/csrProject/_global/streams/out | 0 .../streams/update_cache_2.12/input_dsp | 1 + .../streams/update_cache_2.12/output_dsp | 1 + .../ivyConfiguration/_global/streams/out | 0 .../_global/ivySbt/_global/streams/out | 0 .../moduleSettings/_global/streams/out | 0 .../projectDescriptors/_global/streams/out | 0 .../_global/streams/out | 0 .../_global/update/_global/streams/out | 3 + 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.../fullClasspath/_global/streams/export | 2 +- .../_global/streams/export | 2 +- .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 2 +- .../unmanagedClasspath/_global/streams/export | 0 .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 0 .../test/bloopGenerate/_global/streams/out | 0 .../bloopPostGenerate/_global/streams/out | 0 src/hex/addi.hex | 4 + src/hex/mem.hex | 2 +- src/main/scala/common/Consts.scala | 2 +- src/main/scala/micore/Core.scala | 360 +- src/test/scala/micore/MicoreSpec.scala | 6 +- target/scala-2.13/-name-_2.13-0.1.0.jar | Bin target/scala-2.13/zinc/inc_compile_2.13.zip | Bin 21767 -> 22045 bytes .../_global/streams/update_cache_2.13/output | 2 +- .../_global/_global/compileOutputs/previous | 2 +- .../compile/compile/_global/streams/out | 15 +- .../compileIncremental/_global/streams/out | 42 +- .../exportedProducts/_global/streams/export | 2 +- .../compile/incOptions/_global/streams/out | 13 +- .../TopOrigin.lo.fir | 477 +- 173 files changed, 54595 insertions(+), 592 deletions(-) mode change 100644 => 100755 log.txt create mode 100755 project/project/metals.sbt create mode 100755 project/project/project/metals.sbt rename project/project/{target/config-classes/$6080031bccf8a03d91ba.cache => project/project/target/config-classes/$57f93b93490ea1894b63.cache} (100%) mode change 100644 => 100755 rename project/project/{target/config-classes/$9fddc3a6676a1ed50a85.cache => project/target/config-classes/$534d41cbf8671b3d9a73.cache} (100%) mode change 100644 => 100755 create mode 100755 project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource create mode 100755 project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs create mode 100755 project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output create mode 100755 project/project/project/target/streams/_global/_global/_global/streams/out create mode 100755 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100644 => 100755 project/target/streams/runtime/unmanagedClasspath/_global/streams/export mode change 100644 => 100755 project/target/streams/runtime/unmanagedClasspath/_global/streams/out mode change 100644 => 100755 project/target/streams/runtime/unmanagedJars/_global/streams/export create mode 100755 project/target/streams/test/bloopGenerate/_global/streams/out create mode 100755 project/target/streams/test/bloopPostGenerate/_global/streams/out mode change 100644 => 100755 target/scala-2.13/-name-_2.13-0.1.0.jar mode change 100644 => 100755 target/scala-2.13/zinc/inc_compile_2.13.zip diff --git a/log.txt b/log.txt old mode 100644 new mode 100755 index 6a184f1..b3247ee --- a/log.txt +++ b/log.txt @@ -1,2 +1,54104 @@ [info] welcome to sbt 1.9.7 (Arch Linux Java 23) - \ No newline at end of file +[info] loading settings for project micore-build from metals.sbt,plugins.sbt ... +[info] loading project definition from /run/media/gh0s7/Data/project/ddca2024/micore/project + + | => micore-build / Compile / compileIncremental 0s +[info] loading settings for project root from build.sbt ... +[info] set current project to %NAME% (in build file:/run/media/gh0s7/Data/project/ddca2024/micore/) + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => root / scalaCompilerBridgeBinaryJar 0s + + | => micore.CTest 0s + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000000 + + | => micore.CTest 0s +id_reg_pc: 0x00000000 + + | => micore.CTest 0s +id_reg_inst: 0x00000000 + + | => micore.CTest 0s +id_inst: 0x00000000 + + | => micore.CTest 0s +id_rs_data: 0x00000000 + + | => micore.CTest 0s +id_rt_data: 0x00000000 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x00000000 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000000 + + | => micore.CTest 0s +mem_reg_pc: 0x00000000 + + | => micore.CTest 0s +mem_wb_data: 0x00000000 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000000 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000004 + + | => micore.CTest 0s +id_reg_pc: 0x00000000 + + | => micore.CTest 0s +id_reg_inst: 0x20080001 + + | => micore.CTest 0s +id_inst: 0x20080001 + + | => micore.CTest 0s +id_rs_data: 0x00000000 + + | => micore.CTest 0s +id_rt_data: 0x00000000 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x00000000 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000000 + + | => micore.CTest 0s +mem_reg_pc: 0x00000000 + + | => micore.CTest 0s +mem_wb_data: 0x00000000 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000000 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000008 + + | => micore.CTest 0s +id_reg_pc: 0x00000004 + + | => micore.CTest 0s +id_reg_inst: 0x20100000 + + | => micore.CTest 0s +id_inst: 0x20100000 + + | => micore.CTest 0s +id_rs_data: 0x00000000 + + | => micore.CTest 0s +id_rt_data: 0x00000000 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x00000000 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000001 + + | => micore.CTest 0s +exe_alu_out: 0x00000001 + + | => micore.CTest 0s +mem_reg_pc: 0x00000000 + + | => micore.CTest 0s +mem_wb_data: 0x00000000 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000000 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x0000000c + + | => micore.CTest 0s +id_reg_pc: 0x00000008 + + | => micore.CTest 0s +id_reg_inst: 0x20120005 + + | => micore.CTest 0s +id_inst: 0x20120005 + + | => micore.CTest 0s +id_rs_data: 0x00000000 + + | => micore.CTest 0s +id_rt_data: 0x00000000 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x00000004 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000000 + + | => micore.CTest 0s +mem_reg_pc: 0x00000000 + + | => micore.CTest 0s +mem_wb_data: 0x00000001 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000000 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000010 + + | => micore.CTest 0s +id_reg_pc: 0x0000000c + + | => micore.CTest 0s +id_reg_inst: 0x02088020 + + | => micore.CTest 0s +id_inst: 0x02088020 + + | => micore.CTest 0s +id_rs_data: 0x00000000 + + | => micore.CTest 0s +id_rt_data: 0x00000001 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x00000008 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000005 + + | => micore.CTest 0s +exe_alu_out: 0x00000005 + + | => micore.CTest 0s +mem_reg_pc: 0x00000004 + + | => micore.CTest 0s +mem_wb_data: 0x00000000 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000001 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_pc: 0x00000010 + + | => micore.CTest 0s +id_reg_inst: 0x21080001 + + | => micore.CTest 0s +id_inst: 0x21080001 + + | => micore.CTest 0s +id_rs_data: 0x00000001 + + | => micore.CTest 0s +id_rt_data: 0x00000001 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x0 + + | => micore.CTest 0s +exe_reg_pc: 0x0000000c + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000000 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000001 + + | => micore.CTest 0s +exe_alu_out: 0x00000001 + + | => micore.CTest 0s +mem_reg_pc: 0x00000008 + + | => micore.CTest 0s +mem_wb_data: 0x00000005 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000000 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000001 + + | => micore.CTest 0s +id_rt_data: 0x00000005 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000010 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000001 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000001 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x0000000c + + | => micore.CTest 0s +mem_wb_data: 0x00000001 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000005 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000005 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000001 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000001 + + | => micore.CTest 0s +mem_reg_pc: 0x00000010 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000001 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000001 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000001 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000001 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s +if_reg_pc: 0x00000018 + + | => micore.CTest 0s +id_reg_pc: 0x00000014 + + | => micore.CTest 0s +id_reg_inst: 0x0112502a + + | => micore.CTest 0s +id_inst: 0x20090000 + + | => micore.CTest 0s +id_rs_data: 0x00000002 + + | => micore.CTest 0s +id_rt_data: 0x00000002 + + | => micore.CTest 0s +exe_br_flg: 0x0 + + | => micore.CTest 0s +exe_jmp_flg: 0x0 + + | => micore.CTest 0s +stall_flg: 0x1 + + | => micore.CTest 0s +exe_reg_pc: 0x00000014 + + | => micore.CTest 0s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 0s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 0s +exe_alu_out: 0x00000002 + + | => micore.CTest 0s +mem_reg_pc: 0x00000014 + + | => micore.CTest 0s +mem_wb_data: 0x00000002 + + | => micore.CTest 0s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 0s +--------------- + + | => micore.CTest 0s + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +if_reg_pc: 0x00000018 + + | => micore.CTest 1s +id_reg_pc: 0x00000014 + + | => micore.CTest 1s +id_reg_inst: 0x0112502a + + | => micore.CTest 1s +id_inst: 0x20090000 + + | => micore.CTest 1s +id_rs_data: 0x00000002 + + | => micore.CTest 1s +id_rt_data: 0x00000002 + + | => micore.CTest 1s +exe_br_flg: 0x0 + + | => micore.CTest 1s +exe_jmp_flg: 0x0 + + | => micore.CTest 1s +stall_flg: 0x1 + + | => micore.CTest 1s +exe_reg_pc: 0x00000014 + + | => micore.CTest 1s +exe_reg_op1_data: 0x00000002 + + | => micore.CTest 1s +exe_reg_op2_data: 0x00000000 + + | => micore.CTest 1s +exe_alu_out: 0x00000002 + + | => micore.CTest 1s +mem_reg_pc: 0x00000014 + + | => micore.CTest 1s +mem_wb_data: 0x00000002 + + | => micore.CTest 1s +wb_reg_wb_data: 0x00000002 + + | => micore.CTest 1s +--------------- + + | => micore.CTest 1s +[info] CTest: + + | => micore.CTest 1s +[info] Micore + + | => micore.CTest 1s +[info] - should run the C program *** FAILED *** + + | => micore.CTest 1s +[info]  chiseltest.TimeoutException: timeout on TopOrigin.clock: IO[Clock] at 1000 idle cycles You can extend the timeout by calling .setTimeout() on your clock (setting it to 0 means 'no timeout'). + + | => micore.CTest 1s +[info]  at chiseltest.internal.AccessCheck.simulationStep(AccessCheck.scala:174) + + | => micore.CTest 1s +[info]  at chiseltest.internal.SimController.$anonfun$scheduler$1(SimController.scala:59) + + | => micore.CTest 1s +[info]  at chiseltest.internal.Scheduler.doStep(Scheduler.scala:377) + + | => micore.CTest 1s +[info]  at chiseltest.internal.Scheduler.stepThread(Scheduler.scala:329) + + | => micore.CTest 1s +[info]  at chiseltest.internal.SimController.step(SimController.scala:103) + + | => micore.CTest 1s +[info]  at chiseltest.package$testableClock.step(package.scala:400) + + | => micore.CTest 1s +[info]  at micore.CTest.$anonfun$new$3(MicoreSpec.scala:11) + + | => micore.CTest 1s +[info]  at micore.CTest.$anonfun$new$3$adapted(MicoreSpec.scala:10) + + | => micore.CTest 1s +[info]  at chiseltest.internal.SimController.run(SimController.scala:124) + + | => micore.CTest 1s +[info]  at chiseltest.internal.Context$.$anonfun$runTest$2(Context.scala:30) + + | => micore.CTest 1s +[info]  ... + + | => micore.CTest 1s +[info] Run completed in 2 seconds, 516 milliseconds. + + | => micore.CTest 1s +[info] Total number of tests run: 1 + + | => micore.CTest 1s +[info] Suites: completed 1, aborted 0 + + | => micore.CTest 1s +[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0 + + | => micore.CTest 1s +[info] *** 1 TEST FAILED *** + + | => micore.CTest 1s +[error] Failed tests: + + | => micore.CTest 1s +[error]  micore.CTest + + | => micore.CTest 1s +[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful +[error] Total time: 3 s, completed 2025年1月1日 01:13:58 + \ No newline at end of file diff --git a/project/project/metals.sbt b/project/project/metals.sbt new file mode 100755 index 0000000..e069ffa --- /dev/null +++ b/project/project/metals.sbt @@ -0,0 +1,8 @@ +// format: off +// DO NOT EDIT! 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a/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/update/_global/streams/out b/project/project/project/target/streams/_global/update/_global/streams/out new file mode 100755 index 0000000..982166c --- /dev/null +++ b/project/project/project/target/streams/_global/update/_global/streams/out @@ -0,0 +1,3 @@ +[debug] not up to date. inChanged = true, force = false +[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")... +[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build") diff --git a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100755 index 0000000..d3be71e --- /dev/null +++ b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100755 index 0000000..0637a08 --- /dev/null +++ b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/project/target/streams/compile/bspReporter/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compile/_global/streams/out b/project/project/project/target/streams/compile/compile/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100755 index 0000000..9cca155 --- /dev/null +++ b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1,6 @@ +[debug] [zinc] IncrementalCompile ----------- +[debug] IncrementalCompile.incrementalCompile +[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries +[debug] current source = Set() +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/project/target/streams/compile/copyResources/_global/streams/out new file mode 100755 index 0000000..f25042f --- /dev/null +++ b/project/project/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..98ed4e4 --- /dev/null +++ b/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100755 index 0000000..8d01fa8 --- /dev/null +++ b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..98ed4e4 --- /dev/null +++ b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/project/target/streams/compile/incOptions/_global/streams/out new file mode 100755 index 0000000..7231079 --- /dev/null +++ b/project/project/project/target/streams/compile/incOptions/_global/streams/out @@ -0,0 +1,5 @@ +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] About to delete class files: +[debug] We backup class files: +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100755 index 0000000..98ed4e4 --- /dev/null +++ b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/project/target/streams/compile/scalacOptions/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..aef0f5a --- /dev/null +++ b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100755 index 0000000..8d01fa8 --- /dev/null +++ b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..e2c8173 --- /dev/null +++ b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export new file mode 100755 index 0000000..aef0f5a --- /dev/null +++ b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out b/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out new file mode 100755 index 0000000..d06cba1 --- /dev/null +++ b/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Other repositories: +[debug] Default repositories: diff --git a/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100755 index 0000000..29633ad --- /dev/null +++ b/project/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100755 index 0000000..0637a08 --- /dev/null +++ b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/project/target/streams/compile/bloopGenerate/_global/streams/out b/project/project/target/streams/compile/bloopGenerate/_global/streams/out new file mode 100755 index 0000000..c6e9ce7 --- /dev/null +++ b/project/project/target/streams/compile/bloopGenerate/_global/streams/out @@ -0,0 +1,4 @@ +[debug] [micore-build-build] Classpath dependencies List() +[debug] [micore-build-build] Dependencies from configurations List() +[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json' +[success] Generated .bloop/micore-build-build.json diff --git a/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out b/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out new file mode 100755 index 0000000..d94fa9e --- /dev/null +++ b/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out @@ -0,0 +1 @@ +[debug] Running postGenerate for micore-build-build diff --git a/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/target/streams/compile/bspReporter/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compile/_global/streams/out b/project/project/target/streams/compile/compile/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100755 index 0000000..9cca155 --- /dev/null +++ b/project/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1,6 @@ +[debug] [zinc] IncrementalCompile ----------- +[debug] IncrementalCompile.incrementalCompile +[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries +[debug] current source = Set() +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/target/streams/compile/copyResources/_global/streams/out new file mode 100755 index 0000000..f25042f --- /dev/null +++ b/project/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..7d0296f --- /dev/null +++ b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100755 index 0000000..454272b --- /dev/null +++ b/project/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..7d0296f --- /dev/null +++ b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/2.2.0/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.4.2/launcher-interface-1.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.8.5/caffeine-2.8.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.1.2/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.17.1/log4j-api-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.17.1/log4j-core-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.17.1/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.9.3/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.9.3/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.9.5/compiler-interface-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.9.5/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.12/file-tree-views-2.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.13.0/jna-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.13.0/jna-platform-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.9.1/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal/3.19.0/jline-terminal-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.9.5/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.9.5/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.9.5/zinc_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.9.1/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.9.5/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/jline/jline/2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jna/3.19.0/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jansi/3.19.0/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/checkerframework/checker-qual/3.4.1/checker-qual-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/errorprone/error_prone_annotations/2.4.0/error_prone_annotations-2.4.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.12/2.10.0/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-apache-http_2.12/0.7.0/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-reader/3.19.0/jline-reader-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-builtins/3.19.0/jline-builtins-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-jawn-parser_2.12/0.9.1/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.9.5/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.9.5/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.9.5/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.9.5/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.9.1/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.6.2/ipcsocket-1.6.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/openhft/zero-allocation-hashing/0.10.1/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/2.1.0/jansi-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.7.0/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/target/streams/compile/incOptions/_global/streams/out new file mode 100755 index 0000000..66abc73 --- /dev/null +++ b/project/project/target/streams/compile/incOptions/_global/streams/out @@ -0,0 +1,5 @@ +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] About to delete class files: +[debug] We backup class files: +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100755 index 0000000..7d0296f --- /dev/null +++ b/project/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/2.2.0/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.4.2/launcher-interface-1.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.8.5/caffeine-2.8.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.1.2/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.17.1/log4j-api-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.17.1/log4j-core-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.17.1/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.9.3/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.9.3/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.9.5/compiler-interface-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.9.5/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.12/file-tree-views-2.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.13.0/jna-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.13.0/jna-platform-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.9.1/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal/3.19.0/jline-terminal-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.9.5/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.9.5/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.9.5/zinc_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.9.1/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.9.5/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/jline/jline/2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jna/3.19.0/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jansi/3.19.0/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/checkerframework/checker-qual/3.4.1/checker-qual-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/errorprone/error_prone_annotations/2.4.0/error_prone_annotations-2.4.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.12/2.10.0/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-apache-http_2.12/0.7.0/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-reader/3.19.0/jline-reader-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-builtins/3.19.0/jline-builtins-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-jawn-parser_2.12/0.9.1/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.9.5/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.9.5/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.9.5/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.9.5/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.9.1/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.6.2/ipcsocket-1.6.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/openhft/zero-allocation-hashing/0.10.1/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/2.1.0/jansi-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.7.0/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/target/streams/compile/scalacOptions/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/it/bloopGenerate/_global/streams/out b/project/project/target/streams/it/bloopGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/it/bloopPostGenerate/_global/streams/out b/project/project/target/streams/it/bloopPostGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..bde13f8 --- /dev/null +++ b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar diff --git a/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100755 index 0000000..454272b --- /dev/null +++ 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\ No newline at end of file diff --git a/project/target/streams/_global/ivyConfiguration/_global/streams/out b/project/target/streams/_global/ivyConfiguration/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/_global/ivySbt/_global/streams/out b/project/target/streams/_global/ivySbt/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/_global/moduleSettings/_global/streams/out b/project/target/streams/_global/moduleSettings/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/_global/projectDescriptors/_global/streams/out b/project/target/streams/_global/projectDescriptors/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out old mode 100644 new mode 100755 diff --git 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b/project/target/streams/compile/compileIncremental/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export old mode 100644 new mode 100755 index 98ed4e4..7d0296f --- a/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ b/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export old mode 100644 new mode 100755 index faf6770..4006493 --- a/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export old mode 100644 new mode 100755 index 98ed4e4..7d0296f --- a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -1 +1 @@ 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ven2/org/scala-sbt/zinc-apiinfo_2.12/1.9.5/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.9.5/zinc_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.9.1/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.9.5/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/jline/jline/2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jna/3.19.0/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jansi/3.19.0/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/checkerframework/checker-qual/3.4.1/checker-qual-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/errorprone/error_prone_annotations/2.4.0/error_prone_annotations-2.4.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.12/2.10.0/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-apache-http_2.12/0.7.0/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-reader/3.19.0/jline-reader-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-builtins/3.19.0/jline-builtins-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-jawn-parser_2.12/0.9.1/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.9.5/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.9.5/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.9.5/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.9.5/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.9.1/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.6.2/ipcsocket-1.6.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/openhft/zero-allocation-hashing/0.10.1/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/2.1.0/jansi-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.7.0/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out old mode 100644 new mode 100755 index 96aaeb5..44649e0 --- a/project/target/streams/compile/incOptions/_global/streams/out +++ b/project/target/streams/compile/incOptions/_global/streams/out @@ -1,5 +1,5 @@ -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] About to delete class files: [debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/target/streams/compile/internalDependencyClasspath/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export old mode 100644 new mode 100755 index 98ed4e4..7d0296f --- a/project/target/streams/compile/managedClasspath/_global/streams/export +++ b/project/target/streams/compile/managedClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/compile/scalacOptions/_global/streams/out b/project/target/streams/compile/scalacOptions/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/target/streams/compile/unmanagedClasspath/_global/streams/export old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/target/streams/compile/unmanagedClasspath/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/target/streams/compile/unmanagedJars/_global/streams/export old mode 100644 new mode 100755 diff --git a/project/target/streams/it/bloopGenerate/_global/streams/out b/project/target/streams/it/bloopGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/target/streams/it/bloopPostGenerate/_global/streams/out b/project/target/streams/it/bloopPostGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export old mode 100644 new mode 100755 index 69ab39c..b0b5605 --- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ 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b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export old mode 100644 new mode 100755 index e2c8173..a7fbfb8 --- a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -1 +1 @@ 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a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export old mode 100644 new mode 100755 index e2c8173..a7fbfb8 --- a/project/target/streams/runtime/managedClasspath/_global/streams/export +++ b/project/target/streams/runtime/managedClasspath/_global/streams/export @@ -1 +1 @@ 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+/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export old mode 100644 new mode 100755 diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/project/target/streams/runtime/unmanagedClasspath/_global/streams/out old mode 100644 new mode 100755 diff --git a/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/target/streams/runtime/unmanagedJars/_global/streams/export old mode 100644 new mode 100755 diff --git a/project/target/streams/test/bloopGenerate/_global/streams/out b/project/target/streams/test/bloopGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/target/streams/test/bloopPostGenerate/_global/streams/out b/project/target/streams/test/bloopPostGenerate/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/src/hex/addi.hex b/src/hex/addi.hex index 8e887b9..c725368 100755 --- a/src/hex/addi.hex +++ b/src/hex/addi.hex @@ -2,6 +2,10 @@ 00 09 20 +01 +00 +08 +21 14 45 11 diff --git a/src/hex/mem.hex b/src/hex/mem.hex index bb3d0fa..56ca829 100755 --- a/src/hex/mem.hex +++ b/src/hex/mem.hex @@ -6,7 +6,7 @@ 00 10 20 -05 +65 00 12 20 diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala index 47224e3..893ffc1 100755 --- a/src/main/scala/common/Consts.scala +++ b/src/main/scala/common/Consts.scala @@ -7,7 +7,7 @@ object Consts { // 数据宽度和地址 val WORD_LEN = 32 // 指令和数据的宽度为32位 val START_ADDR = 0x00000000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000 - val BUBBLE = 0x20090000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] + val BUBBLE = 0x20000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令 // 寄存器地址长度 diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala index b35a84d..b20ca87 100755 --- a/src/main/scala/micore/Core.scala +++ b/src/main/scala/micore/Core.scala @@ -15,16 +15,15 @@ class Core extends Module { val regfile = Mem(32, UInt(WORD_LEN.W)) // ********* Pipeline Registers ********* - // IF/ID stage + // IF/ID state val id_reg_pc = RegInit(0.U(WORD_LEN.W)) val id_reg_inst = RegInit(0.U(WORD_LEN.W)) - // ID/EX stage + // ID/EX state val exe_reg_pc = RegInit(0.U(WORD_LEN.W)) val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W)) val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W)) - val exe_reg_rs_data = RegInit(0.U(WORD_LEN.W)) val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W)) val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W)) val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) @@ -33,16 +32,16 @@ class Core extends Module { val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W)) val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W)) - // EX/MEM stage + // EX/MEM state val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) - val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W)) val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) + val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) - // MEM/WB stage + // MEM/WB state val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W)) @@ -75,40 +74,49 @@ class Core extends Module { if_inst, Seq( (exe_br_flg || exe_jmp_flg) -> BUBBLE, - stall_flg -> id_reg_inst + (stall_flg) -> id_reg_inst ) ) // ********* Decode (ID) Stage ********* - val id_rs_addr = id_reg_inst(25, 21) - val id_rt_addr = id_reg_inst(20, 16) - val id_rd_addr = id_reg_inst(15, 11) + val id_rs_addr_b = id_reg_inst(25, 21) + val id_rt_addr_b = id_reg_inst(20, 16) - // Hazard detection + // Data hazard detection val id_rs_data_hazard = - (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr) + (exe_reg_rf_wen === REN_S) && (id_rs_addr_b =/= 0.U) && (id_rs_addr_b === exe_reg_wb_addr) val id_rt_data_hazard = - (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr) - stall_flg := (id_rs_data_hazard || id_rt_data_hazard) && !(exe_reg_wb_sel === WB_MEM) - // stall_flg := 0.U(1.W) + (exe_reg_rf_wen === REN_S) && (id_rt_addr_b =/= 0.U) && (id_rt_addr_b === exe_reg_wb_addr) + stall_flg := (id_rs_data_hazard || id_rt_data_hazard) val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst) + val id_rs_addr = id_inst(25, 21) + val id_rt_addr = id_inst(20, 16) + val id_rd_addr = id_inst(15, 11) + + val mem_wb_data = Wire(UInt(WORD_LEN.W)) val id_rs_data = MuxCase( regfile(id_rs_addr), Seq( (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM - ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB + ((id_rs_addr === exe_reg_wb_addr) && (exe_reg_rf_wen === REN_S)) -> exe_alu_out, // Forward from EX + ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM + ( + (id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S) + ) -> wb_reg_wb_data // Forward from WB ) ) val id_rt_data = MuxCase( regfile(id_rt_addr), Seq( (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM - ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB + ((id_rt_addr === exe_reg_wb_addr) && (exe_reg_rf_wen === REN_S)) -> exe_alu_out, // Forward from EX + ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM + ( + (id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S) + ) -> wb_reg_wb_data // Forward from WB ) ) @@ -165,7 +173,6 @@ class Core extends Module { exe_reg_pc := id_reg_pc exe_reg_op1_data := id_op1_data exe_reg_op2_data := id_op2_data - exe_reg_rs_data := id_rs_data exe_reg_rt_data := id_rt_data exe_reg_wb_addr := MuxCase( id_rt_addr, @@ -214,28 +221,30 @@ class Core extends Module { false.B, Seq( (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data), - (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data) + (exe_reg_exe_fun === BR_BNE) -> (exe_reg_op1_data =/= exe_reg_op2_data) ) ) - exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U(5.W)) + exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U( + 5.W + )) exe_jmp_flg := (exe_reg_wb_sel === WB_PC) // ********* Execute/Memory (EX/MEM) Stage ********* mem_reg_pc := exe_reg_pc + mem_reg_rt_data := exe_reg_rt_data mem_reg_wb_addr := exe_reg_wb_addr mem_reg_alu_out := exe_alu_out - mem_reg_rt_data := exe_reg_rt_data - mem_reg_mem_wen := exe_reg_mem_wen mem_reg_rf_wen := exe_reg_rf_wen mem_reg_wb_sel := exe_reg_wb_sel + mem_reg_mem_wen := exe_reg_mem_wen // ********* Memory (MEM) Stage ********* io.dmem.addr := mem_reg_alu_out io.dmem.wen := mem_reg_mem_wen io.dmem.wdata := mem_reg_rt_data - val mem_wb_data = MuxCase( + mem_wb_data := MuxCase( mem_reg_alu_out, Seq( (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata, @@ -244,9 +253,9 @@ class Core extends Module { ) // ********* Memory/Write Back (MEM/WB) Stage ********* - wb_reg_wb_addr := mem_reg_wb_addr - wb_reg_rf_wen := mem_reg_rf_wen wb_reg_wb_data := mem_wb_data + wb_reg_rf_wen := mem_reg_rf_wen + wb_reg_wb_addr := mem_reg_wb_addr // ********* Write Back (WB) Stage ********* when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) { @@ -257,289 +266,34 @@ class Core extends Module { // ********* Debugging ********* printf(p"---------------\n") + printf(p"if_inst: 0x${Hexadecimal(if_inst)}\n") printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n") printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n") + printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") + printf(p"id_rs_data: 0x${Hexadecimal(id_rs_data)}\n") + printf(p"id_rt_data: 0x${Hexadecimal(id_rt_data)}\n") + printf(p"id_rs_addr: 0x${Hexadecimal(id_rs_addr)}\n") + printf(p"id_rt_addr: 0x${Hexadecimal(id_rt_addr)}\n") + printf(p"id_rd_addr: 0x${Hexadecimal(id_rd_addr)}\n") + // printf(p"id_imm_i_sext: 0x${Hexadecimal(id_imm_i_sext)}\n") + // printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n") + // printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n") + // printf(p"id_rs_data_hazard: 0x${Hexadecimal(id_rs_data_hazard)}\n") + // printf(p"id_rt_data_hazard: 0x${Hexadecimal(id_rt_data_hazard)}\n") + printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n") printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") + printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n") + printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n") printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n") + // printf(p"exe_br_target: 0x${Hexadecimal(exe_br_target)}\n") + printf(p"exe_reg_wb_addr: 0x${Hexadecimal(exe_reg_wb_addr)}\n") printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n") printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") + printf(p"wb_reg_wb_addr: 0x${Hexadecimal(wb_reg_wb_addr)}\n") printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") + printf(p"regfile s0: 0x${(regfile(16.U))}\n") + printf(p"regfile s2: 0x${(regfile(18.U))}\n") + printf(p"regfile t0: 0x${(regfile(8.U))}\n") printf(p"---------------\n") } -// package micore - -// import chisel3._ -// import chisel3.util._ -// import common.Consts._ -// import common.Instructions._ - -// class Core extends Module { -// val io = IO(new Bundle { -// val imem = Flipped(new ImemPortIo()) -// val dmem = Flipped(new DmemPortIo()) -// val exit = Output(Bool()) -// }) - -// val regfile = Mem(32, UInt(WORD_LEN.W)) - -// // ********* Pipeline Registers ********* -// // IF/ID state -// val id_reg_pc = RegInit(0.U(WORD_LEN.W)) -// val id_reg_inst = RegInit(0.U(WORD_LEN.W)) - -// // ID/EX state -// val exe_reg_pc = RegInit(0.U(WORD_LEN.W)) -// val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) -// val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W)) -// val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W)) -// val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W)) -// val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W)) -// val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) -// val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W)) -// val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) -// val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W)) -// val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W)) - -// // EX/MEM state -// val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) -// val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) -// val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W)) -// val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) -// val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) -// val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) -// val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) - -// // MEM/WB state -// val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) -// val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W)) -// val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W)) - -// // ********* Instruction Fetch (IF) Stage ********* -// val if_reg_pc = RegInit(START_ADDR) -// io.imem.addr := if_reg_pc -// val if_inst = io.imem.inst - -// val stall_flg = Wire(Bool()) -// val exe_br_flg = Wire(Bool()) -// val exe_br_target = Wire(UInt(WORD_LEN.W)) -// val exe_jmp_flg = Wire(Bool()) -// val exe_alu_out = Wire(UInt(WORD_LEN.W)) - -// val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W) -// val if_pc_next = MuxCase( -// if_pc_plus4, -// Seq( -// exe_br_flg -> exe_br_target, -// exe_jmp_flg -> exe_alu_out, -// stall_flg -> if_reg_pc // stall -// ) -// ) -// if_reg_pc := if_pc_next - -// // ********* IF/ID Stage ********* -// id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc) -// id_reg_inst := MuxCase( -// if_inst, -// Seq( -// (exe_br_flg || exe_jmp_flg) -> BUBBLE, -// stall_flg -> id_reg_inst -// ) -// ) - -// // ********* Decode (ID) Stage ********* -// val id_rs_addr = id_reg_inst(25, 21) -// val id_rt_addr = id_reg_inst(20, 16) -// val id_rd_addr = id_reg_inst(15, 11) - -// // Data hazard detection -// val id_rs_data_hazard = -// (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr) -// val id_rt_data_hazard = -// (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr) -// stall_flg := 0.U(1.W) -// // stall_flg := (id_rs_data_hazard || id_rt_data_hazard) - -// val id_inst = -// Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst) - -// val mem_wb_data = Wire(UInt(WORD_LEN.W)) -// val id_rs_data = MuxCase( -// regfile(id_rs_addr), -// Seq( -// (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W), -// ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM -// ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB -// ) -// ) -// val id_rt_data = MuxCase( -// regfile(id_rt_addr), -// Seq( -// (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W), -// ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM -// ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB -// ) -// ) - -// val id_imm_i = id_inst(15, 0) -// val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i) -// val id_imm_j = Cat(id_inst(25, 0), Fill(2, 0.U(1.W))) - -// val csignals = ListLookup( -// id_inst, -// List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), -// Array( -// LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM), -// SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_X, WB_X), -// ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), -// SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), -// ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), -// SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), -// BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), -// SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), -// JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), -// JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) -// ) -// ) - -// val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = -// csignals - -// val id_op1_data = MuxCase( -// 0.U(WORD_LEN.W), -// Seq( -// (id_op1_sel === OP1_RS1) -> id_rs_data, -// (id_op1_sel === OP1_PC) -> id_reg_pc -// ) -// ) - -// val id_op2_data = MuxCase( -// 0.U(WORD_LEN.W), -// Seq( -// (id_op2_sel === OP2_RS2) -> id_rt_data, -// (id_op2_sel === OP2_IMI) -> id_imm_i_sext, -// (id_op2_sel === OP2_IMJ) -> id_imm_j -// ) -// ) - -// // ********* Decode/Execute (ID/EX) Stage ********* -// exe_reg_pc := id_reg_pc -// exe_reg_op1_data := id_op1_data -// exe_reg_op2_data := id_op2_data -// exe_reg_rt_data := id_rt_data -// exe_reg_wb_addr := MuxCase( -// id_rt_addr, -// Seq( -// (id_wb_sel === WB_ALU && id_inst( -// 31, -// 26 -// ) === "b000000".U) -> id_rd_addr, // R-type -// (id_inst === JAL) -> 31.U -// ) -// ) -// exe_reg_wb_sel := id_wb_sel -// exe_reg_mem_wen := id_mem_wen -// exe_reg_rf_wen := id_rf_wen -// exe_reg_imm_i_sext := id_imm_i_sext -// exe_reg_imm_j := id_imm_j -// exe_reg_exe_fun := id_exe_fun - -// // ********* Execute (EX) Stage ********* -// exe_alu_out := MuxCase( -// 0.U(WORD_LEN.W), -// Seq( -// (exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data), -// (exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data), -// (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data), -// (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data), -// (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data), -// (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data( -// 4, -// 0 -// ))(31, 0), -// (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data( -// 4, -// 0 -// )).asUInt, -// (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data( -// 4, -// 0 -// )).asUInt, -// (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt, -// (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data -// ) -// ) - -// exe_br_flg := MuxCase( -// false.B, -// Seq( -// (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data), -// (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data) -// ) -// ) - -// exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U(5.W)) -// exe_jmp_flg := (exe_reg_wb_sel === WB_PC) - -// // ********* Execute/Memory (EX/MEM) Stage ********* -// mem_reg_pc := exe_reg_pc -// mem_reg_rt_data := exe_reg_rt_data -// mem_reg_wb_addr := exe_reg_wb_addr -// mem_reg_alu_out := exe_alu_out -// mem_reg_rf_wen := exe_reg_rf_wen -// mem_reg_wb_sel := exe_reg_wb_sel -// mem_reg_mem_wen := exe_reg_mem_wen - -// // ********* Memory (MEM) Stage ********* -// io.dmem.addr := mem_reg_alu_out -// io.dmem.wen := mem_reg_mem_wen -// io.dmem.wdata := mem_reg_rt_data - -// mem_wb_data := MuxCase( -// mem_reg_alu_out, -// Seq( -// (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata, -// (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W)) -// ) -// ) - -// // ********* Memory/Write Back (MEM/WB) Stage ********* -// wb_reg_wb_data := mem_wb_data -// wb_reg_rf_wen := mem_reg_rf_wen -// wb_reg_wb_addr := mem_reg_wb_addr - -// // ********* Write Back (WB) Stage ********* -// when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) { -// regfile(wb_reg_wb_addr) := wb_reg_wb_data -// } - -// io.exit := (id_reg_inst === UNIMP) - -// // ********* Debugging ********* -// printf(p"---------------\n") -// printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") -// printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n") -// printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n") -// printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") -// printf(p"id_rs_data: 0x${Hexadecimal(id_rs_data)}\n") -// printf(p"id_rt_data: 0x${Hexadecimal(id_rt_data)}\n") -// printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n") -// printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n") -// printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n") -// printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") -// printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n") -// printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n") -// printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n") -// printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n") -// printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") -// printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") -// printf(p"---------------\n") -// } diff --git a/src/test/scala/micore/MicoreSpec.scala b/src/test/scala/micore/MicoreSpec.scala index 7c9f8b1..3c80d9d 100755 --- a/src/test/scala/micore/MicoreSpec.scala +++ b/src/test/scala/micore/MicoreSpec.scala @@ -5,11 +5,11 @@ import chiseltest._ import org.scalatest.flatspec.AnyFlatSpec import org.scalatest.matchers.should.Matchers -class CTest extends AnyFlatSpec with ChiselScalatestTester { - "Micore" should "run the C program" in { +class PipelineTest extends AnyFlatSpec with ChiselScalatestTester { + "Micore" should "run the test program" in { test(new TopOrigin) { c => while (!c.io.exit.peek().litToBoolean) { c.clock.step(1) } - c.clock.step(1) + // for (i <- 0 until 24) { c.clock.step(1) } } } } diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar old mode 100644 new mode 100755 diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip old mode 100644 new mode 100755 index d09a03b19f3dface2c8a7f58af4c3883ce55d668..2a881a4ae3ed3ebb37c27d92b26d299986735e5c GIT binary patch literal 22045 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\ No newline at end of file diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous index f82cd18..b950716 100755 --- a/target/streams/compile/_global/_global/compileOutputs/previous +++ b/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] \ No newline at end of file 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\ No newline at end of file diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out index d01a34e..36b4206 100755 --- a/target/streams/compile/compile/_global/streams/out +++ b/target/streams/compile/compile/_global/streams/out @@ -1,4 +1,11 @@ -[error] /run/media/gh0s7/Data/project/ddca2024/micore/src/main/scala/micore/Top.scala:25:9: not found: type TopOrigin -[error]  new TopOrigin, -[error]  ^ -[error] one error found +[error] /run/media/gh0s7/Data/project/ddca2024/micore/src/main/scala/micore/Core.scala:102:8: type mismatch; +[error]  found : Seq[(Object, chisel3.UInt)] +[error]  required: Seq[(chisel3.Bool, ?)] +[error]  Seq( +[error]  ^ +[error] /run/media/gh0s7/Data/project/ddca2024/micore/src/main/scala/micore/Core.scala:113:8: type mismatch; +[error]  found : Seq[(Object, chisel3.UInt)] +[error]  required: Seq[(chisel3.Bool, ?)] +[error]  Seq( +[error]  ^ +[error] two errors found diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index 599b2be..2a8d6f7 100755 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -2,43 +2,5 @@ [debug] IncrementalCompile.incrementalCompile [debug] previous = Stamps for: 24 products, 8 sources, 3 libraries [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/sicore/Top.scala, ${BASE}/src/main/scala/sicore/Memory.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/sicore/Core.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala) -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug]  -[debug] Initial source changes: -[debug]  removed: Set() -[debug]  added: Set() -[debug]  modified: Set(${BASE}/src/main/scala/micore/Core.scala) -[debug] Invalidated products: Set() -[debug] External API changes: API Changes: Set() -[debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(micore.Core) -[debug] Sources indirectly invalidated by: -[debug]  product: Set() -[debug]  binary dep: Set() -[debug]  external source: Set() -[debug] All initially invalidated classes: Set(micore.Core) -[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/micore/Core.scala) -[debug] Initial set of included nodes: micore.Core -[debug] compilation cycle 1 -[info] compiling 1 Scala source to /home/gh0s7/project/ddca/micore/target/scala-2.13/classes ... -[debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar. -[debug] [zinc] Running cached compiler 205a4be3 for Scala compiler version 2.13.12 -[debug] [zinc] The Scala compiler is invoked with: -[debug]  -language:reflectiveCalls -[debug]  -deprecation -[debug]  -feature -[debug]  -Xcheckinit -[debug]  -Ymacro-annotations -[debug]  -Xplugin:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel-plugin_2.13.12/6.2.0/chisel-plugin_2.13.12-6.2.0.jar -[debug]  -bootclasspath -[debug]  /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar -[debug]  -classpath -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar -[debug] New invalidations: -[debug] Initial set of included nodes:  -[debug] Previously invalidated, but (transitively) depend on new invalidations: -[debug] Final step, transitive dependencies: -[debug]  Set() -[debug] No classes were invalidated. -[debug] Scala compilation took 3.173580205 s -[debug] done compiling +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] No changes diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export index 3c15dcc..21cdc14 100755 --- a/target/streams/compile/exportedProducts/_global/streams/export +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/target/scala-2.13/classes +/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out index feff054..9479f4e 100755 --- a/target/streams/compile/incOptions/_global/streams/out +++ b/target/streams/compile/incOptions/_global/streams/out @@ -1,11 +1,2 @@ -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak -[debug] About to delete class files: -[debug]  Core$$anon$1.class -[debug]  Core.class -[debug] We backup class files: -[debug]  Core$$anon$1.class -[debug]  Core.class -[debug] Registering generated classes: -[debug]  Core$$anon$1.class -[debug]  Core.class -[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir index 878b1f0..18ea49d 100755 --- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -18,6 +18,9 @@ circuit TopOrigin : write-latency => 1 reader => id_rs_data_MPORT reader => id_rt_data_MPORT + reader => MPORT_1 + reader => MPORT_2 + reader => MPORT_3 writer => MPORT read-under-write => undefined reg id_reg_pc : UInt<32>, clock with : @@ -32,79 +35,90 @@ circuit TopOrigin : reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 25:33] reg exe_reg_op2_data : UInt<32>, clock with : reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 26:33] - reg exe_reg_rs_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_rs_data) @[src/main/scala/micore/Core.scala 27:32] reg exe_reg_rt_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 28:32] + reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 27:32] reg exe_reg_exe_fun : UInt<5>, clock with : - reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 29:32] + reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 28:32] reg exe_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 30:32] + reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 29:32] reg exe_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 31:31] + reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 30:31] reg exe_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 32:31] + reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 31:31] reg exe_reg_imm_i_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 33:35] + reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 32:35] reg exe_reg_imm_j : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 34:30] + reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 33:30] reg mem_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:27] + reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 36:27] reg mem_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 38:32] - reg mem_reg_alu_out : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 39:32] + reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:32] reg mem_reg_rt_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 40:32] + reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 38:32] reg mem_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 41:32] + reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 39:32] reg mem_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 42:31] + reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 40:31] reg mem_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 43:31] + reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 41:31] + reg mem_reg_alu_out : UInt<32>, clock with : + reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 42:32] reg wb_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 46:31] + reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 45:31] reg wb_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:30] + reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 46:30] reg wb_reg_wb_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 48:31] + reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:31] reg if_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 51:26] - node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 61:31] - node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 61:31] - node stall_flg = UInt<1>("h0") @[src/main/scala/micore/Core.scala 55:23 93:13] + reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 50:26] + node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 60:31] + node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 60:31] + node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 87:21] + node id_rs_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 82:33] + node _id_rs_data_hazard_T_1 = neq(id_rs_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 87:49] + node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 87:32] + node _id_rs_data_hazard_T_3 = eq(id_rs_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 87:75] + node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 87:58] + node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21] + node id_rt_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 83:33] + node _id_rt_data_hazard_T_1 = neq(id_rt_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:49] + node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32] + node _id_rt_data_hazard_T_3 = eq(id_rt_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:75] + node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:58] + node _stall_flg_T = or(id_rs_data_hazard, id_rt_data_hazard) @[src/main/scala/micore/Core.scala 90:35] + node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 54:23 90:13] node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34] - node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 58:25] - node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 191:24] - node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 191:58] - node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 191:58] - node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 192:24] - node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 192:58] - node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 192:58] - node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 193:24] - node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 193:58] - node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 194:24] - node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 194:57] - node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 195:24] - node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 195:58] - node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 196:24] - node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 196:77] - node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 196:58] - node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 199:9] - node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 200:24] - node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 200:77] - node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 200:58] - node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 204:24] - node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 204:58] - node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:84] - node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 204:65] - node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 207:10] - node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 208:24] - node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 208:58] - node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:84] - node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 208:65] - node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 209:24] + node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 231:34] + node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 231:15 57:25] + node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 198:24] + node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:58] + node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 198:58] + node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 199:24] + node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:58] + node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 199:58] + node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 200:24] + node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:58] + node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 201:24] + node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:57] + node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 202:24] + node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:58] + node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 203:24] + node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:77] + node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 203:58] + node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 206:9] + node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 207:24] + node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 207:77] + node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 207:58] + node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 211:24] + node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 211:58] + node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 211:84] + node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 211:65] + node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 214:10] + node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 215:24] + node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 215:58] + node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:84] + node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 215:65] + node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 216:24] node _exe_alu_out_T_29 = mux(_exe_alu_out_T_28, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_30 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_31 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] @@ -115,68 +129,72 @@ circuit TopOrigin : node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 188:15 59:25] + node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 195:15 58:25] node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 216:24] - node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:57] - node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 217:24] - node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:58] - node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 217:39] - node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 213:14 56:24] - node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 221:53] - node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 221:31] - node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 221:31] - node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 221:17 57:27] + node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 223:24] + node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:57] + node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 224:24] + node _exe_br_flg_T_3 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 224:57] + node _exe_br_flg_T_4 = mux(_exe_br_flg_T_2, _exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_br_flg_T_5 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 220:14 55:24] + node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 228:53] + node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 228:31] + node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 228:31] + node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 228:17 56:27] node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 73:19] - node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 77:19] + node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 72:19] + node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 76:19] node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20090000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_rs_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 83:31] - node id_rt_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 84:31] - node id_rd_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 85:31] - node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21] - node _id_rs_data_hazard_T_1 = neq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:47] - node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32] - node _id_rs_data_hazard_T_3 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:71] - node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:56] - node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 91:21] - node _id_rt_data_hazard_T_1 = neq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 91:47] - node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 91:32] - node _id_rt_data_hazard_T_3 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 91:71] - node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 91:56] - node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 96:21] - node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 96:36] - node id_inst = mux(_id_inst_T_1, UInt<32>("h20090000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8] - node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:19] - node _id_rs_data_T_1 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 102:20] - node _id_rs_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 102:60] - node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 102:41] - node _id_rs_data_T_4 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 103:20] - node _id_rs_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 103:58] - node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 103:40] - node _id_rs_data_T_7 = mux(_id_rs_data_T_6, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs_data_T_8 = mux(_id_rs_data_T_3, mem_reg_alu_out, _id_rs_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 109:19] - node _id_rt_data_T_1 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:20] - node _id_rt_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:60] - node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 110:41] - node _id_rt_data_T_4 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 111:20] - node _id_rt_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 111:58] - node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 111:40] - node _id_rt_data_T_7 = mux(_id_rt_data_T_6, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rt_data_T_8 = mux(_id_rt_data_T_3, mem_reg_alu_out, _id_rt_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 115:25] - node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 116:44] - node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 116:31] - node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 116:26] - node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 117:29] - node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 117:42] - node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 117:21] + node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 93:21] + node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 93:36] + node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 93:8] + node id_rs_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 95:27] + node id_rt_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 96:27] + node id_rd_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 97:27] + node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 103:19] + node _id_rs_data_T_1 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20] + node _id_rs_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60] + node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 104:41] + node _id_rs_data_T_4 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 105:20] + node _id_rs_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 105:60] + node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 105:41] + node _id_rs_data_T_7 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:21] + node _id_rs_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:59] + node _id_rs_data_T_9 = and(_id_rs_data_T_7, _id_rs_data_T_8) @[src/main/scala/micore/Core.scala 107:41] + node _id_rs_data_T_10 = mux(_id_rs_data_T_9, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 250:23] + node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 251:23] + node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 251:49] + node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 251:49] + node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 247:15 99:25] + node _id_rs_data_T_11 = mux(_id_rs_data_T_6, mem_wb_data, _id_rs_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rs_data_T_12 = mux(_id_rs_data_T_3, exe_alu_out, _id_rs_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:19] + node _id_rt_data_T_1 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 115:20] + node _id_rt_data_T_2 = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 115:60] + node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 115:41] + node _id_rt_data_T_4 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 116:20] + node _id_rt_data_T_5 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 116:60] + node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 116:41] + node _id_rt_data_T_7 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] + node _id_rt_data_T_8 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59] + node _id_rt_data_T_9 = and(_id_rt_data_T_7, _id_rt_data_T_8) @[src/main/scala/micore/Core.scala 118:41] + node _id_rt_data_T_10 = mux(_id_rt_data_T_9, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rt_data_T_11 = mux(_id_rt_data_T_6, mem_wb_data, _id_rt_data_T_10) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rt_data_T_12 = mux(_id_rt_data_T_3, exe_alu_out, _id_rt_data_T_11) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_12) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 123:25] + node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 124:44] + node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 124:31] + node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 124:26] + node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 125:29] + node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 125:42] + node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 125:21] node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -321,110 +339,157 @@ circuit TopOrigin : node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 150:19] - node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 151:19] + node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 158:19] + node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 159:19] node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_op1_data = mux(_id_op1_data_T, id_rs_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 158:19] - node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 159:19] - node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 160:19] + node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 166:19] + node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 167:19] + node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 168:19] node _id_op2_data_T_3 = mux(_id_op2_data_T_2, id_imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_op2_data_T_4 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_op2_data = mux(_id_op2_data_T, id_rt_data, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 173:18] - node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 173:39] - node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 176:9] - node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 173:29] - node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 177:16] - node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 177:16] + node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 180:18] + node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 180:39] + node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 183:9] + node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 180:29] + node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 184:16] + node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 184:16] node _exe_reg_wb_addr_T_6 = mux(_exe_reg_wb_addr_T_5, UInt<5>("h1f"), id_rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_reg_wb_addr_T_7 = mux(_exe_reg_wb_addr_T_3, id_rd_addr, _exe_reg_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 241:23] - node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 242:23] - node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 242:49] - node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 242:49] - node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node mem_wb_data = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 252:22] - node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:50] - node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 252:32] - node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 252:59 253:12] - node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 252:59 253:12] - node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:59 253:12 15:20] - node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 252:59 253:29] - node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 252:59 253:29] - node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 256:27] - node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 259:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 259:9] - node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 260:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 260:9] - node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 261:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:9] - node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 262:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 262:9] - node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 263:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 263:9] - node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 264:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 264:9] - node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 265:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 265:9] - node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 266:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 266:9] - node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 267:9] - node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 267:9] - node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9] - node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9] - io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 52:16] - io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16] - io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15] - io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 236:17] - io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 256:11] - regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 99:12] - regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 99:12] - regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 99:12] - regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 107:12] - regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 107:12] - regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 107:12] + node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 261:22] + node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:50] + node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 261:32] + node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 261:59 262:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 261:59 262:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:59 262:12 15:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 261:59 262:29] + node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 261:59 262:29] + node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 265:27] + node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9] + node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 269:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 269:9] + node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 270:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 270:9] + node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 271:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 271:9] + node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 272:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 272:9] + node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 273:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 273:9] + node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 274:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 274:9] + node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9] + node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9] + node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9] + node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9] + node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9] + node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] + node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] + node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] + node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] + node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] + node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] + node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] + node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] + node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] + node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] + node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] + node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] + node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9] + node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9] + node _T_39 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9] + node _T_40 = eq(_T_39, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9] + node _T_41 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9] + node _T_42 = eq(_T_41, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9] + node _T_43 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9] + node _T_44 = eq(_T_43, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9] + node _T_45 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9] + node _T_46 = eq(_T_45, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9] + node _T_47 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9] + node _T_48 = eq(_T_47, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9] + node _T_49 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9] + node _T_50 = eq(_T_49, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9] + node _T_51 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9] + node _T_52 = eq(_T_51, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9] + io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 51:16] + io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 243:16] + io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 244:15] + io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 245:17] + io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 265:11] + regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 101:12] + regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 101:12] + regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 101:12] + regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 112:12] + regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 112:12] + regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 112:12] + regfile.MPORT_1.addr <= UInt<5>("h10") @[src/main/scala/micore/Core.scala 295:36] + regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 295:36] + regfile.MPORT_1.clk <= clock @[src/main/scala/micore/Core.scala 295:36] + regfile.MPORT_2.addr <= UInt<5>("h12") @[src/main/scala/micore/Core.scala 296:36] + regfile.MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 296:36] + regfile.MPORT_2.clk <= clock @[src/main/scala/micore/Core.scala 296:36] + regfile.MPORT_3.addr <= UInt<5>("h8") @[src/main/scala/micore/Core.scala 297:36] + regfile.MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 297:36] + regfile.MPORT_3.clk <= clock @[src/main/scala/micore/Core.scala 297:36] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 73:13] - id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 74:15] - exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 165:14 23:{27,27}] - exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 170:19 24:{32,32}] - exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 166:20 25:{33,33}] - exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 167:20 26:{33,33}] - exe_reg_rs_data <= mux(reset, UInt<32>("h0"), id_rs_data) @[src/main/scala/micore/Core.scala 168:19 27:{32,32}] - exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 169:19 28:{32,32}] - exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 185:19 29:{32,32}] - exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 181:19 30:{32,32}] - exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 182:18 31:{31,31}] - exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 180:18 32:{31,31}] - exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 183:22 33:{35,35}] - exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 184:17 34:{30,30}] - mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 225:14 37:{27,27}] - mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 226:19 38:{32,32}] - mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 227:19 39:{32,32}] - mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 228:19 40:{32,32}] - mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 229:19 41:{32,32}] - mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 230:18 42:{31,31}] - mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 231:18 43:{31,31}] - wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 247:18 46:{31,31}] - wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 248:17 47:{30,30}] - wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 249:18 48:{31,31}] - if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 51:{26,26} 70:13] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 259:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 260:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 261:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 262:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_4 @[src/main/scala/micore/Core.scala 263:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_5 @[src/main/scala/micore/Core.scala 264:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_6 @[src/main/scala/micore/Core.scala 265:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_7 @[src/main/scala/micore/Core.scala 266:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_8 @[src/main/scala/micore/Core.scala 267:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "---------------\n") : printf_9 @[src/main/scala/micore/Core.scala 268:9] + id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 72:13] + id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 73:15] + exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 173:14 23:{27,27}] + exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 177:19 24:{32,32}] + exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 174:20 25:{33,33}] + exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 175:20 26:{33,33}] + exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 176:19 27:{32,32}] + exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 192:19 28:{32,32}] + exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 188:19 29:{32,32}] + exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 189:18 30:{31,31}] + exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 187:18 31:{31,31}] + exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 190:22 32:{35,35}] + exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 191:17 33:{30,30}] + mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 234:14 36:{27,27}] + mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 236:19 37:{32,32}] + mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 235:19 38:{32,32}] + mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 240:19 39:{32,32}] + mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 238:18 40:{31,31}] + mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 239:18 41:{31,31}] + mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 237:19 42:{32,32}] + wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 258:18 45:{31,31}] + wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 257:17 46:{30,30}] + wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 256:18 47:{31,31}] + if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 50:{26,26} 69:13] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 268:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/micore/Core.scala 269:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 270:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_3 @[src/main/scala/micore/Core.scala 271:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_4 @[src/main/scala/micore/Core.scala 272:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_5 @[src/main/scala/micore/Core.scala 273:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs_data: 0x%x\n", id_rs_data) : printf_6 @[src/main/scala/micore/Core.scala 274:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_rt_data: 0x%x\n", id_rt_data) : printf_7 @[src/main/scala/micore/Core.scala 275:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_rs_addr: 0x%x\n", id_rs_addr) : printf_8 @[src/main/scala/micore/Core.scala 276:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_rt_addr: 0x%x\n", id_rt_addr) : printf_9 @[src/main/scala/micore/Core.scala 277:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "id_rd_addr: 0x%x\n", id_rd_addr) : printf_10 @[src/main/scala/micore/Core.scala 278:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "stall_flg: 0x%x\n", stall_flg) : printf_11 @[src/main/scala/micore/Core.scala 284:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_12 @[src/main/scala/micore/Core.scala 285:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", exe_reg_op1_data) : printf_13 @[src/main/scala/micore/Core.scala 286:9] + printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", exe_reg_op2_data) : printf_14 @[src/main/scala/micore/Core.scala 287:9] + printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_15 @[src/main/scala/micore/Core.scala 288:9] + printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "exe_reg_wb_addr: 0x%x\n", exe_reg_wb_addr) : printf_16 @[src/main/scala/micore/Core.scala 290:9] + printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_17 @[src/main/scala/micore/Core.scala 291:9] + printf(clock, and(and(UInt<1>("h1"), _T_40), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_18 @[src/main/scala/micore/Core.scala 292:9] + printf(clock, and(and(UInt<1>("h1"), _T_42), UInt<1>("h1")), "wb_reg_wb_addr: 0x%x\n", wb_reg_wb_addr) : printf_19 @[src/main/scala/micore/Core.scala 293:9] + printf(clock, and(and(UInt<1>("h1"), _T_44), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_20 @[src/main/scala/micore/Core.scala 294:9] + printf(clock, and(and(UInt<1>("h1"), _T_46), UInt<1>("h1")), "regfile s0: 0x%d\n", regfile.MPORT_1.data) : printf_21 @[src/main/scala/micore/Core.scala 295:9] + printf(clock, and(and(UInt<1>("h1"), _T_48), UInt<1>("h1")), "regfile s2: 0x%d\n", regfile.MPORT_2.data) : printf_22 @[src/main/scala/micore/Core.scala 296:9] + printf(clock, and(and(UInt<1>("h1"), _T_50), UInt<1>("h1")), "regfile t0: 0x%d\n", regfile.MPORT_3.data) : printf_23 @[src/main/scala/micore/Core.scala 297:9] + printf(clock, and(and(UInt<1>("h1"), _T_52), UInt<1>("h1")), "---------------\n") : printf_24 @[src/main/scala/micore/Core.scala 298:9] module Memory : @[src/main/scala/micore/Memory.scala 20:7] input clock : Clock @[src/main/scala/micore/Memory.scala 20:7]