diff --git a/TopOrigin.sv b/TopOrigin.sv index 002ff0d..9c46214 100755 --- a/TopOrigin.sv +++ b/TopOrigin.sv @@ -20,10 +20,6 @@ module regfile_32x32( input R1_en, R1_clk, output [31:0] R1_data, - input [4:0] R2_addr, - input R2_en, - R2_clk, - output [31:0] R2_data, input [4:0] W0_addr, input W0_en, W0_clk, @@ -37,7 +33,6 @@ module regfile_32x32( end // always @(posedge) assign R0_data = R0_en ? Memory[R0_addr] : 32'bx; assign R1_data = R1_en ? Memory[R1_addr] : 32'bx; - assign R2_data = R2_en ? Memory[R2_addr] : 32'bx; endmodule module Core( @@ -49,83 +44,73 @@ module Core( input [31:0] io_dmem_rdata, output io_dmem_wen, output [31:0] io_dmem_wdata, - output io_exit, - output [31:0] io_gp + output io_exit ); - wire [31:0] mem_wb_data; - wire exe_jmp_flg; - wire exe_br_flg; + wire [31:0] _regfile_ext_R0_data; wire [31:0] _regfile_ext_R1_data; - wire [31:0] _regfile_ext_R2_data; - reg [31:0] id_reg_pc; - reg [31:0] id_reg_inst; - reg [31:0] exe_reg_pc; - reg [4:0] exe_reg_wb_addr; - reg [31:0] exe_reg_op1_data; - reg [31:0] exe_reg_op2_data; - reg [31:0] exe_reg_rs2_data; - reg [4:0] exe_reg_exe_fun; - reg [1:0] exe_reg_mem_wen; - reg [1:0] exe_reg_rf_wen; - reg [2:0] exe_reg_wb_sel; - reg [31:0] exe_reg_imm_b_sext; - reg [31:0] mem_reg_pc; - reg [4:0] mem_reg_wb_addr; - reg [31:0] mem_reg_rs2_data; - reg [1:0] mem_reg_mem_wen; - reg [1:0] mem_reg_rf_wen; - reg [2:0] mem_reg_wb_sel; - reg [31:0] mem_reg_alu_out; - reg [4:0] wb_reg_wb_addr; - reg [1:0] wb_reg_rf_wen; - reg [31:0] wb_reg_wb_data; - reg [31:0] if_reg_pc; - wire _id_inst_T = exe_br_flg | exe_jmp_flg; - wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; - wire stall_flg = - _id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) - & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T - & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; - wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; - wire _id_rs1_data_T = id_inst[25:21] == 5'h0; - wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; - wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2; - wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; - wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5; - wire [31:0] id_rs2_data = - id_inst[20:16] == 5'h0 - ? 32'h0 - : id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 - ? mem_wb_data - : id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 - ? wb_reg_wb_data - : _regfile_ext_R1_data; - wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; - wire _csignals_T_5 = _GEN == 17'h20; - wire _csignals_T_7 = id_inst[31:28] == 4'h8; - wire _csignals_T_9 = _GEN == 17'h22; - wire _csignals_T_11 = _GEN == 17'h24; - wire _csignals_T_13 = _GEN == 17'h25; - wire _csignals_T_15 = _GEN == 17'h26; - wire _csignals_T_17 = id_inst[31:28] == 4'hC; - wire _csignals_T_19 = id_inst[31:28] == 4'hD; - wire _csignals_T_21 = _GEN == 17'h2A; - wire _csignals_T_23 = id_inst[31:28] == 4'h4; - wire _csignals_T_25 = id_inst[31:28] == 4'h5; - wire _csignals_T_27 = id_inst[31:28] == 4'h3; - wire _csignals_T_29 = id_inst[31:23] == 9'h1E0; - wire _GEN_0 = _csignals_T_27 | _csignals_T_29; - wire [4:0] _csignals_T_31 = {4'h0, _GEN_0}; - wire _GEN_1 = _csignals_T_5 | _csignals_T_7; - wire _GEN_2 = _csignals_T_23 | _csignals_T_25; - wire _GEN_3 = _csignals_T_21 | _GEN_2; + reg [31:0] pc_reg; + wire [31:0] _pc_plus4_T = pc_reg + 32'h4; + wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]}; + wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8; + wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0; + wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0; + wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]}; + wire _csignals_T_5 = _GEN_0 == 12'h20; + wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8; + wire _csignals_T_9 = _GEN_0 == 12'h22; + wire _csignals_T_11 = _GEN_0 == 12'h24; + wire _csignals_T_13 = _GEN_0 == 12'h25; + wire _csignals_T_15 = _GEN_0 == 12'h26; + wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC; + wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD; + wire _csignals_T_21 = _GEN_0 == 12'h2A; + wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4; + wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5; + wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]}; + wire _csignals_T_27 = _GEN_1 == 17'h0; + wire _csignals_T_29 = _GEN_1 == 17'h2; + wire _csignals_T_31 = _GEN_1 == 17'h3; + wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3; + wire _csignals_T_35 = _GEN == 10'h8; + wire [4:0] csignals_0 = + _csignals_T_5 | _csignals_T_7 + ? 5'h1 + : _csignals_T_9 + ? 5'h2 + : _csignals_T_11 + ? 5'h3 + : _csignals_T_13 + ? 5'h4 + : _csignals_T_15 + ? 5'h5 + : _csignals_T_17 + ? 5'h3 + : _csignals_T_19 + ? 5'h4 + : _csignals_T_21 + ? 5'h9 + : _csignals_T_23 + ? 5'hB + : _csignals_T_25 + ? 5'hC + : _csignals_T_27 + ? 5'h6 + : _csignals_T_29 + ? 5'h7 + : _csignals_T_31 + ? 5'h8 + : _csignals_T_33 + ? 5'h1 + : _csignals_T_35 ? 5'hD : 5'h0; + wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31; + wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2; wire [1:0] csignals_1 = _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 + | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33 ? 2'h1 - : _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29}; - wire [2:0] _csignals_T_70 = + : 2'h2; + wire [2:0] _csignals_T_85 = _csignals_T_5 ? 3'h1 : _csignals_T_7 @@ -134,254 +119,140 @@ module Core( ? 3'h1 : _csignals_T_17 | _csignals_T_19 ? 3'h2 - : _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1}; - wire [1:0] _csignals_T_87 = {1'h0, _GEN_0}; - wire _GEN_4 = + : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35}; + wire _GEN_4 = _csignals_T_23 | _csignals_T_25; + wire _GEN_5 = _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21; - wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29}; - wire _id_op1_data_T = csignals_1 == 2'h1; - wire _id_op1_data_T_1 = csignals_1 == 2'h2; - wire [35:0] id_op2_data = - _csignals_T_70 == 3'h1 - ? {4'h0, id_rs2_data} - : _csignals_T_70 == 3'h2 - ? {4'h0, {16{id_inst[15]}}, id_inst[15:0]} - : _csignals_T_70 == 3'h3 - ? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]} - : _csignals_T_70 == 3'h4 - ? {{6{id_inst[23]}}, id_inst[25:0], 4'h0} - : {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0}; - wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data; - wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; - wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]}; - wire [31:0] _exe_alu_out_T_46 = - exe_reg_exe_fun == 5'h1 - ? _exe_alu_out_T_30 - : exe_reg_exe_fun == 5'h2 - ? exe_reg_op1_data - exe_reg_op2_data - : exe_reg_exe_fun == 5'h3 - ? exe_reg_op1_data & exe_reg_op2_data - : exe_reg_exe_fun == 5'h4 - ? exe_reg_op1_data | exe_reg_op2_data - : exe_reg_exe_fun == 5'h5 - ? exe_reg_op1_data ^ exe_reg_op2_data - : exe_reg_exe_fun == 5'h6 - ? _exe_alu_out_T_14[31:0] - : exe_reg_exe_fun == 5'h7 - ? exe_reg_op1_data >> _GEN_5 - : exe_reg_exe_fun == 5'h8 - ? $signed($signed(exe_reg_op1_data) >>> _GEN_5) - : exe_reg_exe_fun == 5'h9 - ? {31'h0, - $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} - : exe_reg_exe_fun == 5'hA - ? {31'h0, exe_reg_op1_data < exe_reg_op2_data} - : exe_reg_exe_fun == 5'h11 - ? _exe_alu_out_T_30 & 32'hFFFFFFFE - : exe_reg_exe_fun == 5'h12 - ? exe_reg_op1_data - : 32'h0; - wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data; - assign exe_br_flg = - exe_reg_exe_fun == 5'hB - ? _exe_br_flg_T_3 - : exe_reg_exe_fun == 5'hC & ~_exe_br_flg_T_3; - assign exe_jmp_flg = exe_reg_wb_sel == 3'h3; - assign mem_wb_data = - mem_reg_wb_sel == 3'h2 - ? io_dmem_rdata - : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out; + wire [1:0] _csignals_T_136 = + _GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}}; + wire _op1_data_T = csignals_1 == 2'h1; + wire _op1_data_T_1 = csignals_1 == 2'h2; + wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0; + wire [31:0] op2_data = + _csignals_T_85 == 3'h1 + ? rt_data + : _csignals_T_85 == 3'h2 + ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]} + : _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0; + wire _alu_out_T = csignals_0 == 5'h1; + wire [31:0] _alu_out_T_1 = op1_data + op2_data; + wire _alu_out_T_3 = csignals_0 == 5'h2; + wire [31:0] _alu_out_T_4 = op1_data - op2_data; + wire _alu_out_T_6 = csignals_0 == 5'h3; + wire [31:0] _alu_out_T_7 = op1_data & op2_data; + wire _alu_out_T_8 = csignals_0 == 5'h4; + wire [31:0] _alu_out_T_9 = op1_data | op2_data; + wire _alu_out_T_10 = csignals_0 == 5'h5; + wire [31:0] _alu_out_T_11 = op1_data ^ op2_data; + wire _alu_out_T_12 = csignals_0 == 5'h6; + wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0]; + wire _alu_out_T_16 = csignals_0 == 5'h7; + wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]}; + wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6; + wire _alu_out_T_19 = csignals_0 == 5'h8; + wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6); + wire _alu_out_T_24 = csignals_0 == 5'h9; + wire _alu_out_T_28 = csignals_0 == 5'hD; + wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)}; + wire [31:0] alu_out = + _alu_out_T + ? _alu_out_T_1 + : _alu_out_T_3 + ? _alu_out_T_4 + : _alu_out_T_6 + ? _alu_out_T_7 + : _alu_out_T_8 + ? _alu_out_T_9 + : _alu_out_T_10 + ? _alu_out_T_11 + : _alu_out_T_12 + ? _alu_out_T_14[31:0] + : _alu_out_T_16 + ? _alu_out_T_18 + : _alu_out_T_19 + ? _alu_out_T_22 + : _alu_out_T_24 + ? _GEN_7 + : _alu_out_T_28 ? op1_data : 32'h0; + wire _br_flg_T_3 = op1_data == op2_data; + wire br_flg = + csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3; + wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg; + wire [31:0] wb_data = + _csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out; `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset) begin - automatic logic [31:0] id_rs1_data = - _id_rs1_data_T - ? 32'h0 - : _id_rs1_data_T_3 - ? mem_wb_data - : _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data; - $fwrite(32'h80000002, "---------------------\n"); - $fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc); - $fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst); - $fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst); - $fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]); - $fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]); - $fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]); - $fwrite(32'h80000002, "id_exe_fun: 0x%x\n", - _GEN_1 - ? 5'h1 - : _csignals_T_9 - ? 5'h2 - : _csignals_T_11 - ? 5'h3 - : _csignals_T_13 - ? 5'h4 - : _csignals_T_15 - ? 5'h5 - : _csignals_T_17 - ? 5'h3 - : _csignals_T_19 - ? 5'h4 - : _csignals_T_21 - ? 5'h9 - : _csignals_T_23 - ? 5'hB - : _csignals_T_25 - ? 5'hC - : _csignals_T_31); - $fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1); - $fwrite(32'h80000002, "id_op1_data: 0x%x\n", - _id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0); - $fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70); - $fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data); - $fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0); - $fwrite(32'h80000002, "id_rf_wen: 0x%x\n", - _GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87); - $fwrite(32'h80000002, "id_wb_sel: 0x%x\n", - _GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100); - $fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data); - $fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data); - $fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46); - $fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc); - $fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out); - $fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data); - $fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data); - $fwrite(32'h80000002, "---------------------\n"); + $fwrite(32'h80000002, "---------------\n"); + $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst); + $fwrite(32'h80000002, "pc_next: 0x%x\n", + br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T); + $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]); + $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]); + $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data); + $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data); + $fwrite(32'h80000002, "---------------\n"); end end // always @(posedge) `endif // not def SYNTHESIS always @(posedge clock) begin - if (reset) begin - id_reg_pc <= 32'h0; - id_reg_inst <= 32'h0; - exe_reg_pc <= 32'h0; - exe_reg_wb_addr <= 5'h0; - exe_reg_op1_data <= 32'h0; - exe_reg_op2_data <= 32'h0; - exe_reg_rs2_data <= 32'h0; - exe_reg_exe_fun <= 5'h0; - exe_reg_mem_wen <= 2'h0; - exe_reg_rf_wen <= 2'h0; - exe_reg_wb_sel <= 3'h0; - exe_reg_imm_b_sext <= 32'h0; - mem_reg_pc <= 32'h0; - mem_reg_wb_addr <= 5'h0; - mem_reg_rs2_data <= 32'h0; - mem_reg_mem_wen <= 2'h0; - mem_reg_rf_wen <= 2'h0; - mem_reg_wb_sel <= 3'h0; - mem_reg_alu_out <= 32'h0; - wb_reg_wb_addr <= 5'h0; - wb_reg_rf_wen <= 2'h0; - wb_reg_wb_data <= 32'h0; - if_reg_pc <= 32'h400000; - end - else begin - if (~stall_flg) - id_reg_pc <= if_reg_pc; - if (_id_inst_T) - id_reg_inst <= 32'h0; - else if (~stall_flg) - id_reg_inst <= io_imem_inst; - exe_reg_pc <= id_reg_pc; - exe_reg_wb_addr <= id_inst[15:11]; - if (_id_op1_data_T) begin - if (_id_rs1_data_T) - exe_reg_op1_data <= 32'h0; - else if (_id_rs1_data_T_3) - exe_reg_op1_data <= mem_wb_data; - else if (_id_rs1_data_T_6) - exe_reg_op1_data <= wb_reg_wb_data; - else - exe_reg_op1_data <= _regfile_ext_R2_data; + if (reset) + pc_reg <= 32'h0; + else if (br_flg) + pc_reg <= br_target; + else if (jmp_flg) begin + if (_alu_out_T) + pc_reg <= _alu_out_T_1; + else if (_alu_out_T_3) + pc_reg <= _alu_out_T_4; + else if (_alu_out_T_6) + pc_reg <= _alu_out_T_7; + else if (_alu_out_T_8) + pc_reg <= _alu_out_T_9; + else if (_alu_out_T_10) + pc_reg <= _alu_out_T_11; + else if (_alu_out_T_12) + pc_reg <= _alu_out_T_14[31:0]; + else if (_alu_out_T_16) + pc_reg <= _alu_out_T_18; + else if (_alu_out_T_19) + pc_reg <= _alu_out_T_22; + else if (_alu_out_T_24) + pc_reg <= _GEN_7; + else if (_alu_out_T_28) begin + if (_op1_data_T) + pc_reg <= rs_data; + else if (~_op1_data_T_1) + pc_reg <= 32'h0; end - else if (_id_op1_data_T_1) - exe_reg_op1_data <= id_reg_pc; else - exe_reg_op1_data <= 32'h0; - exe_reg_op2_data <= id_op2_data[31:0]; - exe_reg_rs2_data <= id_rs2_data; - if (_GEN_1) - exe_reg_exe_fun <= 5'h1; - else if (_csignals_T_9) - exe_reg_exe_fun <= 5'h2; - else if (_csignals_T_11) - exe_reg_exe_fun <= 5'h3; - else if (_csignals_T_13) - exe_reg_exe_fun <= 5'h4; - else if (_csignals_T_15) - exe_reg_exe_fun <= 5'h5; - else if (_csignals_T_17) - exe_reg_exe_fun <= 5'h3; - else if (_csignals_T_19) - exe_reg_exe_fun <= 5'h4; - else if (_csignals_T_21) - exe_reg_exe_fun <= 5'h9; - else if (_csignals_T_23) - exe_reg_exe_fun <= 5'hB; - else if (_csignals_T_25) - exe_reg_exe_fun <= 5'hC; - else - exe_reg_exe_fun <= _csignals_T_31; - exe_reg_mem_wen <= 2'h0; - if (_GEN_4) begin - exe_reg_rf_wen <= 2'h1; - exe_reg_wb_sel <= 3'h1; - end - else if (_GEN_2) begin - exe_reg_rf_wen <= 2'h0; - exe_reg_wb_sel <= 3'h0; - end - else begin - exe_reg_rf_wen <= _csignals_T_87; - if (_csignals_T_27) - exe_reg_wb_sel <= 3'h3; - else - exe_reg_wb_sel <= _csignals_T_100; - end - exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0}; - mem_reg_pc <= exe_reg_pc; - mem_reg_wb_addr <= exe_reg_wb_addr; - mem_reg_rs2_data <= exe_reg_rs2_data; - mem_reg_mem_wen <= exe_reg_mem_wen; - mem_reg_rf_wen <= exe_reg_rf_wen; - mem_reg_wb_sel <= exe_reg_wb_sel; - mem_reg_alu_out <= _exe_alu_out_T_46; - wb_reg_wb_addr <= mem_reg_wb_addr; - wb_reg_rf_wen <= mem_reg_rf_wen; - wb_reg_wb_data <= mem_wb_data; - if (exe_br_flg) - if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; - else if (exe_jmp_flg) - if_reg_pc <= _exe_alu_out_T_46; - else if (~stall_flg) - if_reg_pc <= if_reg_pc + 32'h4; + pc_reg <= 32'h0; end + else + pc_reg <= _pc_plus4_T; end // always @(posedge) regfile_32x32 regfile_ext ( - .R0_addr (5'h3), + .R0_addr (io_imem_inst[20:16]), .R0_en (1'h1), .R0_clk (clock), - .R0_data (io_gp), - .R1_addr (id_inst[20:16]), + .R0_data (_regfile_ext_R0_data), + .R1_addr (io_imem_inst[25:21]), .R1_en (1'h1), .R1_clk (clock), .R1_data (_regfile_ext_R1_data), - .R2_addr (id_inst[25:21]), - .R2_en (1'h1), - .R2_clk (clock), - .R2_data (_regfile_ext_R2_data), - .W0_addr (wb_reg_wb_addr), - .W0_en (_id_rs2_data_T_5), + .W0_addr (io_imem_inst[15:11]), + .W0_en + (_GEN_5 | ~_GEN_4 + & (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)), .W0_clk (clock), - .W0_data (wb_reg_wb_data) + .W0_data (wb_data) ); - assign io_imem_addr = if_reg_pc; - assign io_dmem_addr = mem_reg_alu_out; - assign io_dmem_wen = mem_reg_mem_wen[0]; - assign io_dmem_wdata = mem_reg_rs2_data; - assign io_exit = id_reg_inst == 32'h114514; + assign io_imem_addr = pc_reg; + assign io_dmem_addr = alu_out; + assign io_dmem_wen = 1'h0; + assign io_dmem_wdata = rt_data; + assign io_exit = io_imem_inst == 32'h114514; endmodule // VCS coverage exclude_file @@ -449,7 +320,7 @@ module mem_4096x8( end // always @(posedge) `ifdef ENABLE_INITIAL_MEM_ initial - $readmemh("src/hex/mem.hex", Memory); + $readmemh("src/hex/addi.hex", Memory); `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; @@ -539,10 +410,9 @@ module Memory( endmodule module TopOrigin( - input clock, - reset, - output io_exit, - output [31:0] io_gp + input clock, + reset, + output io_exit ); wire [31:0] _memory_io_imem_inst; @@ -560,8 +430,7 @@ module TopOrigin( .io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_wen (_core_io_dmem_wen), .io_dmem_wdata (_core_io_dmem_wdata), - .io_exit (io_exit), - .io_gp (io_gp) + .io_exit (io_exit) ); Memory memory ( .clock (clock), diff --git a/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource b/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource new file mode 100755 index 0000000..9d348e7 --- /dev/null +++ b/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs new file mode 100755 index 0000000..fd70f3c --- /dev/null +++ b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs @@ -0,0 +1 @@ +-2109952146 \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output new file mode 100755 index 0000000..5cdd450 --- /dev/null +++ b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/project/project/project/target/streams/_global/_global/_global/streams/out b/project/project/project/target/streams/_global/_global/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/csrConfiguration/_global/streams/out b/project/project/project/target/streams/_global/csrConfiguration/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/csrProject/_global/streams/out b/project/project/project/target/streams/_global/csrProject/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp new file mode 100755 index 0000000..c09d4f8 --- /dev/null +++ b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp @@ -0,0 +1 @@ +-2132504562 \ No newline at end of file diff --git a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp new file mode 100755 index 0000000..7a9f043 --- /dev/null +++ b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp @@ -0,0 +1 @@ +{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":3342},"type":"LinePosition"}} \ No newline at end of file diff --git a/project/project/project/target/streams/_global/ivyConfiguration/_global/streams/out b/project/project/project/target/streams/_global/ivyConfiguration/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/ivySbt/_global/streams/out b/project/project/project/target/streams/_global/ivySbt/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/moduleSettings/_global/streams/out b/project/project/project/target/streams/_global/moduleSettings/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/projectDescriptors/_global/streams/out b/project/project/project/target/streams/_global/projectDescriptors/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/_global/update/_global/streams/out b/project/project/project/target/streams/_global/update/_global/streams/out new file mode 100755 index 0000000..982166c --- /dev/null +++ b/project/project/project/target/streams/_global/update/_global/streams/out @@ -0,0 +1,3 @@ +[debug] not up to date. inChanged = true, force = false +[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")... +[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build") diff --git a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100755 index 0000000..d3be71e --- /dev/null +++ b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100755 index 0000000..0637a08 --- /dev/null +++ b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/project/target/streams/compile/bspReporter/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compile/_global/streams/out b/project/project/project/target/streams/compile/compile/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100755 index 0000000..9cca155 --- /dev/null +++ b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1,6 @@ +[debug] [zinc] IncrementalCompile ----------- +[debug] IncrementalCompile.incrementalCompile +[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries +[debug] current source = Set() +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/project/target/streams/compile/copyResources/_global/streams/out new file mode 100755 index 0000000..f25042f --- /dev/null +++ b/project/project/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ 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diff --git a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100755 index 0000000..8d01fa8 --- /dev/null +++ b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/project/target/streams/compile/incOptions/_global/streams/out new file mode 100755 index 0000000..7231079 --- /dev/null +++ b/project/project/project/target/streams/compile/incOptions/_global/streams/out @@ -0,0 +1,5 @@ +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] About to delete class files: +[debug] We backup class files: +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/project/target/streams/compile/scalacOptions/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..3f98510 --- /dev/null +++ b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100755 index 0000000..8d01fa8 --- /dev/null +++ b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..bbd3b52 --- /dev/null +++ b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export new file mode 100755 index 0000000..3f98510 --- /dev/null +++ b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..8d01fa8 --- /dev/null +++ b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100755 index 0000000..bbd3b52 --- /dev/null +++ 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a/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/_global/update/_global/streams/out b/project/project/target/streams/_global/update/_global/streams/out new file mode 100755 index 0000000..587fe53 --- /dev/null +++ b/project/project/target/streams/_global/update/_global/streams/out @@ -0,0 +1,3 @@ +[debug] not up to date. inChanged = true, force = false +[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")... +[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build") diff --git a/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100755 index 0000000..29633ad --- /dev/null +++ b/project/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100755 index 0000000..0637a08 --- /dev/null +++ b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/target/streams/compile/bspReporter/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compile/_global/streams/out b/project/project/target/streams/compile/compile/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100755 index 0000000..9cca155 --- /dev/null +++ b/project/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1,6 @@ +[debug] [zinc] IncrementalCompile ----------- +[debug] IncrementalCompile.incrementalCompile +[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries +[debug] current source = Set() +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/target/streams/compile/copyResources/_global/streams/out new file mode 100755 index 0000000..f25042f --- /dev/null +++ b/project/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100755 index 0000000..454272b --- /dev/null +++ b/project/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/target/streams/compile/incOptions/_global/streams/out new file mode 100755 index 0000000..66abc73 --- /dev/null +++ b/project/project/target/streams/compile/incOptions/_global/streams/out @@ -0,0 +1,5 @@ +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] About to delete class files: +[debug] We backup class files: +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100755 index 0000000..b1694c2 --- /dev/null +++ b/project/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/target/streams/compile/scalacOptions/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100755 index 0000000..4c93399 --- /dev/null +++ b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100755 index 0000000..454272b --- /dev/null +++ b/project/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..bbd3b52 --- /dev/null +++ b/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/target/streams/runtime/fullClasspath/_global/streams/export new file mode 100755 index 0000000..4c93399 --- /dev/null +++ b/project/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export new file mode 100755 index 0000000..454272b --- /dev/null +++ b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/project/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100755 index 0000000..bbd3b52 --- /dev/null +++ b/project/project/target/streams/runtime/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/out new file mode 100755 index 0000000..e69de29 diff --git a/project/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/project/target/streams/runtime/unmanagedJars/_global/streams/export new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/project/project/target/streams/runtime/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/config-classes/$92eace74df3dd60b2407.cache b/project/target/config-classes/$2b8c65d0a3a3f42e1015.cache old mode 100644 new mode 100755 similarity index 100% rename from project/target/config-classes/$92eace74df3dd60b2407.cache rename to project/target/config-classes/$2b8c65d0a3a3f42e1015.cache diff --git a/project/target/config-classes/$87709882d327edfdfbe4.cache b/project/target/config-classes/$948efd6ee3ba8f09824e.cache old mode 100644 new mode 100755 similarity index 100% rename from project/target/config-classes/$87709882d327edfdfbe4.cache rename to project/target/config-classes/$948efd6ee3ba8f09824e.cache diff --git a/project/target/config-classes/$b99baa0e80f987ddc888.cache b/project/target/config-classes/$add241eb0c1a6339f011.cache old mode 100644 new mode 100755 similarity index 100% rename from project/target/config-classes/$b99baa0e80f987ddc888.cache rename to project/target/config-classes/$add241eb0c1a6339f011.cache diff --git a/project/target/config-classes/$bc99ac17cdce7fb9c74c.cache b/project/target/config-classes/$eac2b8278586e49cb092.cache old mode 100644 new mode 100755 similarity index 100% rename from project/target/config-classes/$bc99ac17cdce7fb9c74c.cache rename to project/target/config-classes/$eac2b8278586e49cb092.cache diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp index 93fa874..00763b6 100755 --- a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp @@ -1 +1 @@ -{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} \ No newline at end of file +{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous index 3cd4ba7..3f53060 100755 --- a/project/target/streams/compile/_global/_global/compileOutputs/previous +++ b/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export index faf6770..4006493 100755 --- a/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out index 96aaeb5..44649e0 100755 --- a/project/target/streams/compile/incOptions/_global/streams/out +++ b/project/target/streams/compile/incOptions/_global/streams/out @@ -1,5 +1,5 @@ -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] About to delete class files: [debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export index 69ab39c..f810de7 100755 --- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export index faf6770..4006493 100755 --- a/project/target/streams/runtime/exportedProducts/_global/streams/export +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export index 69ab39c..f810de7 100755 --- a/project/target/streams/runtime/fullClasspath/_global/streams/export +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export index faf6770..4006493 100755 --- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes +/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/src/hex/addi.hex b/src/hex/addi.hex new file mode 100755 index 0000000..8e887b9 --- /dev/null +++ b/src/hex/addi.hex @@ -0,0 +1,8 @@ +10 +00 +09 +20 +14 +45 +11 +00 diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala index 162c274..893ffc1 100755 --- a/src/main/scala/common/Consts.scala +++ b/src/main/scala/common/Consts.scala @@ -6,9 +6,9 @@ import chisel3.util._ object Consts { // 数据宽度和地址 val WORD_LEN = 32 // 指令和数据的宽度为32位 - val START_ADDR = 0x00400000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000 - val BUBBLE = 0x00000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] - val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令 [NOP] + val START_ADDR = 0x00000000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000 + val BUBBLE = 0x20000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] + val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令 // 寄存器地址长度 val ADDR_LEN = 5 // rs、rt和rd的地址宽度为5位 @@ -28,8 +28,8 @@ object Consts { val ALU_SLTU = 10.U(EXE_FUN_LEN.W) // 无符号比较小于操作 val BR_BEQ = 11.U(EXE_FUN_LEN.W) // 分支相等 val BR_BNE = 12.U(EXE_FUN_LEN.W) // 分支不等 - val ALU_JALR = 13.U(EXE_FUN_LEN.W) // JALR跳转（MIPS中没有JALR，但可以模拟） - val ALU_COPY1 = 14.U(EXE_FUN_LEN.W) // 复制操作 + // val ALU_JALR = 13.U(EXE_FUN_LEN.W) // JALR跳转（MIPS中没有JALR，但可以模拟） + val ALU_COPY1 = 13.U(EXE_FUN_LEN.W) // 复制操作 // 操作数选择 val OP1_LEN = 2 // 操作数1的选择宽度为2位 diff --git a/src/main/scala/common/Instructions.scala b/src/main/scala/common/Instructions.scala index 2e1a83d..8bd1912 100755 --- a/src/main/scala/common/Instructions.scala +++ b/src/main/scala/common/Instructions.scala @@ -9,16 +9,16 @@ object Instructions { val SW = BitPat("b101011????????????????????????????") // sw rt, offset(rs) // * 算术运算 - val ADD = BitPat("b000000???????????????00000100000") // add rd, rs, rt + val ADD = BitPat("b000000????????????????????100000") // add rd, rs, rt val ADDI = BitPat( "b001000????????????????????????????" ) // addi rt, rs, immediate - val SUB = BitPat("b000000???????????????00000100010") // sub rd, rs, rt + val SUB = BitPat("b000000????????????????????100010") // sub rd, rs, rt // * 逻辑运算 - val AND = BitPat("b000000???????????????00000100100") // and rd, rs, rt - val OR = BitPat("b000000???????????????00000100101") // or rd, rs, rt - val XOR = BitPat("b000000???????????????00000100110") // xor rd, rs, rt + val AND = BitPat("b000000????????????????????100100") // and rd, rs, rt + val OR = BitPat("b000000????????????????????100101") // or rd, rs, rt + val XOR = BitPat("b000000????????????????????100110") // xor rd, rs, rt val ANDI = BitPat( "b001100????????????????????????????" ) // andi rt, rs, immediate @@ -27,7 +27,7 @@ object Instructions { ) // ori rt, rs, immediate // * 比较 - val SLT = BitPat("b000000???????????????00000101010") // slt rd, rs, rt + val SLT = BitPat("b000000????????????????????101010") // slt rd, rs, rt // * 条件分支 val BEQ = BitPat("b000100????????????????????????????") // beq rs, rt, offset @@ -39,12 +39,9 @@ object Instructions { val SRA = BitPat("b00000000000???????????????000011") // sra rd, rt, shamt // * 跳转 - val JR = BitPat("b000000????????????0000000000001000") // jr rs + val JR = BitPat("b000000??????????????????????001000") // jr rs val JAL = BitPat("b000011????????????????????????????") // jal target - // * 立即数加载 - val LUI = BitPat("b00111100000???????????????????????") // lui rt, immediate - // * NOP - val NOP = BitPat("b00000000000000000000000000000000") // nop (sll $0, $0, 0) + val NOP = BitPat("b00100000000000000000000000000000") // nop (addi $0, $0, 0) } diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala index 5b0971f..2bf205e 100755 --- a/src/main/scala/micore/Core.scala +++ b/src/main/scala/micore/Core.scala @@ -33,7 +33,6 @@ class Core extends Module { val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W)) val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W)) val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W)) - val exe_reg_imm_z_uext = RegInit(0.U(WORD_LEN.W)) // EX/MEM state val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) @@ -43,7 +42,6 @@ class Core extends Module { val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) - val mem_reg_imm_z_uext = RegInit(0.U(WORD_LEN.W)) val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) // MEM/WB state @@ -157,8 +155,8 @@ class Core extends Module { SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), JR -> List(ALU_X, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X), JAL -> List(ALU_X, OP1_PC, OP2_X, MEN_X, REN_X, WB_X), - LUI -> List(ALU_X, OP1_X, OP2_IMU, MEN_X, REN_X, WB_ALU), NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X) + // LUI -> List(ALU_X, OP1_X, OP2_IMU, MEN_X, REN_X, WB_ALU), ) ) @@ -219,10 +217,7 @@ class Core extends Module { 0 )).asUInt, (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt, - (exe_reg_exe_fun === ALU_SLTU) -> (exe_reg_op1_data < exe_reg_op2_data).asUInt, - (exe_reg_exe_fun === ALU_JALR) -> ((exe_reg_op1_data + exe_reg_op2_data) & (~1 - .U(WORD_LEN.W))), - (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data + (exe_reg_exe_fun === ALU_SLTU) -> (exe_reg_op1_data < exe_reg_op2_data).asUInt ) ) @@ -246,7 +241,6 @@ class Core extends Module { mem_reg_alu_out := exe_alu_out mem_reg_rf_wen := exe_reg_rf_wen mem_reg_wb_sel := exe_reg_wb_sel - mem_reg_imm_z_uext := exe_reg_imm_z_uext mem_reg_mem_wen := exe_reg_mem_wen // ********* Memory (MEM) Stage ********* @@ -279,6 +273,9 @@ class Core extends Module { printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") printf(p"id_rs1_data: 0x${Hexadecimal(id_rs1_data)}\n") printf(p"id_rs2_data: 0x${Hexadecimal(id_rs2_data)}\n") + printf(p"id_exe_fun: 0x${Hexadecimal(id_exe_fun)}\n") + printf(p"id_op1_sel: 0x${Hexadecimal(id_op1_sel)}\n") + printf(p"id_op2_sel: 0x${Hexadecimal(id_op2_sel)}\n") printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") printf(p"exe_reg_op1_data: 0x${Hexadecimal(id_op1_data)}\n") printf(p"exe_reg_op2_data: 0x${Hexadecimal(id_op2_data)}\n") @@ -287,24 +284,4 @@ class Core extends Module { printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") printf(p"---------------------\n") - - // io.gp := regfile(3) - // printf(p"---------------\n") - // printf( - // p"io.pc: 0x${Hexadecimal(pc_reg)}\ninst: 0x${Hexadecimal(inst)} \n" - // ) - // // printf( - // // p"rs1_addr: 0x${Hexadecimal(rs1_addr)} rs2_addr: 0x${Hexadecimal(rs2_addr)} wb_addr: 0x${Hexadecimal(wb_addr)}\n" - // // ) - // // printf(p"gp: 0x${Hexadecimal(regfile(3))}\n") - // printf(p"rs1_addr: 0x${Hexadecimal(rs1_addr)}\n") - // // printf(p"rs2_data: 0x${Hexadecimal(rs2_data)}\n") - // printf(p"wb_addr: 0x${Hexadecimal(wb_addr)}\n") - // printf(p"rs1_data: 0x${Hexadecimal(rs1_data)}\n") - // printf(p"wb_data: 0x${Hexadecimal(wb_data)}\n") - // // printf(p"dmem.addr: 0x${Hexadecimal(io.dmem.addr)}\n") - // // printf(p"dmem.wen: ${io.dmem.wen}\n") - // // printf(p"dmem.wdata: 0x${Hexadecimal(io.dmem.wdata)}\n") - // printf(p"---------------\n") - } diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala index 40d003d..9eb8386 100755 --- a/src/main/scala/micore/Memory.scala +++ b/src/main/scala/micore/Memory.scala @@ -31,7 +31,7 @@ class Memory extends Module { val mem = Mem(4096, UInt(8.W)) // 加载存储器的初始值。 - loadMemoryFromFileInline(mem, "src/hex/mem.hex") + loadMemoryFromFileInline(mem, "src/hex/addi.hex") // 连接四个地址存储的八位数据形成一个32位的指令。 io.imem.inst := Cat( diff --git a/src/main/scala/sicore/Core.scala b/src/main/scala/sicore/Core.scala new file mode 100755 index 0000000..d49de9e --- /dev/null +++ b/src/main/scala/sicore/Core.scala @@ -0,0 +1,151 @@ +package sicore + +import chisel3._ +import chisel3.util._ +import common.Consts._ +import common.Instructions._ + +class Core extends Module { + val io = IO(new Bundle { + val imem = Flipped(new ImemPortIo()) + val dmem = Flipped(new DmemPortIo()) + val exit = Output(Bool()) + }) + + // 寄存器文件 + val regfile = Mem(32, UInt(WORD_LEN.W)) + + // ********* Instruction Fetch (IF) Stage ********* + val pc_reg = RegInit(START_ADDR) + io.imem.addr := pc_reg + val inst = io.imem.inst + val pc_plus4 = pc_reg + 4.U(WORD_LEN.W) + val br_flg = Wire(Bool()) + val br_target = Wire(UInt(WORD_LEN.W)) + val jmp_flg = (inst === JAL || inst === JR) + val alu_out = Wire(UInt(WORD_LEN.W)) + + val pc_next = MuxCase( + pc_plus4, + Seq( + br_flg -> br_target, + jmp_flg -> alu_out + ) + ) + + pc_reg := pc_next + + // ********* Decode (ID) Stage ********* + val rs_addr = inst(25, 21) // rs_addr为指令的rs字段 + val rt_addr = inst(20, 16) // rt_addr为指令的rt字段 + val rd_addr = inst(15, 11) // rd_addr为指令的rd字段 + val rs_data = Mux((rs_addr =/= 0.U), regfile(rs_addr), 0.U(WORD_LEN.W)) + val rt_data = Mux((rt_addr =/= 0.U), regfile(rt_addr), 0.U(WORD_LEN.W)) + val imm_i = inst(15, 0) + val imm_i_sext = Cat(Fill(16, imm_i(15)), imm_i) + val imm_j = Cat(inst(25, 0), Fill(2, 0.U(1.W))) + + val csignals = ListLookup( + inst, + List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), + Array( + LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM), + SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_X, WB_X), + ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), + BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), + SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), + JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) // 添加JR指令 + ) + ) + + val exe_fun :: op1_sel :: op2_sel :: mem_wen :: rf_wen :: wb_sel :: Nil = + csignals + + val op1_data = MuxCase( + 0.U(WORD_LEN.W), + Seq( + (op1_sel === OP1_RS1) -> rs_data, + (op1_sel === OP1_PC) -> pc_reg + ) + ) + + val op2_data = MuxCase( + 0.U(WORD_LEN.W), + Seq( + (op2_sel === OP2_RS2) -> rt_data, + (op2_sel === OP2_IMI) -> imm_i_sext, + (op2_sel === OP2_IMJ) -> imm_j + ) + ) + + // ********* Execute (EX) Stage ********* + alu_out := MuxCase( + 0.U(WORD_LEN.W), + Seq( + (exe_fun === ALU_ADD) -> (op1_data + op2_data), + (exe_fun === ALU_SUB) -> (op1_data - op2_data), + (exe_fun === ALU_AND) -> (op1_data & op2_data), + (exe_fun === ALU_OR) -> (op1_data | op2_data), + (exe_fun === ALU_XOR) -> (op1_data ^ op2_data), + (exe_fun === ALU_SLL) -> (op1_data << op2_data(4, 0))(31, 0), + (exe_fun === ALU_SRL) -> (op1_data >> op2_data(4, 0)).asUInt, + (exe_fun === ALU_SRA) -> (op1_data.asSInt >> op2_data(4, 0)).asUInt, + (exe_fun === ALU_SLT) -> (op1_data.asSInt < op2_data.asSInt).asUInt, + (exe_fun === ALU_COPY1) -> op1_data // 添加JR指令的处理 + ) + ) + + br_flg := MuxCase( + false.B, + Seq( + (exe_fun === BR_BEQ) -> (op1_data === op2_data), + (exe_fun === BR_BNE) -> !(op1_data === op2_data) + ) + ) + + // 修复：将移位操作数的位宽限制为5位 + br_target := pc_reg + (imm_i_sext << 2.U(5.W)) + + // ********* Memory (MEM) Stage ********* + io.dmem.addr := alu_out + io.dmem.wen := mem_wen + io.dmem.wdata := rt_data + + // ********* Write Back (WB) Stage ********* + val wb_data = MuxCase( + alu_out, + Seq( + (wb_sel === WB_MEM) -> io.dmem.rdata, + (wb_sel === WB_PC) -> pc_plus4 + ) + ) + + // 写回寄存器文件 + when(rf_wen === REN_S && rd_addr =/= 0.U) { + regfile(rd_addr) := wb_data + } + + io.exit := (inst === UNIMP) + + // ********* Debugging ********* + printf(p"---------------\n") + printf(p"io.pc: 0x${Hexadecimal(pc_reg)}\ninst: 0x${Hexadecimal(inst)} \n") + printf(p"pc_next: 0x${Hexadecimal(pc_next)}\n") + printf(p"rs_addr: 0x${Hexadecimal(rs_addr)}\n") + printf(p"rd_addr: 0x${Hexadecimal(rd_addr)}\n") + printf(p"rs_data: 0x${Hexadecimal(rs_data)}\n") + printf(p"wb_data: 0x${Hexadecimal(wb_data)}\n") + printf(p"---------------\n") +} diff --git a/src/main/scala/sicore/Memory.scala b/src/main/scala/sicore/Memory.scala new file mode 100755 index 0000000..97d4bca --- /dev/null +++ b/src/main/scala/sicore/Memory.scala @@ -0,0 +1,59 @@ +package sicore + +import chisel3._ +import chisel3.util._ +import common.Consts._ +import chisel3.util.experimental.loadMemoryFromFileInline + +/** 表示一个指令内存端口接口的类 + */ +class ImemPortIo extends Bundle { + val addr = Input(UInt(WORD_LEN.W)) + val inst = Output(UInt(WORD_LEN.W)) +} + +/** 表示一个数据内存端口接口的类 + */ +class DmemPortIo extends Bundle { + val addr = Input(UInt(WORD_LEN.W)) + val rdata = Output(UInt(WORD_LEN.W)) + val wen = Input(Bool()) + val wdata = Input(UInt(WORD_LEN.W)) +} + +class Memory extends Module { + val io = IO(new Bundle { + val imem = new ImemPortIo() + val dmem = new DmemPortIo() + }) + + // 生成八位宽x4096(4KB)寄存器的存储器。 + val mem = Mem(4096, UInt(8.W)) + + // 加载存储器的初始值。 + loadMemoryFromFileInline(mem, "src/hex/mem.hex") + + // 连接四个地址存储的八位数据形成一个32位的指令。 + io.imem.inst := Cat( + mem(io.imem.addr + 3.U(WORD_LEN.W)), + mem(io.imem.addr + 2.U(WORD_LEN.W)), + mem(io.imem.addr + 1.U(WORD_LEN.W)), + mem(io.imem.addr) + ) + + // 连接四个地址存储的八位数据形成一个32位的数据。 + io.dmem.rdata := Cat( + mem(io.dmem.addr + 3.U(WORD_LEN.W)), + mem(io.dmem.addr + 2.U(WORD_LEN.W)), + mem(io.dmem.addr + 1.U(WORD_LEN.W)), + mem(io.dmem.addr) + ) + + // 写数据到存储器。 + when(io.dmem.wen) { + mem(io.dmem.addr) := io.dmem.wdata(7, 0) + mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8) + mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(23, 16) + mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(31, 24) + } +} diff --git a/src/main/scala/sicore/Top.scala b/src/main/scala/sicore/Top.scala new file mode 100755 index 0000000..05bc3c9 --- /dev/null +++ b/src/main/scala/sicore/Top.scala @@ -0,0 +1,30 @@ +package sicore + +import chisel3._ +// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ +import _root_.circt.stage.ChiselStage +import common.Consts._ + +class TopOrigin extends Module { + val io = IO(new Bundle { + val exit = Output(Bool()) + }) + val core = Module(new Core()) + val memory = Module(new Memory()) + core.io.imem <> memory.io.imem + core.io.dmem <> memory.io.dmem + io.exit := core.io.exit +} + +/** Generate Verilog sources and save it in file + */ +object TopOrigin extends App { + ChiselStage.emitSystemVerilogFile( + new TopOrigin, + firtoolOpts = Array( + "--disable-all-randomization", + "--strip-debug-info", + "--O=release" + ) + ) +} diff --git a/src/test/scala/micore/MicoreSpec.scala b/src/test/scala/micore/MicoreSpec.scala index 879f293..7c9f8b1 100755 --- a/src/test/scala/micore/MicoreSpec.scala +++ b/src/test/scala/micore/MicoreSpec.scala @@ -9,6 +9,7 @@ class CTest extends AnyFlatSpec with ChiselScalatestTester { "Micore" should "run the C program" in { test(new TopOrigin) { c => while (!c.io.exit.peek().litToBoolean) { c.clock.step(1) } + c.clock.step(1) } } } diff --git a/src/test/scala/sicore/SicoreSpec.scala b/src/test/scala/sicore/SicoreSpec.scala new file mode 100755 index 0000000..10e1199 --- /dev/null +++ b/src/test/scala/sicore/SicoreSpec.scala @@ -0,0 +1,15 @@ +package sicore + +import chisel3._ +import chiseltest._ +import org.scalatest.flatspec.AnyFlatSpec +import org.scalatest.matchers.should.Matchers + +class MemTest extends AnyFlatSpec with ChiselScalatestTester { + "Sicore" should "run the C program" in { + test(new TopOrigin) { c => + while (!c.io.exit.peek().litToBoolean) { c.clock.step(1) } + c.clock.step(1) + } + } +} diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar old mode 100644 new mode 100755 index a9270ff..e15fe4c Binary files a/target/scala-2.13/-name-_2.13-0.1.0.jar and b/target/scala-2.13/-name-_2.13-0.1.0.jar differ diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip old mode 100644 new mode 100755 index f980154..db59827 Binary files a/target/scala-2.13/zinc/inc_compile_2.13.zip and b/target/scala-2.13/zinc/inc_compile_2.13.zip differ diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous index 6e27812..b950716 100755 --- a/target/streams/compile/_global/_global/compileOutputs/previous +++ b/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/discoveredMainClasses/data b/target/streams/compile/_global/_global/discoveredMainClasses/data index 708003a..63fda3e 100755 --- a/target/streams/compile/_global/_global/discoveredMainClasses/data +++ b/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -1 +1 @@ -["micore.TopOrigin"] \ No newline at end of file +["micore.TopOrigin","sicore.TopOrigin"] \ No newline at end of file diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index f3c3491..3710e64 100755 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -1,29 +1,28 @@ [debug] [zinc] IncrementalCompile ----------- [debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 14 products, 5 sources, 2 libraries -[debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala) -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] previous = Stamps for: 24 products, 8 sources, 2 libraries +[debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/sicore/Top.scala, ${BASE}/src/main/scala/sicore/Memory.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/sicore/Core.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala) +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/sicore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set()) [debug]  [debug] Initial source changes: [debug]  removed: Set() [debug]  added: Set() -[debug]  modified: Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala) +[debug]  modified: Set(${BASE}/src/main/scala/sicore/Core.scala) [debug] Invalidated products: Set() [debug] External API changes: API Changes: Set() [debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo) +[debug] Initial directly invalidated classes: Set(sicore.Core) [debug] Sources indirectly invalidated by: [debug]  product: Set() [debug]  binary dep: Set() [debug]  external source: Set() -[debug] All initially invalidated classes: Set(micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo) -[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala) -[debug] Initial set of included nodes: micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo -[debug] Recompiling all sources: number of invalidated sources > 50.0 percent of all sources +[debug] All initially invalidated classes: Set(sicore.Core) +[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/sicore/Core.scala) +[debug] Initial set of included nodes: sicore.Core [debug] compilation cycle 1 -[info] compiling 5 Scala sources to /home/gh0s7/project/ddca/micore/target/scala-2.13/classes ... +[info] compiling 1 Scala source to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ... [debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar. -[debug] [zinc] Running cached compiler 53b08b84 for Scala compiler version 2.13.12 +[debug] [zinc] Running cached compiler 486ef6c9 for Scala compiler version 2.13.12 [debug] [zinc] The Scala compiler is invoked with: [debug]  -language:reflectiveCalls [debug]  -deprecation @@ -34,6 +33,22 @@ [debug]  -bootclasspath [debug]  /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar [debug]  -classpath -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar -[debug] Scala compilation took 3.902681144 s +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar +[debug] Invalidating (transitively) by inheritance from sicore.Core... +[debug] Initial set of included nodes: sicore.Core +[debug] Invalidated by transitive inheritance dependency: Set(sicore.Core) +[debug] None of the modified names appears in source file of sicore.TopOrigin. This dependency is not being considered for invalidation. +[debug] Change NamesChange(sicore.Core,ModifiedNames(changes = UsedName(rs_addr,[Default]), UsedName(imm_j,[Default]), UsedName(alu_result,[Default]), UsedName(opcode,[Default]), UsedName(rd,[Default]), UsedName(address,[Default]), UsedName(rt,[Default]), UsedName(imm,[Default]), UsedName(rf_wen,[Default]), UsedName(op1_sel,[Default]), UsedName(shamt,[Default]), UsedName(mem_wen,[Default]), UsedName(rs,[Default]), UsedName(csignals,[Default]), UsedName(pc_next,[Default]), UsedName(is_jump,[Default]), UsedName(br_target,[Default]), UsedName(imm_sext,[Default]), UsedName(rd_addr,[Default]), UsedName(alu_out,[Default]), UsedName(exe_fun,[Default]), UsedName(br_flg,[Default]), UsedName(pc_inc,[Default]), UsedName(is_branch,[Default]), UsedName(rt_addr,[Default]), UsedName(alu_op2,[Default]), UsedName(jmp_flg,[Default]), UsedName(funct,[Default]), UsedName(branch_target,[Default]), UsedName(imm_i,[Default]), UsedName(op2_data,[Default]), UsedName(pc_plus4,[Default]), UsedName(wb_sel,[Default]), UsedName(op1_data,[Default]), UsedName(wb_data,[Default]), UsedName(alu_op1,[Default]), UsedName(op2_sel,[Default]), UsedName(jump_target,[Default]), UsedName(imm_i_sext,[Default]))) invalidates 1 classes due to The sicore.Core has the following regular definitions changed: +[debug]  UsedName(rs_addr,[Default]), UsedName(imm_j,[Default]), UsedName(alu_result,[Default]), UsedName(opcode,[Default]), UsedName(rd,[Default]), UsedName(address,[Default]), UsedName(rt,[Default]), UsedName(imm,[Default]), UsedName(rf_wen,[Default]), UsedName(op1_sel,[Default]), UsedName(shamt,[Default]), UsedName(mem_wen,[Default]), UsedName(rs,[Default]), UsedName(csignals,[Default]), UsedName(pc_next,[Default]), UsedName(is_jump,[Default]), UsedName(br_target,[Default]), UsedName(imm_sext,[Default]), UsedName(rd_addr,[Default]), UsedName(alu_out,[Default]), UsedName(exe_fun,[Default]), UsedName(br_flg,[Default]), UsedName(pc_inc,[Default]), UsedName(is_branch,[Default]), UsedName(rt_addr,[Default]), UsedName(alu_op2,[Default]), UsedName(jmp_flg,[Default]), UsedName(funct,[Default]), UsedName(branch_target,[Default]), UsedName(imm_i,[Default]), UsedName(op2_data,[Default]), UsedName(pc_plus4,[Default]), UsedName(wb_sel,[Default]), UsedName(op1_data,[Default]), UsedName(wb_data,[Default]), UsedName(alu_op1,[Default]), UsedName(op2_sel,[Default]), UsedName(jump_target,[Default]), UsedName(imm_i_sext,[Default]). +[debug]  > by transitive inheritance: Set(sicore.Core) +[debug]  >  +[debug]  >  +[debug]   +[debug] New invalidations: +[debug] Initial set of included nodes:  +[debug] Previously invalidated, but (transitively) depend on new invalidations: +[debug] Final step, transitive dependencies: +[debug]  Set() +[debug] No classes were invalidated. +[debug] Scala compilation took 2.296694362 s [debug] done compiling diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export index 26fe379..671555b 100755 --- a/target/streams/compile/exportedProductJars/_global/streams/export +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export index 3c15dcc..21cdc14 100755 --- a/target/streams/compile/exportedProducts/_global/streams/export +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/target/scala-2.13/classes +/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out index 4a34f08..dae7507 100755 --- a/target/streams/compile/incOptions/_global/streams/out +++ b/target/streams/compile/incOptions/_global/streams/out @@ -1,47 +1,11 @@ -[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak [debug] About to delete class files: -[debug]  Core$$anon$1.class -[debug]  Consts$.class -[debug]  TopOrigin$delayedInit$body.class -[debug]  Instructions$.class -[debug]  TopOrigin.class -[debug]  TopOrigin$$anon$1.class -[debug]  Memory$$anon$1.class -[debug]  ImemPortIo.class [debug]  Core.class -[debug]  Consts.class -[debug]  DmemPortIo.class -[debug]  Memory.class -[debug]  TopOrigin$.class -[debug]  Instructions.class +[debug]  Core$$anon$1.class [debug] We backup class files: -[debug]  Core$$anon$1.class -[debug]  Consts$.class -[debug]  TopOrigin$delayedInit$body.class -[debug]  Instructions$.class -[debug]  TopOrigin.class -[debug]  TopOrigin$$anon$1.class -[debug]  Memory$$anon$1.class -[debug]  ImemPortIo.class [debug]  Core.class -[debug]  Consts.class -[debug]  DmemPortIo.class -[debug]  Memory.class -[debug]  TopOrigin$.class -[debug]  Instructions.class +[debug]  Core$$anon$1.class [debug] Registering generated classes: [debug]  Core$$anon$1.class -[debug]  Consts$.class -[debug]  TopOrigin$delayedInit$body.class -[debug]  Instructions$.class -[debug]  TopOrigin.class -[debug]  TopOrigin$$anon$1.class -[debug]  Memory$$anon$1.class -[debug]  ImemPortIo.class [debug]  Core.class -[debug]  Consts.class -[debug]  DmemPortIo.class -[debug]  Memory.class -[debug]  TopOrigin$.class -[debug]  Instructions.class -[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak +[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs index 66c2ab4..35c218e 100755 --- a/target/streams/compile/packageBin/_global/streams/inputs +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ --1320494222 \ No newline at end of file +175918183 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out index f991401..873cb34 100755 --- a/target/streams/compile/packageBin/_global/streams/out +++ b/target/streams/compile/packageBin/_global/streams/out @@ -1,51 +1,57 @@ -[debug] Packaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... +[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... [debug] Input file mappings: -[debug]  gcd -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd -[debug]  gcd/GcdInputBundle.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class -[debug]  gcd/GcdOutputBundle.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class -[debug]  gcd/DecoupledGcd.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class -[debug]  gcd/GCD.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class -[debug]  gcd/GCD$.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class -[debug]  gcd/GCD$$anon$1.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class -[debug]  gcd/GCD$delayedInit$body.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class [debug]  common -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common [debug]  common/Consts$.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class [debug]  common/Consts.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class [debug]  common/Instructions$.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class [debug]  common/Instructions.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class [debug]  micore -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore -[debug]  micore/Core.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore [debug]  micore/Core$$anon$1.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class -[debug]  micore/ImemPortIo.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class +[debug]  micore/Core.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class [debug]  micore/DmemPortIo.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class -[debug]  micore/Memory.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class +[debug]  micore/ImemPortIo.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class [debug]  micore/Memory$$anon$1.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class -[debug]  micore/TopOrigin.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class -[debug]  micore/TopOrigin$.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class +[debug]  micore/Memory.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class [debug]  micore/TopOrigin$$anon$1.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class +[debug]  micore/TopOrigin$.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class [debug]  micore/TopOrigin$delayedInit$body.class -[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class +[debug]  micore/TopOrigin.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class +[debug]  sicore +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore +[debug]  sicore/Core$$anon$1.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class +[debug]  sicore/Core.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core.class +[debug]  sicore/DmemPortIo.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/DmemPortIo.class +[debug]  sicore/ImemPortIo.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/ImemPortIo.class +[debug]  sicore/Memory$$anon$1.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class +[debug]  sicore/Memory.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory.class +[debug]  sicore/TopOrigin$$anon$1.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class +[debug]  sicore/TopOrigin$.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$.class +[debug]  sicore/TopOrigin$delayedInit$body.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class +[debug]  sicore/TopOrigin.class +[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin.class [debug] Done packaging. diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output index 4e9041f..ccc866e 100755 --- a/target/streams/compile/packageBin/_global/streams/output +++ b/target/streams/compile/packageBin/_global/streams/output @@ -1 +1 @@ -1488086236 \ No newline at end of file +-1359482768 \ No newline at end of file diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export index ddc45ce..112ae53 100755 --- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -1 +1 @@ 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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export index 26fe379..671555b 100755 --- a/target/streams/runtime/exportedProductJars/_global/streams/export +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export index ddc45ce..112ae53 100755 --- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -1 +1 @@ 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diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export index 26fe379..671555b 100755 --- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir index 908c5e5..caeb25a 100755 --- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -81,13 +81,13 @@ circuit TopOrigin : node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 65:31] node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 65:31] node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] - node id_rs1_addr_b = bits(id_reg_inst, 19, 15) @[src/main/scala/micore/Core.scala 87:34] + node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 87:34] node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50] node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77] node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59] node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21] - node id_rs2_addr_b = bits(id_reg_inst, 24, 20) @[src/main/scala/micore/Core.scala 88:34] + node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 88:34] node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:50] node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32] node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:77] @@ -127,25 +127,17 @@ circuit TopOrigin : node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 221:65] node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 222:24] node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 222:59] - node _exe_alu_out_T_30 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 223:24] - node _exe_alu_out_T_31 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:60] - node _exe_alu_out_T_32 = tail(_exe_alu_out_T_31, 1) @[src/main/scala/micore/Core.scala 223:60] - node _exe_alu_out_T_33 = not(UInt<32>("h1")) @[src/main/scala/micore/Core.scala 223:83] - node _exe_alu_out_T_34 = and(_exe_alu_out_T_32, _exe_alu_out_T_33) @[src/main/scala/micore/Core.scala 223:80] - node _exe_alu_out_T_35 = eq(exe_reg_exe_fun, UInt<5>("he")) @[src/main/scala/micore/Core.scala 225:24] - node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_37 = mux(_exe_alu_out_T_30, _exe_alu_out_T_34, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_38 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_39 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_40 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_39) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_41 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_40) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_42 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_41) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_43 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_42) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_44 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_43) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_45 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_44) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_46 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_45) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_47 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_46) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_alu_out = _exe_alu_out_T_47 @[src/main/scala/micore/Core.scala 201:15 63:25] + node _exe_alu_out_T_30 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_31 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_32 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_33 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_34 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_35 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_36 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_37 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_38 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_39 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 201:15 63:25] node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 232:24] node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 232:57] @@ -162,10 +154,10 @@ circuit TopOrigin : node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 77:19] node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 81:19] node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21] node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36] - node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8] + node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8] node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 100:28] node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 101:28] node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 102:27] @@ -218,23 +210,23 @@ circuit TopOrigin : node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_4 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_4 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_6 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_8 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_8 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_10 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_10 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_12 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_12 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_14 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_14 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_16 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_18 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_20 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_20 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_22 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -246,134 +238,126 @@ circuit TopOrigin : node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_32 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(id_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_34 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_35 = eq(UInt<30>("h30000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_36 = and(id_inst, UInt<34>("h3ff800000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_37 = eq(UInt<32>("hf0000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_38 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h0"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_36 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_37 = eq(UInt<30>("h20000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_38 = mux(_csignals_T_37, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_39 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_40 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_41 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_42 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_43 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_44 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_45 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_46 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_47 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_48 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_49 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_50 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_51 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_52 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_53 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_54 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_55 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_56 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_57 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_58 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_59 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_60 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_61 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_62 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_63 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_64 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_65 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_66 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_67 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_68 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_69 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_70 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_71 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_72 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_73 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_74 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_75 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_76 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_77 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_78 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_79 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_80 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_81 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_82 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_83 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_84 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_85 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_86 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_87 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_88 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_89 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_90 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_91 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_92 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_93 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_94 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_95 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_96 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_97 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_98 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_99 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_100 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_101 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_102 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_103 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_104 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_105 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_106 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_107 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_108 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_109 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_110 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_111 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_112 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_113 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_114 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_115 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_116 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_117 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_118 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_119 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_120 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_121 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_122 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_123 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_124 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_125 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_126 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_127 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_128 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_129 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_130 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_131 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_132 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_133 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_134 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_135 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_136 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_137 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_138 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_139 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_140 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_141 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_142 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_143 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_144 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_145 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 171:19] node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 172:19] node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] @@ -423,6 +407,12 @@ circuit TopOrigin : node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] + node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] + node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] + node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9] + node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9] + node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9] + node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9] io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 56:16] io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 253:16] io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 254:15] @@ -467,7 +457,7 @@ circuit TopOrigin : wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:18 50:{31,31}] wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 267:17 51:{30,30}] wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 266:18 52:{31,31}] - if_reg_pc <= mux(reset, UInt<32>("h400000"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13] + if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13] printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 275:9] printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 276:9] printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 277:9] @@ -475,14 +465,17 @@ circuit TopOrigin : printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 279:9] printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 280:9] printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 281:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_7 @[src/main/scala/micore/Core.scala 282:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_8 @[src/main/scala/micore/Core.scala 283:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_9 @[src/main/scala/micore/Core.scala 284:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_10 @[src/main/scala/micore/Core.scala 285:9] - printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_11 @[src/main/scala/micore/Core.scala 286:9] - printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9] - printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_13 @[src/main/scala/micore/Core.scala 288:9] - printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------------\n") : printf_14 @[src/main/scala/micore/Core.scala 289:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 282:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 283:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 284:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 285:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 286:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 288:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 289:9] + printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 290:9] + printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 291:9] + printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 292:9] module Memory : @[src/main/scala/micore/Memory.scala 24:7] input clock : Clock @[src/main/scala/micore/Memory.scala 24:7] diff --git a/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir new file mode 100755 index 0000000..0176dec --- /dev/null +++ b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir @@ -0,0 +1,452 @@ +FIRRTL version 1.2.0 +circuit TopOrigin : + module Core : @[src/main/scala/sicore/Core.scala 8:7] + input clock : Clock @[src/main/scala/sicore/Core.scala 8:7] + input reset : UInt<1> @[src/main/scala/sicore/Core.scala 8:7] + output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] + input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] + output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] + input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] + output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 9:14] + output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] + output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 9:14] + + mem regfile : @[src/main/scala/sicore/Core.scala 16:20] + data-type => UInt<32> + depth => 32 + read-latency => 0 + write-latency => 1 + reader => rs_data_MPORT + reader => rt_data_MPORT + writer => MPORT + read-under-write => undefined + reg pc_reg : UInt<32>, clock with : + reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 19:23] + node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 22:25] + node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 22:25] + node _jmp_flg_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/sicore/Core.scala 25:23] + node _jmp_flg_T_1 = eq(UInt<30>("h30000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 25:23] + node _jmp_flg_T_2 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/sicore/Core.scala 25:39] + node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 25:39] + node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 25:31] + node _csignals_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_2 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_4 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_6 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_8 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_10 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_11 = eq(UInt<6>("h24"), _csignals_T_10) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_12 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_14 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_16 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_18 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_20 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_22 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_24 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_26 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_28 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_30 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_33 = eq(UInt<30>("h30000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_38 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_39 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_40 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_41 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_42 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_43 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_44 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_45 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_46 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_47 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_48 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_49 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_50 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 97:16] + node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_56 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_57 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_58 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_59 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_60 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_61 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_62 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_63 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_64 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_65 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_66 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_67 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 79:16] + node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 39:21] + node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 42:30] + node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 42:20] + node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 80:16] + node _op1_data_T_2 = mux(_op1_data_T_1, pc_reg, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node op1_data = mux(_op1_data_T, rs_data, _op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_71 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_72 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_73 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_74 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_75 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_76 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_77 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_78 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_79 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_80 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_81 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_82 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_83 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_84 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 87:16] + node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 40:21] + node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30] + node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20] + node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 88:16] + node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 44:19] + node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 45:38] + node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 45:28] + node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 45:23] + node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 89:16] + node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 46:23] + node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 46:36] + node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 46:18] + node _op2_data_T_3 = mux(_op2_data_T_2, imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _op2_data_T_4 = mux(_op2_data_T_1, imm_i_sext, _op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node op2_data = mux(_op2_data_T, rt_data, _op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 97:42] + node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 97:42] + node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 98:16] + node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 99:16] + node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42] + node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 100:16] + node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:41] + node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 101:16] + node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:42] + node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 102:16] + node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 102:53] + node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 102:42] + node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 102:60] + node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 103:16] + node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53] + node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 103:42] + node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 104:16] + node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 104:42] + node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:60] + node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 104:49] + node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 104:68] + node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 105:16] + node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42] + node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 105:60] + node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 105:49] + node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 106:16] + node _alu_out_T_29 = mux(_alu_out_T_28, op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_30 = mux(_alu_out_T_24, _alu_out_T_27, _alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_31 = mux(_alu_out_T_19, _alu_out_T_23, _alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_32 = mux(_alu_out_T_16, _alu_out_T_18, _alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_33 = mux(_alu_out_T_12, _alu_out_T_15, _alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_34 = mux(_alu_out_T_10, _alu_out_T_11, _alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_35 = mux(_alu_out_T_8, _alu_out_T_9, _alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_36 = mux(_alu_out_T_6, _alu_out_T_7, _alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_37 = mux(_alu_out_T_3, _alu_out_T_5, _alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _alu_out_T_38 = mux(_alu_out_T, _alu_out_T_2, _alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 26:21 94:11] + node _pc_next_T = mux(jmp_flg, alu_out, pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 113:16] + node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 113:41] + node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 114:16] + node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:42] + node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 114:31] + node _br_flg_T_5 = mux(_br_flg_T_2, _br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _br_flg_T_6 = mux(_br_flg_T, _br_flg_T_1, _br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 110:10 23:20] + node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 119:37] + node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 119:23] + node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 119:23] + node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 119:13 24:23] + node pc_next = mux(br_flg, br_target, _pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 41:21] + node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_90 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_91 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_92 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_93 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_94 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_95 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_96 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_97 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_98 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_99 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_100 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_101 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_102 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_103 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_104 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_105 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_106 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_107 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_108 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_109 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_110 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_111 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_112 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_113 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_114 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_115 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_116 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_117 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_118 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_119 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_120 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_121 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_122 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_123 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_124 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_125 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_126 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_127 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_128 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_129 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_130 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_131 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_132 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_133 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_134 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_135 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 130:15] + node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 131:15] + node _wb_data_T_2 = mux(_wb_data_T_1, pc_plus4, alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node wb_data = mux(_wb_data_T, io_dmem_rdata, _wb_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 136:15] + node _T_1 = neq(rd_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:36] + node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 136:25] + node _GEN_0 = validif(_T_2, rd_addr) @[src/main/scala/sicore/Core.scala 136:45 137:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 136:45 137:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:45 137:12 16:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 136:45 137:22] + node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 136:45 137:22] + node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 140:20] + node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 143:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:9] + node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 144:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 144:9] + node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 145:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 145:9] + node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 146:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:9] + node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 147:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 147:9] + node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 148:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 148:9] + node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 149:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 149:9] + node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 150:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 150:9] + io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 20:16] + io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 122:16] + io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 123:15] + io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 124:17] + io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 140:11] + regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 42:47] + regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 42:47] + regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 42:47] + regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 43:47] + regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47] + regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47] + regfile.MPORT.addr <= _GEN_0 + regfile.MPORT.en <= _GEN_2 + regfile.MPORT.clk <= _GEN_1 + regfile.MPORT.data <= _GEN_4 + regfile.MPORT.mask <= _GEN_3 + pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 19:{23,23} 36:10] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 143:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 144:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_2 @[src/main/scala/sicore/Core.scala 145:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_3 @[src/main/scala/sicore/Core.scala 146:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_4 @[src/main/scala/sicore/Core.scala 147:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_5 @[src/main/scala/sicore/Core.scala 148:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_6 @[src/main/scala/sicore/Core.scala 149:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "---------------\n") : printf_7 @[src/main/scala/sicore/Core.scala 150:9] + + module Memory : @[src/main/scala/sicore/Memory.scala 24:7] + input clock : Clock @[src/main/scala/sicore/Memory.scala 24:7] + input reset : UInt<1> @[src/main/scala/sicore/Memory.scala 24:7] + input io_imem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + output io_imem_inst : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + input io_dmem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + output io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + input io_dmem_wen : UInt<1> @[src/main/scala/sicore/Memory.scala 25:14] + input io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + + mem mem : @[src/main/scala/sicore/Memory.scala 31:16] + data-type => UInt<8> + depth => 4096 + read-latency => 0 + write-latency => 1 + reader => io_imem_inst_MPORT + reader => io_imem_inst_MPORT_1 + reader => io_imem_inst_MPORT_2 + reader => io_imem_inst_MPORT_3 + reader => io_dmem_rdata_MPORT + reader => io_dmem_rdata_MPORT_1 + reader => io_dmem_rdata_MPORT_2 + reader => io_dmem_rdata_MPORT_3 + writer => MPORT + writer => MPORT_1 + writer => MPORT_2 + writer => MPORT_3 + read-under-write => undefined + node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 38:22] + node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/sicore/Memory.scala 38:22] + node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 38:8] + node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 39:22] + node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/sicore/Memory.scala 39:22] + node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 39:8] + node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 40:22] + node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/sicore/Memory.scala 40:22] + node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 40:8] + node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 41:8] + node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 37:22] + node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 37:22] + node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/sicore/Memory.scala 37:22] + node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 46:22] + node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/sicore/Memory.scala 46:22] + node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 46:8] + node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 47:22] + node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/sicore/Memory.scala 47:22] + node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 47:8] + node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 48:22] + node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/sicore/Memory.scala 48:22] + node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 48:8] + node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 49:8] + node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 45:23] + node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 45:23] + node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/sicore/Memory.scala 45:23] + node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 54:8] + node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/sicore/Memory.scala 54:39] + node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 55:22] + node _T_3 = tail(_T_2, 1) @[src/main/scala/sicore/Memory.scala 55:22] + node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/sicore/Memory.scala 55:8] + node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/sicore/Memory.scala 55:57] + node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 56:22] + node _T_7 = tail(_T_6, 1) @[src/main/scala/sicore/Memory.scala 56:22] + node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 56:8] + node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/sicore/Memory.scala 56:57] + node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 57:22] + node _T_11 = tail(_T_10, 1) @[src/main/scala/sicore/Memory.scala 57:22] + node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/sicore/Memory.scala 57:8] + node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/sicore/Memory.scala 57:57] + node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/sicore/Memory.scala 53:21 54:8] + node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/sicore/Memory.scala 53:21 54:8] + node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Memory.scala 31:16 53:21 54:8] + node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/sicore/Memory.scala 53:21 54:23] + node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/sicore/Memory.scala 53:21 54:23] + node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/sicore/Memory.scala 53:21 55:8] + node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/sicore/Memory.scala 53:21 55:41] + node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/sicore/Memory.scala 53:21 56:8] + node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/sicore/Memory.scala 53:21 56:41] + node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/sicore/Memory.scala 53:21 57:8] + node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/sicore/Memory.scala 53:21 57:41] + io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/sicore/Memory.scala 37:16] + io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/sicore/Memory.scala 45:17] + mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/sicore/Memory.scala 41:8] + mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 41:8] + mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/sicore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/sicore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/sicore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/sicore/Memory.scala 49:8] + mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 49:8] + mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 49:8] + mem.MPORT.addr <= _GEN_0 + mem.MPORT.en <= _GEN_2 + mem.MPORT.clk <= _GEN_1 + mem.MPORT.data <= _GEN_4 + mem.MPORT.mask <= _GEN_3 + mem.MPORT_1.addr <= _GEN_5 + mem.MPORT_1.en <= _GEN_2 + mem.MPORT_1.clk <= _GEN_1 + mem.MPORT_1.data <= _GEN_6 + mem.MPORT_1.mask <= _GEN_3 + mem.MPORT_2.addr <= _GEN_7 + mem.MPORT_2.en <= _GEN_2 + mem.MPORT_2.clk <= _GEN_1 + mem.MPORT_2.data <= _GEN_8 + mem.MPORT_2.mask <= _GEN_3 + mem.MPORT_3.addr <= _GEN_9 + mem.MPORT_3.en <= _GEN_2 + mem.MPORT_3.clk <= _GEN_1 + mem.MPORT_3.data <= _GEN_10 + mem.MPORT_3.mask <= _GEN_3 + + module TopOrigin : @[src/main/scala/sicore/Top.scala 8:7] + input clock : Clock @[src/main/scala/sicore/Top.scala 8:7] + input reset : UInt<1> @[src/main/scala/sicore/Top.scala 8:7] + output io_exit : UInt<1> @[src/main/scala/sicore/Top.scala 9:14] + + inst core of Core @[src/main/scala/sicore/Top.scala 12:20] + inst memory of Memory @[src/main/scala/sicore/Top.scala 13:22] + io_exit <= core.io_exit @[src/main/scala/sicore/Top.scala 16:11] + core.clock <= clock + core.reset <= reset + core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/sicore/Top.scala 14:16] + core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/sicore/Top.scala 15:16] + memory.clock <= clock + memory.reset <= reset + memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/sicore/Top.scala 14:16] + memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/sicore/Top.scala 15:16] + memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/sicore/Top.scala 15:16] + memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/sicore/Top.scala 15:16]