diff --git a/log.txt b/log.txt new file mode 100644 index 0000000..6a184f1 --- /dev/null +++ b/log.txt @@ -0,0 +1,2 @@ +[info] welcome to sbt 1.9.7 (Arch Linux Java 23) + \ No newline at end of file diff --git a/src/hex/mem.hex b/src/hex/mem.hex index 56ca829..bb3d0fa 100755 --- a/src/hex/mem.hex +++ b/src/hex/mem.hex @@ -6,7 +6,7 @@ 00 10 20 -65 +05 00 12 20 diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala index 893ffc1..47224e3 100755 --- a/src/main/scala/common/Consts.scala +++ b/src/main/scala/common/Consts.scala @@ -7,7 +7,7 @@ object Consts { // 数据宽度和地址 val WORD_LEN = 32 // 指令和数据的宽度为32位 val START_ADDR = 0x00000000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000 - val BUBBLE = 0x20000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] + val BUBBLE = 0x20090000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令 // 寄存器地址长度 diff --git a/src/main/scala/common/Instructions.scala b/src/main/scala/common/Instructions.scala index 7d5f10f..80d69a5 100755 --- a/src/main/scala/common/Instructions.scala +++ b/src/main/scala/common/Instructions.scala @@ -43,5 +43,5 @@ object Instructions { val JAL = BitPat("b000011??????????????????????????") // jal target // * NOP - val NOP = BitPat("b00100000000000000000000000000000") // nop (addi $0, $0, 0) + val NOP = BitPat("b00100000000010010000000000000000") // nop } diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala index 3b138d1..b35a84d 100755 --- a/src/main/scala/micore/Core.scala +++ b/src/main/scala/micore/Core.scala @@ -15,36 +15,34 @@ class Core extends Module { val regfile = Mem(32, UInt(WORD_LEN.W)) // ********* Pipeline Registers ********* - // IF/ID state + // IF/ID stage val id_reg_pc = RegInit(0.U(WORD_LEN.W)) val id_reg_inst = RegInit(0.U(WORD_LEN.W)) - // ID/EX state + // ID/EX stage val exe_reg_pc = RegInit(0.U(WORD_LEN.W)) val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W)) val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W)) - val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W)) + val exe_reg_rs_data = RegInit(0.U(WORD_LEN.W)) + val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W)) val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W)) val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W)) - val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W)) - val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W)) - val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W)) + val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W)) - // EX/MEM state + // EX/MEM stage val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) - val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W)) - val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W)) + val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) + val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W)) val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) - val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) - // MEM/WB state + // MEM/WB stage val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W)) val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W)) @@ -82,90 +80,64 @@ class Core extends Module { ) // ********* Decode (ID) Stage ********* - val id_rs1_addr_b = id_reg_inst(25, 21) - val id_rs2_addr_b = id_reg_inst(20, 16) + val id_rs_addr = id_reg_inst(25, 21) + val id_rt_addr = id_reg_inst(20, 16) + val id_rd_addr = id_reg_inst(15, 11) - // 与EX数据冒险 -> stall - val id_rs1_data_hazard = - (exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr) - val id_rs2_data_hazard = - (exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr) - stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard) + // Hazard detection + val id_rs_data_hazard = + (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr) + val id_rt_data_hazard = + (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr) + stall_flg := (id_rs_data_hazard || id_rt_data_hazard) && !(exe_reg_wb_sel === WB_MEM) + // stall_flg := 0.U(1.W) val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst) - val id_rs1_addr = id_inst(25, 21) - val id_rs2_addr = id_inst(20, 16) - // val id_wb_addr = id_inst(15, 11) - val id_wb_addr = MuxCase( - id_inst(20, 16), // 默认是 rt_addr + val id_rs_data = MuxCase( + regfile(id_rs_addr), Seq( - (id_inst(31, 26) === "b000000".U) -> id_inst( - 15, - 11 - ), // R型指令，目标寄存器是 rd_addr - (id_inst === JAL) -> 31.U // JAL指令，目标寄存器是 $ra (寄存器31) + (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W), + ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM + ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB ) ) - - val mem_wb_data = Wire(UInt(WORD_LEN.W)) - val id_rs1_data = MuxCase( - regfile(id_rs1_addr), + val id_rt_data = MuxCase( + regfile(id_rt_addr), Seq( - (id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEN直通 - ((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 - ) - ) - val id_rs2_data = MuxCase( - regfile(id_rs2_addr), - Seq( - (id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEN直通 - ((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 + (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W), + ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_reg_alu_out, // Forwarding from MEM + ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forwarding from WB ) ) val id_imm_i = id_inst(15, 0) val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i) - val id_imm_b = Cat( - id_inst(15, 0), - 0.U(2.W) - ) - val id_imm_b_sext = Cat(Fill(14, id_imm_b(17)), id_imm_b) - val id_imm_j = Cat( - id_inst(25, 0), - 0.U(2.W) - ) - val id_imm_j_sext = Cat(Fill(6, id_imm_j(25)), id_imm_j) - val id_imm_u = id_inst(15, 0) - val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U)) - val id_imm_shamt = id_inst(10, 6) + val id_imm_j = Cat(id_inst(25, 0), Fill(2, 0.U(1.W))) val csignals = ListLookup( id_inst, List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), Array( - LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_S, WB_MEM), - SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_S, WB_MEM), - ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), - SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), - ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), - SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM), + SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_X, WB_X), + ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), + SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), - SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), - JR -> List(ALU_X, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X), - JAL -> List(ALU_X, OP1_PC, OP2_X, MEN_X, REN_X, WB_X), - NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X) + SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), + JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), + JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) ) ) @@ -175,7 +147,7 @@ class Core extends Module { val id_op1_data = MuxCase( 0.U(WORD_LEN.W), Seq( - (id_op1_sel === OP1_RS1) -> id_rs1_data, + (id_op1_sel === OP1_RS1) -> id_rs_data, (id_op1_sel === OP1_PC) -> id_reg_pc ) ) @@ -183,10 +155,9 @@ class Core extends Module { val id_op2_data = MuxCase( 0.U(WORD_LEN.W), Seq( - (id_op2_sel === OP2_RS2) -> id_rs2_data, + (id_op2_sel === OP2_RS2) -> id_rt_data, (id_op2_sel === OP2_IMI) -> id_imm_i_sext, - (id_op2_sel === OP2_IMJ) -> id_imm_j_sext, - (id_op2_sel === OP2_IMU) -> id_imm_u_shifted + (id_op2_sel === OP2_IMJ) -> id_imm_j ) ) @@ -194,14 +165,23 @@ class Core extends Module { exe_reg_pc := id_reg_pc exe_reg_op1_data := id_op1_data exe_reg_op2_data := id_op2_data - exe_reg_rs2_data := id_rs2_data - exe_reg_wb_addr := id_wb_addr + exe_reg_rs_data := id_rs_data + exe_reg_rt_data := id_rt_data + exe_reg_wb_addr := MuxCase( + id_rt_addr, + Seq( + (id_wb_sel === WB_ALU && id_inst( + 31, + 26 + ) === "b000000".U) -> id_rd_addr, // R-type + (id_inst === JAL) -> 31.U + ) + ) exe_reg_wb_sel := id_wb_sel exe_reg_mem_wen := id_mem_wen exe_reg_rf_wen := id_rf_wen exe_reg_imm_i_sext := id_imm_i_sext - exe_reg_imm_b_sext := id_imm_b_sext - exe_reg_imm_u_shifted := id_imm_u_shifted + exe_reg_imm_j := id_imm_j exe_reg_exe_fun := id_exe_fun // ********* Execute (EX) Stage ********* @@ -226,7 +206,7 @@ class Core extends Module { 0 )).asUInt, (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt, - (exe_reg_exe_fun === ALU_SLTU) -> (exe_reg_op1_data < exe_reg_op2_data).asUInt + (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data ) ) @@ -238,26 +218,24 @@ class Core extends Module { ) ) - exe_br_target := exe_reg_pc + exe_reg_imm_b_sext - + exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U(5.W)) exe_jmp_flg := (exe_reg_wb_sel === WB_PC) - // ********** Execute/Memory (EX/MEM) Stage *********** + // ********* Execute/Memory (EX/MEM) Stage ********* mem_reg_pc := exe_reg_pc - mem_reg_op1_data := exe_reg_op1_data - mem_reg_rs2_data := exe_reg_rs2_data mem_reg_wb_addr := exe_reg_wb_addr mem_reg_alu_out := exe_alu_out + mem_reg_rt_data := exe_reg_rt_data + mem_reg_mem_wen := exe_reg_mem_wen mem_reg_rf_wen := exe_reg_rf_wen mem_reg_wb_sel := exe_reg_wb_sel - mem_reg_mem_wen := exe_reg_mem_wen // ********* Memory (MEM) Stage ********* io.dmem.addr := mem_reg_alu_out io.dmem.wen := mem_reg_mem_wen - io.dmem.wdata := mem_reg_rs2_data + io.dmem.wdata := mem_reg_rt_data - mem_wb_data := MuxCase( + val mem_wb_data = MuxCase( mem_reg_alu_out, Seq( (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata, @@ -265,35 +243,303 @@ class Core extends Module { ) ) - // ********** Memory/Write Back (MEM/WB) Stage *********** - wb_reg_wb_data := mem_wb_data - wb_reg_rf_wen := mem_reg_rf_wen + // ********* Memory/Write Back (MEM/WB) Stage ********* wb_reg_wb_addr := mem_reg_wb_addr + wb_reg_rf_wen := mem_reg_rf_wen + wb_reg_wb_data := mem_wb_data // ********* Write Back (WB) Stage ********* - // when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } - // ********* Debugging ********* io.exit := (id_reg_inst === UNIMP) - printf(p"---------------------\n") + + // ********* Debugging ********* + printf(p"---------------\n") printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n") printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n") - printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") - printf(p"id_rs1_data: 0x${Hexadecimal(id_rs1_data)}\n") - printf(p"id_rs2_data: 0x${Hexadecimal(id_rs2_data)}\n") - printf(p"id_exe_fun: 0x${Hexadecimal(id_exe_fun)}\n") - printf(p"id_op1_sel: 0x${Hexadecimal(id_op1_sel)}\n") - printf(p"id_op2_sel: 0x${Hexadecimal(id_op2_sel)}\n") printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") - printf(p"exe_reg_op1_data: 0x${Hexadecimal(id_op1_data)}\n") - printf(p"exe_reg_op2_data: 0x${Hexadecimal(id_op2_data)}\n") printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n") printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n") printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") - printf(p"---------------------\n") + printf(p"---------------\n") } +// package micore + +// import chisel3._ +// import chisel3.util._ +// import common.Consts._ +// import common.Instructions._ + +// class Core extends Module { +// val io = IO(new Bundle { +// val imem = Flipped(new ImemPortIo()) +// val dmem = Flipped(new DmemPortIo()) +// val exit = Output(Bool()) +// }) + +// val regfile = Mem(32, UInt(WORD_LEN.W)) + +// // ********* Pipeline Registers ********* +// // IF/ID state +// val id_reg_pc = RegInit(0.U(WORD_LEN.W)) +// val id_reg_inst = RegInit(0.U(WORD_LEN.W)) + +// // ID/EX state +// val exe_reg_pc = RegInit(0.U(WORD_LEN.W)) +// val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) +// val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W)) +// val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W)) +// val exe_reg_rt_data = RegInit(0.U(WORD_LEN.W)) +// val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W)) +// val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) +// val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W)) +// val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) +// val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W)) +// val exe_reg_imm_j = RegInit(0.U(WORD_LEN.W)) + +// // EX/MEM state +// val mem_reg_pc = RegInit(0.U(WORD_LEN.W)) +// val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) +// val mem_reg_rt_data = RegInit(0.U(WORD_LEN.W)) +// val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W)) +// val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W)) +// val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W)) +// val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W)) + +// // MEM/WB state +// val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W)) +// val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W)) +// val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W)) + +// // ********* Instruction Fetch (IF) Stage ********* +// val if_reg_pc = RegInit(START_ADDR) +// io.imem.addr := if_reg_pc +// val if_inst = io.imem.inst + +// val stall_flg = Wire(Bool()) +// val exe_br_flg = Wire(Bool()) +// val exe_br_target = Wire(UInt(WORD_LEN.W)) +// val exe_jmp_flg = Wire(Bool()) +// val exe_alu_out = Wire(UInt(WORD_LEN.W)) + +// val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W) +// val if_pc_next = MuxCase( +// if_pc_plus4, +// Seq( +// exe_br_flg -> exe_br_target, +// exe_jmp_flg -> exe_alu_out, +// stall_flg -> if_reg_pc // stall +// ) +// ) +// if_reg_pc := if_pc_next + +// // ********* IF/ID Stage ********* +// id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc) +// id_reg_inst := MuxCase( +// if_inst, +// Seq( +// (exe_br_flg || exe_jmp_flg) -> BUBBLE, +// stall_flg -> id_reg_inst +// ) +// ) + +// // ********* Decode (ID) Stage ********* +// val id_rs_addr = id_reg_inst(25, 21) +// val id_rt_addr = id_reg_inst(20, 16) +// val id_rd_addr = id_reg_inst(15, 11) + +// // Data hazard detection +// val id_rs_data_hazard = +// (exe_reg_rf_wen === REN_S) && (id_rs_addr =/= 0.U) && (id_rs_addr === exe_reg_wb_addr) +// val id_rt_data_hazard = +// (exe_reg_rf_wen === REN_S) && (id_rt_addr =/= 0.U) && (id_rt_addr === exe_reg_wb_addr) +// stall_flg := 0.U(1.W) +// // stall_flg := (id_rs_data_hazard || id_rt_data_hazard) + +// val id_inst = +// Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst) + +// val mem_wb_data = Wire(UInt(WORD_LEN.W)) +// val id_rs_data = MuxCase( +// regfile(id_rs_addr), +// Seq( +// (id_rs_addr === 0.U) -> 0.U(WORD_LEN.W), +// ((id_rs_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM +// ((id_rs_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB +// ) +// ) +// val id_rt_data = MuxCase( +// regfile(id_rt_addr), +// Seq( +// (id_rt_addr === 0.U) -> 0.U(WORD_LEN.W), +// ((id_rt_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // Forward from MEM +// ((id_rt_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // Forward from WB +// ) +// ) + +// val id_imm_i = id_inst(15, 0) +// val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i) +// val id_imm_j = Cat(id_inst(25, 0), Fill(2, 0.U(1.W))) + +// val csignals = ListLookup( +// id_inst, +// List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), +// Array( +// LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM), +// SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_X, WB_X), +// ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), +// SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), +// ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU), +// SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), +// BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), +// SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), +// JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), +// JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) +// ) +// ) + +// val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil = +// csignals + +// val id_op1_data = MuxCase( +// 0.U(WORD_LEN.W), +// Seq( +// (id_op1_sel === OP1_RS1) -> id_rs_data, +// (id_op1_sel === OP1_PC) -> id_reg_pc +// ) +// ) + +// val id_op2_data = MuxCase( +// 0.U(WORD_LEN.W), +// Seq( +// (id_op2_sel === OP2_RS2) -> id_rt_data, +// (id_op2_sel === OP2_IMI) -> id_imm_i_sext, +// (id_op2_sel === OP2_IMJ) -> id_imm_j +// ) +// ) + +// // ********* Decode/Execute (ID/EX) Stage ********* +// exe_reg_pc := id_reg_pc +// exe_reg_op1_data := id_op1_data +// exe_reg_op2_data := id_op2_data +// exe_reg_rt_data := id_rt_data +// exe_reg_wb_addr := MuxCase( +// id_rt_addr, +// Seq( +// (id_wb_sel === WB_ALU && id_inst( +// 31, +// 26 +// ) === "b000000".U) -> id_rd_addr, // R-type +// (id_inst === JAL) -> 31.U +// ) +// ) +// exe_reg_wb_sel := id_wb_sel +// exe_reg_mem_wen := id_mem_wen +// exe_reg_rf_wen := id_rf_wen +// exe_reg_imm_i_sext := id_imm_i_sext +// exe_reg_imm_j := id_imm_j +// exe_reg_exe_fun := id_exe_fun + +// // ********* Execute (EX) Stage ********* +// exe_alu_out := MuxCase( +// 0.U(WORD_LEN.W), +// Seq( +// (exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data), +// (exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data), +// (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data), +// (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data), +// (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data), +// (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data( +// 4, +// 0 +// ))(31, 0), +// (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data( +// 4, +// 0 +// )).asUInt, +// (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data( +// 4, +// 0 +// )).asUInt, +// (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt, +// (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data +// ) +// ) + +// exe_br_flg := MuxCase( +// false.B, +// Seq( +// (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data), +// (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data) +// ) +// ) + +// exe_br_target := exe_reg_pc + (exe_reg_imm_i_sext << 2.U(5.W)) +// exe_jmp_flg := (exe_reg_wb_sel === WB_PC) + +// // ********* Execute/Memory (EX/MEM) Stage ********* +// mem_reg_pc := exe_reg_pc +// mem_reg_rt_data := exe_reg_rt_data +// mem_reg_wb_addr := exe_reg_wb_addr +// mem_reg_alu_out := exe_alu_out +// mem_reg_rf_wen := exe_reg_rf_wen +// mem_reg_wb_sel := exe_reg_wb_sel +// mem_reg_mem_wen := exe_reg_mem_wen + +// // ********* Memory (MEM) Stage ********* +// io.dmem.addr := mem_reg_alu_out +// io.dmem.wen := mem_reg_mem_wen +// io.dmem.wdata := mem_reg_rt_data + +// mem_wb_data := MuxCase( +// mem_reg_alu_out, +// Seq( +// (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata, +// (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W)) +// ) +// ) + +// // ********* Memory/Write Back (MEM/WB) Stage ********* +// wb_reg_wb_data := mem_wb_data +// wb_reg_rf_wen := mem_reg_rf_wen +// wb_reg_wb_addr := mem_reg_wb_addr + +// // ********* Write Back (WB) Stage ********* +// when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) { +// regfile(wb_reg_wb_addr) := wb_reg_wb_data +// } + +// io.exit := (id_reg_inst === UNIMP) + +// // ********* Debugging ********* +// printf(p"---------------\n") +// printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") +// printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n") +// printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n") +// printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") +// printf(p"id_rs_data: 0x${Hexadecimal(id_rs_data)}\n") +// printf(p"id_rt_data: 0x${Hexadecimal(id_rt_data)}\n") +// printf(p"exe_br_flg: 0x${Hexadecimal(exe_br_flg)}\n") +// printf(p"exe_jmp_flg: 0x${Hexadecimal(exe_jmp_flg)}\n") +// printf(p"stall_flg: 0x${Hexadecimal(stall_flg)}\n") +// printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") +// printf(p"exe_reg_op1_data: 0x${Hexadecimal(exe_reg_op1_data)}\n") +// printf(p"exe_reg_op2_data: 0x${Hexadecimal(exe_reg_op2_data)}\n") +// printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n") +// printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n") +// printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") +// printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") +// printf(p"---------------\n") +// } diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala index 40d003d..aaf7b97 100755 --- a/src/main/scala/micore/Memory.scala +++ b/src/main/scala/micore/Memory.scala @@ -5,15 +5,11 @@ import chisel3.util._ import common.Consts._ import chisel3.util.experimental.loadMemoryFromFileInline -/** 表示一个指令内存端口接口的类 - */ class ImemPortIo extends Bundle { val addr = Input(UInt(WORD_LEN.W)) val inst = Output(UInt(WORD_LEN.W)) } -/** 表示一个数据内存端口接口的类 - */ class DmemPortIo extends Bundle { val addr = Input(UInt(WORD_LEN.W)) val rdata = Output(UInt(WORD_LEN.W)) @@ -27,13 +23,10 @@ class Memory extends Module { val dmem = new DmemPortIo() }) - // 生成八位宽x4096(4KB)寄存器的存储器。 val mem = Mem(4096, UInt(8.W)) - // 加载存储器的初始值。 loadMemoryFromFileInline(mem, "src/hex/mem.hex") - // 连接四个地址存储的八位数据形成一个32位的指令。 io.imem.inst := Cat( mem(io.imem.addr + 3.U(WORD_LEN.W)), mem(io.imem.addr + 2.U(WORD_LEN.W)), @@ -41,7 +34,6 @@ class Memory extends Module { mem(io.imem.addr) ) - // 连接四个地址存储的八位数据形成一个32位的数据。 io.dmem.rdata := Cat( mem(io.dmem.addr + 3.U(WORD_LEN.W)), mem(io.dmem.addr + 2.U(WORD_LEN.W)), @@ -49,7 +41,6 @@ class Memory extends Module { mem(io.dmem.addr) ) - // 写数据到存储器。 when(io.dmem.wen) { mem(io.dmem.addr) := io.dmem.wdata(7, 0) mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8) diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip index ab2e924..d09a03b 100644 Binary files a/target/scala-2.13/zinc/inc_compile_2.13.zip and b/target/scala-2.13/zinc/inc_compile_2.13.zip differ diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index 1af0b06..599b2be 100755 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -22,7 +22,7 @@ [debug] compilation cycle 1 [info] compiling 1 Scala source to /home/gh0s7/project/ddca/micore/target/scala-2.13/classes ... [debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar. -[debug] [zinc] Running cached compiler 26d066fe for Scala compiler version 2.13.12 +[debug] [zinc] Running cached compiler 205a4be3 for Scala compiler version 2.13.12 [debug] [zinc] The Scala compiler is invoked with: [debug]  -language:reflectiveCalls [debug]  -deprecation @@ -40,5 +40,5 @@ [debug] Final step, transitive dependencies: [debug]  Set() [debug] No classes were invalidated. -[debug] Scala compilation took 3.12228093 s +[debug] Scala compilation took 3.173580205 s [debug] done compiling diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir index b40fce7..878b1f0 100755 --- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -16,8 +16,8 @@ circuit TopOrigin : depth => 32 read-latency => 0 write-latency => 1 - reader => id_rs1_data_MPORT - reader => id_rs2_data_MPORT + reader => id_rs_data_MPORT + reader => id_rt_data_MPORT writer => MPORT read-under-write => undefined reg id_reg_pc : UInt<32>, clock with : @@ -32,183 +32,151 @@ circuit TopOrigin : reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 25:33] reg exe_reg_op2_data : UInt<32>, clock with : reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 26:33] - reg exe_reg_rs2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 27:33] + reg exe_reg_rs_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_rs_data) @[src/main/scala/micore/Core.scala 27:32] + reg exe_reg_rt_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 28:32] reg exe_reg_exe_fun : UInt<5>, clock with : - reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 28:32] + reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 29:32] reg exe_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 29:32] + reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 30:32] reg exe_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 30:31] + reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 31:31] reg exe_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 31:31] + reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 32:31] reg exe_reg_imm_i_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 32:35] - reg exe_reg_imm_s_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:35] - reg exe_reg_imm_b_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 34:35] - reg exe_reg_imm_u_shifted : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 35:38] + reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 33:35] + reg exe_reg_imm_j : UInt<32>, clock with : + reset => (UInt<1>("h0"), exe_reg_imm_j) @[src/main/scala/micore/Core.scala 34:30] reg mem_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 38:27] + reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:27] reg mem_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 39:32] - reg mem_reg_op1_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 40:33] - reg mem_reg_rs2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 41:33] - reg mem_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 42:32] - reg mem_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 43:31] - reg mem_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 44:31] + reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 38:32] reg mem_reg_alu_out : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 45:32] + reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 39:32] + reg mem_reg_rt_data : UInt<32>, clock with : + reset => (UInt<1>("h0"), mem_reg_rt_data) @[src/main/scala/micore/Core.scala 40:32] + reg mem_reg_mem_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 41:32] + reg mem_reg_rf_wen : UInt<2>, clock with : + reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 42:31] + reg mem_reg_wb_sel : UInt<3>, clock with : + reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 43:31] reg wb_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 48:31] + reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 46:31] reg wb_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 49:30] + reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:30] reg wb_reg_wb_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 50:31] + reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 48:31] reg if_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 53:26] - node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 63:31] - node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 63:31] - node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 90:21] - node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 85:34] - node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 90:50] - node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 90:32] - node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 90:77] - node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 90:59] - node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] - node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 86:34] - node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50] - node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] - node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77] - node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59] - node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 93:36] - node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 57:23 93:13] + reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 51:26] + node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 61:31] + node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 61:31] + node stall_flg = UInt<1>("h0") @[src/main/scala/micore/Core.scala 55:23 93:13] node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 243:34] - node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 243:15 60:25] - node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 211:24] - node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 211:58] - node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 211:58] - node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 212:24] - node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 212:58] - node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 212:58] - node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 213:24] - node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 213:58] - node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 214:24] - node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 214:57] - node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 215:24] - node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:58] - node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 216:24] - node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 216:77] - node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 216:58] - node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 219:9] - node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 220:24] - node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 220:77] - node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 220:58] - node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 224:24] - node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 224:58] - node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 224:84] - node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 224:65] - node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 227:10] - node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 228:24] - node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 228:58] - node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 228:84] - node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 228:65] - node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 229:24] - node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 229:59] - node _exe_alu_out_T_30 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_31 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_32 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_33 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_34 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_35 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_36 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_37 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_38 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_39 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 208:15 61:25] + node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34] + node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 58:25] + node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 191:24] + node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 191:58] + node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 191:58] + node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 192:24] + node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 192:58] + node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 192:58] + node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 193:24] + node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 193:58] + node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 194:24] + node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 194:57] + node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 195:24] + node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 195:58] + node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 196:24] + node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 196:77] + node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 196:58] + node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 199:9] + node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 200:24] + node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 200:77] + node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 200:58] + node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 204:24] + node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 204:58] + node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:84] + node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 204:65] + node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 207:10] + node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 208:24] + node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 208:58] + node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:84] + node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 208:65] + node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 209:24] + node _exe_alu_out_T_29 = mux(_exe_alu_out_T_28, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_30 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_31 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_32 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_33 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_32) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_34 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_33) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_35 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_34) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_36 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_37 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_38 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 188:15 59:25] node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 236:24] - node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 236:57] - node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 237:24] - node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 237:58] - node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 237:39] + node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 216:24] + node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:57] + node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 217:24] + node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:58] + node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 217:39] node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 233:14 58:24] - node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 241:31] - node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 241:31] - node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 241:17 59:27] + node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 213:14 56:24] + node _exe_br_target_T = dshl(exe_reg_imm_i_sext, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 221:53] + node _exe_br_target_T_1 = add(exe_reg_pc, _exe_br_target_T) @[src/main/scala/micore/Core.scala 221:31] + node _exe_br_target_T_2 = tail(_exe_br_target_T_1, 1) @[src/main/scala/micore/Core.scala 221:31] + node exe_br_target = bits(_exe_br_target_T_2, 31, 0) @[src/main/scala/micore/Core.scala 221:17 57:27] node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 75:19] - node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 79:19] + node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 73:19] + node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 77:19] node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20090000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_rs_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 83:31] + node id_rt_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 84:31] + node id_rd_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 85:31] + node _id_rs_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 89:21] + node _id_rs_data_hazard_T_1 = neq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 89:47] + node _id_rs_data_hazard_T_2 = and(_id_rs_data_hazard_T, _id_rs_data_hazard_T_1) @[src/main/scala/micore/Core.scala 89:32] + node _id_rs_data_hazard_T_3 = eq(id_rs_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 89:71] + node id_rs_data_hazard = and(_id_rs_data_hazard_T_2, _id_rs_data_hazard_T_3) @[src/main/scala/micore/Core.scala 89:56] + node _id_rt_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 91:21] + node _id_rt_data_hazard_T_1 = neq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 91:47] + node _id_rt_data_hazard_T_2 = and(_id_rt_data_hazard_T, _id_rt_data_hazard_T_1) @[src/main/scala/micore/Core.scala 91:32] + node _id_rt_data_hazard_T_3 = eq(id_rt_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 91:71] + node id_rt_data_hazard = and(_id_rt_data_hazard_T_2, _id_rt_data_hazard_T_3) @[src/main/scala/micore/Core.scala 91:56] node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 96:21] node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 96:36] - node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8] - node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 98:28] - node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 99:28] - node _id_wb_addr_T = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 102:12] - node _id_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 104:15] - node _id_wb_addr_T_2 = eq(_id_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 104:24] - node _id_wb_addr_T_3 = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 104:51] - node _id_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 108:16] - node _id_wb_addr_T_5 = eq(UInt<28>("hc000000"), _id_wb_addr_T_4) @[src/main/scala/micore/Core.scala 108:16] - node _id_wb_addr_T_6 = mux(_id_wb_addr_T_5, UInt<5>("h1f"), _id_wb_addr_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_wb_addr = mux(_id_wb_addr_T_2, _id_wb_addr_T_3, _id_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20] - node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21] - node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61] - node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 117:42] - node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] - node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59] - node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 118:41] - node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 263:23] - node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 264:23] - node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 264:49] - node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 264:49] - node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 112:25 260:15] - node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_wb_data, _id_rs1_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 124:20] - node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 125:21] - node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 125:61] - node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 125:42] - node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 126:21] - node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 126:59] - node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 126:41] - node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_wb_data, _id_rs2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 130:25] - node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 131:44] - node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 131:31] - node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 131:26] - node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 133:12] - node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 132:21] - node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 136:44] - node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 136:31] - node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 136:26] - node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 138:12] - node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 137:21] - node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 141:43] - node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 141:31] - node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 141:26] - node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 142:25] - node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 143:44] - node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 143:29] - node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 144:29] + node id_inst = mux(_id_inst_T_1, UInt<32>("h20090000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8] + node _id_rs_data_T = eq(id_rs_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:19] + node _id_rs_data_T_1 = eq(id_rs_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 102:20] + node _id_rs_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 102:60] + node _id_rs_data_T_3 = and(_id_rs_data_T_1, _id_rs_data_T_2) @[src/main/scala/micore/Core.scala 102:41] + node _id_rs_data_T_4 = eq(id_rs_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 103:20] + node _id_rs_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 103:58] + node _id_rs_data_T_6 = and(_id_rs_data_T_4, _id_rs_data_T_5) @[src/main/scala/micore/Core.scala 103:40] + node _id_rs_data_T_7 = mux(_id_rs_data_T_6, wb_reg_wb_data, regfile.id_rs_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rs_data_T_8 = mux(_id_rs_data_T_3, mem_reg_alu_out, _id_rs_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_rs_data = mux(_id_rs_data_T, UInt<32>("h0"), _id_rs_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rt_data_T = eq(id_rt_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 109:19] + node _id_rt_data_T_1 = eq(id_rt_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:20] + node _id_rt_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:60] + node _id_rt_data_T_3 = and(_id_rt_data_T_1, _id_rt_data_T_2) @[src/main/scala/micore/Core.scala 110:41] + node _id_rt_data_T_4 = eq(id_rt_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 111:20] + node _id_rt_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 111:58] + node _id_rt_data_T_6 = and(_id_rt_data_T_4, _id_rt_data_T_5) @[src/main/scala/micore/Core.scala 111:40] + node _id_rt_data_T_7 = mux(_id_rt_data_T_6, wb_reg_wb_data, regfile.id_rt_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rt_data_T_8 = mux(_id_rt_data_T_3, mem_reg_alu_out, _id_rt_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_rt_data = mux(_id_rt_data_T, UInt<32>("h0"), _id_rt_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 115:25] + node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 116:44] + node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 116:31] + node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 116:26] + node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 117:29] + node _id_imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/micore/Core.scala 117:42] + node id_imm_j = cat(_id_imm_j_T, _id_imm_j_T_1) @[src/main/scala/micore/Core.scala 117:21] node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -241,256 +209,234 @@ circuit TopOrigin : node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_32 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_34 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_35 = eq(UInt<28>("hc000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_36 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_37 = eq(UInt<30>("h20000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_38 = mux(_csignals_T_37, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_39 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_40 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_41 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_42 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_43 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_44 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_45 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_46 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_47 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_48 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_49 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_50 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_51 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_52 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_53 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_54 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_55 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_56 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_57 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_58 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_59 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_60 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_61 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_62 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_63 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_64 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_65 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_66 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_67 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_68 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_69 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_70 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_71 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_72 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_73 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_74 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_75 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_76 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_77 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_78 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_79 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_80 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_81 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_82 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_83 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_84 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_85 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_86 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_87 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_88 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_89 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_90 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_91 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_92 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_93 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_94 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_95 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_96 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_97 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_98 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_99 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_100 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_101 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_102 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_103 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_104 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_105 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_106 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_107 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_108 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_109 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_110 = mux(_csignals_T_37, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_111 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_112 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_113 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_114 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_115 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_116 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_117 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_118 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_119 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_120 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_121 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_122 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_123 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_124 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_125 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_126 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_127 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_128 = mux(_csignals_T_37, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_129 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_130 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_131 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_132 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_133 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_134 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_135 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_136 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_137 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_138 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_139 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_140 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_141 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_142 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_143 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_144 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_145 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 178:19] - node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 179:19] + node _csignals_T_32 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_38 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_39 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_40 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_41 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_42 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_43 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_44 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_45 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_46 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_47 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_48 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_49 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_50 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_56 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_57 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_58 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_59 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_60 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_61 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_62 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_63 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_64 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_65 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_66 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_67 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_71 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_72 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_73 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_74 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_75 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_76 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_77 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_78 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_79 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_80 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_81 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_82 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_83 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_84 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_90 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_91 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_92 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_93 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_94 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_95 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_96 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_97 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_98 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_99 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_100 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_101 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_102 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_103 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_104 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_105 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_106 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_107 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_108 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_109 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_110 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_111 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_112 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_113 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_114 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_115 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_116 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_117 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_118 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_119 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_120 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_121 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_122 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_123 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_124 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_125 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_126 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_127 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_128 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_129 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_130 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_131 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_132 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_133 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_134 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_135 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 150:19] + node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 151:19] node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 186:19] - node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 187:19] - node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 188:19] - node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 189:19] - node _id_op2_data_T_4 = mux(_id_op2_data_T_3, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T_5 = mux(_id_op2_data_T_2, id_imm_j_sext, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T_6 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 275:22] - node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:50] - node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 275:32] - node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 275:59 276:12] - node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 275:59 276:12] - node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:59 276:12 15:20] - node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 275:59 276:29] - node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 275:59 276:29] - node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 280:27] - node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9] - node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9] - node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9] - node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] - node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] - node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] - node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] - node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] - node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] - node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] - node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] - node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] - node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9] - node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9] - node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9] - node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9] - node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9] - node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9] - node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9] - node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9] - node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9] - node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9] - node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9] - node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9] - node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9] - node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9] - node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9] - node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9] - io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 54:16] - io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 256:16] - io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 257:15] - io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 258:17] - io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 280:11] - regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 114:12] - regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12] - regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12] - regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:12] - regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 122:12] - regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:12] + node id_op1_data = mux(_id_op1_data_T, id_rs_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 158:19] + node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 159:19] + node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 160:19] + node _id_op2_data_T_3 = mux(_id_op2_data_T_2, id_imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_op2_data_T_4 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_op2_data = mux(_id_op2_data_T, id_rt_data, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_reg_wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 173:18] + node _exe_reg_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 173:39] + node _exe_reg_wb_addr_T_2 = eq(_exe_reg_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 176:9] + node _exe_reg_wb_addr_T_3 = and(_exe_reg_wb_addr_T, _exe_reg_wb_addr_T_2) @[src/main/scala/micore/Core.scala 173:29] + node _exe_reg_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 177:16] + node _exe_reg_wb_addr_T_5 = eq(UInt<28>("hc000000"), _exe_reg_wb_addr_T_4) @[src/main/scala/micore/Core.scala 177:16] + node _exe_reg_wb_addr_T_6 = mux(_exe_reg_wb_addr_T_5, UInt<5>("h1f"), id_rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_reg_wb_addr_T_7 = mux(_exe_reg_wb_addr_T_3, id_rd_addr, _exe_reg_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 241:23] + node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 242:23] + node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 242:49] + node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 242:49] + node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node mem_wb_data = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 252:22] + node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:50] + node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 252:32] + node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 252:59 253:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 252:59 253:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 252:59 253:12 15:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 252:59 253:29] + node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 252:59 253:29] + node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 256:27] + node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 259:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 259:9] + node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 260:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 260:9] + node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 261:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 261:9] + node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 262:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 262:9] + node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 263:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 263:9] + node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 264:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 264:9] + node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 265:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 265:9] + node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 266:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 266:9] + node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 267:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 267:9] + node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 268:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 268:9] + io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 52:16] + io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16] + io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15] + io_dmem_wdata <= mem_reg_rt_data @[src/main/scala/micore/Core.scala 236:17] + io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 256:11] + regfile.id_rs_data_MPORT.addr <= id_rs_addr @[src/main/scala/micore/Core.scala 99:12] + regfile.id_rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 99:12] + regfile.id_rs_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 99:12] + regfile.id_rt_data_MPORT.addr <= id_rt_addr @[src/main/scala/micore/Core.scala 107:12] + regfile.id_rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 107:12] + regfile.id_rt_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 107:12] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 75:13] - id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 76:15] - exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 194:14 23:{27,27}] - exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 198:19 24:{32,32}] - exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 195:20 25:{33,33}] - exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 196:20 26:{33,33}] - exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 197:20 27:{33,33}] - exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 205:19 28:{32,32}] - exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 200:19 29:{32,32}] - exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 201:18 30:{31,31}] - exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 199:18 31:{31,31}] - exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 202:22 32:{35,35}] - exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:{35,35,35}] - exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 203:22 34:{35,35}] - exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 204:25 35:{38,38}] - mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 246:14 38:{27,27}] - mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 249:19 39:{32,32}] - mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 247:20 40:{33,33}] - mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 248:20 41:{33,33}] - mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 253:19 42:{32,32}] - mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 251:18 43:{31,31}] - mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 252:18 44:{31,31}] - mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 250:19 45:{32,32}] - wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:18 48:{31,31}] - wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 270:17 49:{30,30}] - wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 269:18 50:{31,31}] - if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 53:{26,26} 72:13] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 281:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 282:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 283:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 284:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 285:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 286:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 287:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 288:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 289:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 290:9] - printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 291:9] - printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 292:9] - printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 293:9] - printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 294:9] - printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 295:9] - printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 296:9] - printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 297:9] - printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 298:9] + id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 73:13] + id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 74:15] + exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 165:14 23:{27,27}] + exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), _exe_reg_wb_addr_T_7) @[src/main/scala/micore/Core.scala 170:19 24:{32,32}] + exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 166:20 25:{33,33}] + exe_reg_op2_data <= mux(reset, UInt<32>("h0"), id_op2_data) @[src/main/scala/micore/Core.scala 167:20 26:{33,33}] + exe_reg_rs_data <= mux(reset, UInt<32>("h0"), id_rs_data) @[src/main/scala/micore/Core.scala 168:19 27:{32,32}] + exe_reg_rt_data <= mux(reset, UInt<32>("h0"), id_rt_data) @[src/main/scala/micore/Core.scala 169:19 28:{32,32}] + exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 185:19 29:{32,32}] + exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 181:19 30:{32,32}] + exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 182:18 31:{31,31}] + exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 180:18 32:{31,31}] + exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 183:22 33:{35,35}] + exe_reg_imm_j <= mux(reset, UInt<32>("h0"), id_imm_j) @[src/main/scala/micore/Core.scala 184:17 34:{30,30}] + mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 225:14 37:{27,27}] + mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 226:19 38:{32,32}] + mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 227:19 39:{32,32}] + mem_reg_rt_data <= mux(reset, UInt<32>("h0"), exe_reg_rt_data) @[src/main/scala/micore/Core.scala 228:19 40:{32,32}] + mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 229:19 41:{32,32}] + mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 230:18 42:{31,31}] + mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 231:18 43:{31,31}] + wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 247:18 46:{31,31}] + wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 248:17 47:{30,30}] + wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 249:18 48:{31,31}] + if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 51:{26,26} 70:13] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/micore/Core.scala 259:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 260:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 261:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 262:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_4 @[src/main/scala/micore/Core.scala 263:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_5 @[src/main/scala/micore/Core.scala 264:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_6 @[src/main/scala/micore/Core.scala 265:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_7 @[src/main/scala/micore/Core.scala 266:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_8 @[src/main/scala/micore/Core.scala 267:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "---------------\n") : printf_9 @[src/main/scala/micore/Core.scala 268:9] - module Memory : @[src/main/scala/micore/Memory.scala 24:7] - input clock : Clock @[src/main/scala/micore/Memory.scala 24:7] - input reset : UInt<1> @[src/main/scala/micore/Memory.scala 24:7] - input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] - output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] - input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] - output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] - input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 25:14] - input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] + module Memory : @[src/main/scala/micore/Memory.scala 20:7] + input clock : Clock @[src/main/scala/micore/Memory.scala 20:7] + input reset : UInt<1> @[src/main/scala/micore/Memory.scala 20:7] + input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 21:14] + input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14] - mem mem : @[src/main/scala/micore/Memory.scala 31:16] + mem mem : @[src/main/scala/micore/Memory.scala 26:16] data-type => UInt<8> depth => 4096 read-latency => 0 @@ -508,83 +454,83 @@ circuit TopOrigin : writer => MPORT_2 writer => MPORT_3 read-under-write => undefined - node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 38:22] - node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 38:22] - node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 38:8] - node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 39:22] - node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 39:22] - node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 39:8] - node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 40:22] - node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 40:22] - node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 40:8] - node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 41:8] - node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 37:22] - node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 37:22] - node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 37:22] - node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 46:22] - node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 46:22] - node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 46:8] - node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 47:22] - node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 47:22] - node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 47:8] - node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 48:22] - node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 48:22] - node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 48:8] - node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 49:8] - node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 45:23] - node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 45:23] - node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 45:23] - node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 54:8] - node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 54:39] - node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 55:22] - node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 55:22] - node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 55:8] - node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 55:57] - node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 56:22] - node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 56:22] - node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 56:8] - node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 56:57] - node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 57:22] - node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 57:22] - node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 57:8] - node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 57:57] - node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 53:21 54:8] - node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 53:21 54:8] - node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 31:16 53:21 54:8] - node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 53:21 54:23] - node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 53:21 54:23] - node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 53:21 55:8] - node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 53:21 55:41] - node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 53:21 56:8] - node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 53:21 56:41] - node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 53:21 57:8] - node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 53:21 57:41] - io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 37:16] - io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 45:17] - mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 38:8] - mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 38:8] - mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 38:8] - mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 41:8] - mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 49:8] + node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 31:22] + node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 31:22] + node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 31:8] + node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 32:22] + node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 32:22] + node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 32:8] + node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 33:22] + node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 33:22] + node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 33:8] + node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 34:8] + node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 30:22] + node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 30:22] + node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 30:22] + node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 38:22] + node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 38:22] + node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 38:8] + node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 39:22] + node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 39:22] + node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 39:8] + node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 40:22] + node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 40:22] + node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 40:8] + node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 41:8] + node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 37:23] + node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 37:23] + node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 37:23] + node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 45:8] + node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 45:39] + node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 46:22] + node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 46:22] + node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 46:8] + node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 46:57] + node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 47:22] + node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 47:22] + node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 47:8] + node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 47:57] + node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 48:22] + node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 48:22] + node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 48:8] + node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 48:57] + node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 44:21 45:8] + node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 44:21 45:8] + node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 26:16 44:21 45:8] + node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 44:21 45:23] + node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 44:21 45:23] + node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 44:21 46:8] + node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 44:21 46:41] + node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 44:21 47:8] + node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 44:21 47:41] + node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 44:21 48:8] + node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 44:21 48:41] + io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 30:16] + io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 37:17] + mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 31:8] + mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 31:8] + mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 31:8] + mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 34:8] + mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 34:8] + mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 34:8] + mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 41:8] mem.MPORT.addr <= _GEN_0 mem.MPORT.en <= _GEN_2 mem.MPORT.clk <= _GEN_1 diff --git a/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir index 366d2f3..27a8fe7 100755 --- a/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir @@ -11,7 +11,7 @@ circuit TopOrigin : output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 10:14] - mem regfile : @[src/main/scala/sicore/Core.scala 17:20] + mem regfile : @[src/main/scala/sicore/Core.scala 16:20] data-type => UInt<32> depth => 32 read-latency => 0 @@ -22,14 +22,14 @@ circuit TopOrigin : writer => MPORT read-under-write => undefined reg pc_reg : UInt<32>, clock with : - reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 20:23] - node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 23:25] - node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 23:25] - node _jmp_flg_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 26:23] - node _jmp_flg_T_1 = eq(UInt<28>("hc000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 26:23] - node _jmp_flg_T_2 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/sicore/Core.scala 26:39] - node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 26:39] - node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 26:31] + reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 19:23] + node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 22:25] + node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 22:25] + node _jmp_flg_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 25:23] + node _jmp_flg_T_1 = eq(UInt<28>("hc000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 25:23] + node _jmp_flg_T_2 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/sicore/Core.scala 25:39] + node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 25:39] + node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 25:31] node _csignals_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_2 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -84,7 +84,7 @@ circuit TopOrigin : node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 98:16] + node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 97:16] node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -103,11 +103,11 @@ circuit TopOrigin : node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 80:16] - node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 40:21] - node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30] - node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20] - node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 81:16] + node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 79:16] + node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 39:21] + node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 42:30] + node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 42:20] + node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 80:16] node _op1_data_T_2 = mux(_op1_data_T_1, pc_reg, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node op1_data = mux(_op1_data_T, rs_data, _op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -128,50 +128,50 @@ circuit TopOrigin : node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 88:16] - node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 41:21] - node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 44:30] - node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 44:20] - node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 89:16] - node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 45:19] - node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 46:38] - node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 46:28] - node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 46:23] - node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 90:16] - node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 47:23] - node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 47:36] - node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 47:18] + node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 87:16] + node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 40:21] + node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30] + node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20] + node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 88:16] + node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 44:19] + node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 45:38] + node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 45:28] + node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 45:23] + node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 89:16] + node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 46:23] + node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 46:36] + node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 46:18] node _op2_data_T_3 = mux(_op2_data_T_2, imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _op2_data_T_4 = mux(_op2_data_T_1, imm_i_sext, _op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] node op2_data = mux(_op2_data_T, rt_data, _op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42] - node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 98:42] - node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 99:16] - node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42] - node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 99:42] - node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 100:16] - node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:42] - node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 101:16] - node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:41] - node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 102:16] - node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 102:42] - node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 103:16] - node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53] - node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 103:42] - node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 103:60] - node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 104:16] - node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:53] - node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 104:42] - node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 105:16] - node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42] - node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 105:60] - node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 105:49] - node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 105:68] - node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 106:16] - node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 106:42] - node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 106:60] - node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 106:49] - node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 107:16] + node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 97:42] + node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 97:42] + node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 98:16] + node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 99:16] + node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42] + node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 100:16] + node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:41] + node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 101:16] + node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:42] + node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 102:16] + node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 102:53] + node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 102:42] + node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 102:60] + node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 103:16] + node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53] + node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 103:42] + node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 104:16] + node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 104:42] + node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:60] + node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 104:49] + node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 104:68] + node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 105:16] + node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42] + node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 105:60] + node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 105:49] + node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 106:16] node _alu_out_T_29 = mux(_alu_out_T_28, op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_30 = mux(_alu_out_T_24, _alu_out_T_27, _alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_31 = mux(_alu_out_T_19, _alu_out_T_23, _alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] @@ -182,22 +182,22 @@ circuit TopOrigin : node _alu_out_T_36 = mux(_alu_out_T_6, _alu_out_T_7, _alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_37 = mux(_alu_out_T_3, _alu_out_T_5, _alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_38 = mux(_alu_out_T, _alu_out_T_2, _alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 27:21 95:11] + node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 26:21 94:11] node _pc_next_T = mux(jmp_flg, alu_out, pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 114:16] - node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:41] - node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 115:16] - node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 115:42] - node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 115:31] + node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 113:16] + node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 113:41] + node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 114:16] + node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:42] + node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 114:31] node _br_flg_T_5 = mux(_br_flg_T_2, _br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _br_flg_T_6 = mux(_br_flg_T, _br_flg_T_1, _br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 111:10 24:20] - node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 120:37] - node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 120:23] - node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 120:23] - node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 120:13 25:23] + node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 110:10 23:20] + node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 119:37] + node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 119:23] + node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 119:23] + node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 119:13 24:23] node pc_next = mux(br_flg, br_target, _pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 42:21] + node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 41:21] node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -252,101 +252,101 @@ circuit TopOrigin : node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 131:15] - node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 132:15] + node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 130:15] + node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 131:15] node _wb_data_T_2 = mux(_wb_data_T_1, pc_plus4, alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] node wb_data = mux(_wb_data_T, io_dmem_rdata, _wb_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 140:15] - node _wb_addr_T_1 = bits(io_imem_inst, 31, 26) @[src/main/scala/sicore/Core.scala 140:33] - node _wb_addr_T_2 = eq(_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 140:42] - node _wb_addr_T_3 = and(_wb_addr_T, _wb_addr_T_2) @[src/main/scala/sicore/Core.scala 140:26] - node _wb_addr_T_4 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 141:13] - node _wb_addr_T_5 = eq(UInt<28>("hc000000"), _wb_addr_T_4) @[src/main/scala/sicore/Core.scala 141:13] + node _wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 138:15] + node _wb_addr_T_1 = bits(io_imem_inst, 31, 26) @[src/main/scala/sicore/Core.scala 138:33] + node _wb_addr_T_2 = eq(_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 138:42] + node _wb_addr_T_3 = and(_wb_addr_T, _wb_addr_T_2) @[src/main/scala/sicore/Core.scala 138:26] + node _wb_addr_T_4 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 139:13] + node _wb_addr_T_5 = eq(UInt<28>("hc000000"), _wb_addr_T_4) @[src/main/scala/sicore/Core.scala 139:13] node _wb_addr_T_6 = mux(_wb_addr_T_5, UInt<5>("h1f"), rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16] node wb_addr = mux(_wb_addr_T_3, rd_addr, _wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 146:15] - node _T_1 = neq(wb_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:36] - node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 146:25] - node _GEN_0 = validif(_T_2, wb_addr) @[src/main/scala/sicore/Core.scala 146:45 147:12] - node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 146:45 147:12] - node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:45 147:12 17:20] - node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 146:45 147:22] - node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 146:45 147:22] - node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 150:20] - node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 153:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 153:9] - node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 154:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 154:9] - node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 155:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 155:9] - node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 156:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 156:9] - node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 157:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 157:9] - node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 158:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 158:9] - node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 159:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 159:9] - node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 160:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 160:9] - node _T_19 = asUInt(reset) @[src/main/scala/sicore/Core.scala 161:9] - node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 161:9] - node _T_21 = asUInt(reset) @[src/main/scala/sicore/Core.scala 162:9] - node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 162:9] - node _T_23 = asUInt(reset) @[src/main/scala/sicore/Core.scala 164:9] - node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 164:9] - node _T_25 = asUInt(reset) @[src/main/scala/sicore/Core.scala 165:9] - node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 165:9] - node _T_27 = asUInt(reset) @[src/main/scala/sicore/Core.scala 166:9] - node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 166:9] - node _T_29 = asUInt(reset) @[src/main/scala/sicore/Core.scala 167:9] - node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 167:9] - io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 21:16] - io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 123:16] - io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 124:15] - io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 125:17] - io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 150:11] - regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 43:47] - regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47] - regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47] - regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 44:47] - regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 44:47] - regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 44:47] - regfile.MPORT_1.addr <= rt_addr @[src/main/scala/sicore/Core.scala 161:40] - regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 161:40] - regfile.MPORT_1.clk <= clock @[src/main/scala/sicore/Core.scala 161:40] + node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 143:15] + node _T_1 = neq(wb_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:36] + node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 143:25] + node _GEN_0 = validif(_T_2, wb_addr) @[src/main/scala/sicore/Core.scala 143:45 144:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 143:45 144:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:45 144:12 16:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 143:45 144:22] + node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 143:45 144:22] + node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 147:20] + node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 150:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 150:9] + node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 151:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 151:9] + node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 152:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 152:9] + node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 153:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 153:9] + node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 154:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 154:9] + node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 155:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 155:9] + node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 156:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 156:9] + node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 157:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 157:9] + node _T_19 = asUInt(reset) @[src/main/scala/sicore/Core.scala 158:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 158:9] + node _T_21 = asUInt(reset) @[src/main/scala/sicore/Core.scala 159:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 159:9] + node _T_23 = asUInt(reset) @[src/main/scala/sicore/Core.scala 161:9] + node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 161:9] + node _T_25 = asUInt(reset) @[src/main/scala/sicore/Core.scala 162:9] + node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 162:9] + node _T_27 = asUInt(reset) @[src/main/scala/sicore/Core.scala 163:9] + node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 163:9] + node _T_29 = asUInt(reset) @[src/main/scala/sicore/Core.scala 164:9] + node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 164:9] + io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 20:16] + io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 122:16] + io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 123:15] + io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 124:17] + io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 147:11] + regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 42:47] + regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 42:47] + regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 42:47] + regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 43:47] + regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47] + regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47] + regfile.MPORT_1.addr <= rt_addr @[src/main/scala/sicore/Core.scala 158:40] + regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 158:40] + regfile.MPORT_1.clk <= clock @[src/main/scala/sicore/Core.scala 158:40] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 20:{23,23} 37:10] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 153:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.imem.inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 154:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst) : printf_2 @[src/main/scala/sicore/Core.scala 155:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_3 @[src/main/scala/sicore/Core.scala 156:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_fun: 0x%x\n", csignals_0) : printf_4 @[src/main/scala/sicore/Core.scala 157:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_5 @[src/main/scala/sicore/Core.scala 158:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "rt_addr: 0x%x\n", rt_addr) : printf_6 @[src/main/scala/sicore/Core.scala 159:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_7 @[src/main/scala/sicore/Core.scala 160:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "reg: 0x%x\n", regfile.MPORT_1.data) : printf_8 @[src/main/scala/sicore/Core.scala 161:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "rf_wen: 0x%x\n", csignals_4) : printf_9 @[src/main/scala/sicore/Core.scala 162:9] - printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_10 @[src/main/scala/sicore/Core.scala 164:9] - printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "rt_data: 0x%x\n", rt_data) : printf_11 @[src/main/scala/sicore/Core.scala 165:9] - printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_12 @[src/main/scala/sicore/Core.scala 166:9] - printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------\n") : printf_13 @[src/main/scala/sicore/Core.scala 167:9] + pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 19:{23,23} 36:10] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 150:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.imem.inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 151:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst) : printf_2 @[src/main/scala/sicore/Core.scala 152:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_3 @[src/main/scala/sicore/Core.scala 153:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_fun: 0x%x\n", csignals_0) : printf_4 @[src/main/scala/sicore/Core.scala 154:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_5 @[src/main/scala/sicore/Core.scala 155:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "rt_addr: 0x%x\n", rt_addr) : printf_6 @[src/main/scala/sicore/Core.scala 156:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_7 @[src/main/scala/sicore/Core.scala 157:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "reg: 0x%x\n", regfile.MPORT_1.data) : printf_8 @[src/main/scala/sicore/Core.scala 158:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "rf_wen: 0x%x\n", csignals_4) : printf_9 @[src/main/scala/sicore/Core.scala 159:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_10 @[src/main/scala/sicore/Core.scala 161:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "rt_data: 0x%x\n", rt_data) : printf_11 @[src/main/scala/sicore/Core.scala 162:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_12 @[src/main/scala/sicore/Core.scala 163:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------\n") : printf_13 @[src/main/scala/sicore/Core.scala 164:9] - module Memory : @[src/main/scala/sicore/Memory.scala 24:7] - input clock : Clock @[src/main/scala/sicore/Memory.scala 24:7] - input reset : UInt<1> @[src/main/scala/sicore/Memory.scala 24:7] - input io_imem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] - output io_imem_inst : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] - input io_dmem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] - output io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] - input io_dmem_wen : UInt<1> @[src/main/scala/sicore/Memory.scala 25:14] - input io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Memory.scala 25:14] + module Memory : @[src/main/scala/sicore/Memory.scala 20:7] + input clock : Clock @[src/main/scala/sicore/Memory.scala 20:7] + input reset : UInt<1> @[src/main/scala/sicore/Memory.scala 20:7] + input io_imem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 21:14] + output io_imem_inst : UInt<32> @[src/main/scala/sicore/Memory.scala 21:14] + input io_dmem_addr : UInt<32> @[src/main/scala/sicore/Memory.scala 21:14] + output io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Memory.scala 21:14] + input io_dmem_wen : UInt<1> @[src/main/scala/sicore/Memory.scala 21:14] + input io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Memory.scala 21:14] - mem mem : @[src/main/scala/sicore/Memory.scala 31:16] + mem mem : @[src/main/scala/sicore/Memory.scala 26:16] data-type => UInt<8> depth => 4096 read-latency => 0 @@ -364,83 +364,83 @@ circuit TopOrigin : writer => MPORT_2 writer => MPORT_3 read-under-write => undefined - node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 38:22] - node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/sicore/Memory.scala 38:22] - node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 38:8] - node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 39:22] - node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/sicore/Memory.scala 39:22] - node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 39:8] - node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 40:22] - node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/sicore/Memory.scala 40:22] - node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 40:8] - node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 41:8] - node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 37:22] - node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 37:22] - node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/sicore/Memory.scala 37:22] - node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 46:22] - node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/sicore/Memory.scala 46:22] - node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 46:8] - node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 47:22] - node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/sicore/Memory.scala 47:22] - node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 47:8] - node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 48:22] - node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/sicore/Memory.scala 48:22] - node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 48:8] - node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 49:8] - node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 45:23] - node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 45:23] - node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/sicore/Memory.scala 45:23] - node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 54:8] - node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/sicore/Memory.scala 54:39] - node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 55:22] - node _T_3 = tail(_T_2, 1) @[src/main/scala/sicore/Memory.scala 55:22] - node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/sicore/Memory.scala 55:8] - node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/sicore/Memory.scala 55:57] - node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 56:22] - node _T_7 = tail(_T_6, 1) @[src/main/scala/sicore/Memory.scala 56:22] - node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 56:8] - node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/sicore/Memory.scala 56:57] - node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 57:22] - node _T_11 = tail(_T_10, 1) @[src/main/scala/sicore/Memory.scala 57:22] - node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/sicore/Memory.scala 57:8] - node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/sicore/Memory.scala 57:57] - node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/sicore/Memory.scala 53:21 54:8] - node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/sicore/Memory.scala 53:21 54:8] - node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Memory.scala 31:16 53:21 54:8] - node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/sicore/Memory.scala 53:21 54:23] - node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/sicore/Memory.scala 53:21 54:23] - node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/sicore/Memory.scala 53:21 55:8] - node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/sicore/Memory.scala 53:21 55:41] - node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/sicore/Memory.scala 53:21 56:8] - node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/sicore/Memory.scala 53:21 56:41] - node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/sicore/Memory.scala 53:21 57:8] - node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/sicore/Memory.scala 53:21 57:41] - io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/sicore/Memory.scala 37:16] - io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/sicore/Memory.scala 45:17] - mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/sicore/Memory.scala 38:8] - mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 38:8] - mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 38:8] - mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/sicore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/sicore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/sicore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 41:8] - mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/sicore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 46:8] - mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/sicore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/sicore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/sicore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 49:8] + node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 31:22] + node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/sicore/Memory.scala 31:22] + node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 31:8] + node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 32:22] + node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/sicore/Memory.scala 32:22] + node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 32:8] + node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 33:22] + node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/sicore/Memory.scala 33:22] + node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 33:8] + node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 34:8] + node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 30:22] + node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 30:22] + node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/sicore/Memory.scala 30:22] + node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 38:22] + node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/sicore/Memory.scala 38:22] + node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/sicore/Memory.scala 38:8] + node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 39:22] + node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/sicore/Memory.scala 39:22] + node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/sicore/Memory.scala 39:8] + node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 40:22] + node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/sicore/Memory.scala 40:22] + node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 40:8] + node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 41:8] + node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/sicore/Memory.scala 37:23] + node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/sicore/Memory.scala 37:23] + node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/sicore/Memory.scala 37:23] + node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/sicore/Memory.scala 45:8] + node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/sicore/Memory.scala 45:39] + node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/sicore/Memory.scala 46:22] + node _T_3 = tail(_T_2, 1) @[src/main/scala/sicore/Memory.scala 46:22] + node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/sicore/Memory.scala 46:8] + node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/sicore/Memory.scala 46:57] + node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/sicore/Memory.scala 47:22] + node _T_7 = tail(_T_6, 1) @[src/main/scala/sicore/Memory.scala 47:22] + node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/sicore/Memory.scala 47:8] + node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/sicore/Memory.scala 47:57] + node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/sicore/Memory.scala 48:22] + node _T_11 = tail(_T_10, 1) @[src/main/scala/sicore/Memory.scala 48:22] + node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/sicore/Memory.scala 48:8] + node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/sicore/Memory.scala 48:57] + node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/sicore/Memory.scala 44:21 45:8] + node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/sicore/Memory.scala 44:21 45:8] + node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Memory.scala 26:16 44:21 45:8] + node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/sicore/Memory.scala 44:21 45:23] + node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/sicore/Memory.scala 44:21 45:23] + node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/sicore/Memory.scala 44:21 46:8] + node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/sicore/Memory.scala 44:21 46:41] + node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/sicore/Memory.scala 44:21 47:8] + node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/sicore/Memory.scala 44:21 47:41] + node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/sicore/Memory.scala 44:21 48:8] + node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/sicore/Memory.scala 44:21 48:41] + io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/sicore/Memory.scala 30:16] + io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/sicore/Memory.scala 37:17] + mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/sicore/Memory.scala 31:8] + mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 31:8] + mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 31:8] + mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/sicore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 32:8] + mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/sicore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 33:8] + mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/sicore/Memory.scala 34:8] + mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 34:8] + mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 34:8] + mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/sicore/Memory.scala 38:8] + mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/sicore/Memory.scala 39:8] + mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/sicore/Memory.scala 40:8] + mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/sicore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/sicore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/sicore/Memory.scala 41:8] mem.MPORT.addr <= _GEN_0 mem.MPORT.en <= _GEN_2 mem.MPORT.clk <= _GEN_1