From c5eba630857c406f7b8464b2dc77304540c6a2d6 Mon Sep 17 00:00:00 2001 From: CGH0S7 <776459475@qq.com> Date: Tue, 31 Dec 2024 09:28:33 +0800 Subject: [PATCH] Fix bugs in Sicore --- TopOrigin.sv | 147 +++--- .../scala-2.12/sbt-1.0/sync/copy-resource | 1 - .../sbt-1.0/update/update_cache_2.12/inputs | 1 - .../sbt-1.0/update/update_cache_2.12/output | 1 - .../_global/_global/_global/streams/out | 0 .../csrConfiguration/_global/streams/out | 0 .../_global/csrProject/_global/streams/out | 0 .../streams/update_cache_2.12/input_dsp | 1 - .../streams/update_cache_2.12/output_dsp | 1 - .../ivyConfiguration/_global/streams/out | 0 .../_global/ivySbt/_global/streams/out | 0 .../moduleSettings/_global/streams/out | 0 .../projectDescriptors/_global/streams/out | 0 .../_global/streams/out | 0 .../_global/update/_global/streams/out | 3 - .../_global/_global/compileOutputs/previous | 1 - .../_global/discoveredMainClasses/data | 1 - .../compile/bspReporter/_global/streams/out | 0 .../compile/compile/_global/streams/out | 0 .../compileIncremental/_global/streams/export | 0 .../compileIncremental/_global/streams/out | 6 - .../compile/copyResources/_global/streams/out | 2 - .../_global/streams/export | 1 - .../exportedProducts/_global/streams/export | 1 - .../_global/streams/export | 1 - .../compile/incOptions/_global/streams/out | 5 - .../_global/streams/export | 1 - .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 1 - .../compile/scalacOptions/_global/streams/out | 0 .../unmanagedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 1 - .../_global/streams/export | 1 - .../exportedProducts/_global/streams/export | 1 - .../_global/streams/export | 1 - .../fullClasspath/_global/streams/export | 1 - .../_global/streams/export | 1 - .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 1 - ...2fb4.cache => $6080031bccf8a03d91ba.cache} | 0 ...a68a.cache => $9fddc3a6676a1ed50a85.cache} | 0 .../scala-2.12/sbt-1.0/sync/copy-resource | 1 - .../sbt-1.0/update/update_cache_2.12/inputs | 1 - .../sbt-1.0/update/update_cache_2.12/output | 1 - .../_global/_global/_global/streams/out | 0 .../csrConfiguration/_global/streams/out | 0 .../_global/csrProject/_global/streams/out | 0 .../streams/update_cache_2.12/input_dsp | 1 - .../streams/update_cache_2.12/output_dsp | 1 - .../ivyConfiguration/_global/streams/out | 0 .../_global/ivySbt/_global/streams/out | 0 .../moduleSettings/_global/streams/out | 0 .../projectDescriptors/_global/streams/out | 0 .../_global/streams/out | 0 .../_global/update/_global/streams/out | 3 - .../_global/_global/compileOutputs/previous | 1 - .../_global/discoveredMainClasses/data | 1 - .../compile/bspReporter/_global/streams/out | 0 .../compile/compile/_global/streams/out | 0 .../compileIncremental/_global/streams/export | 0 .../compileIncremental/_global/streams/out | 6 - .../compile/copyResources/_global/streams/out | 2 - .../_global/streams/export | 1 - .../exportedProducts/_global/streams/export | 1 - .../_global/streams/export | 1 - .../compile/incOptions/_global/streams/out | 5 - .../_global/streams/export | 1 - .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 1 - .../compile/scalacOptions/_global/streams/out | 0 .../unmanagedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 1 - .../_global/streams/export | 1 - .../exportedProducts/_global/streams/export | 1 - .../_global/streams/export | 1 - .../fullClasspath/_global/streams/export | 1 - .../_global/streams/export | 1 - .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/export | 1 - .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 1 - ...824e.cache => $87709882d327edfdfbe4.cache} | 0 ...1015.cache => $92eace74df3dd60b2407.cache} | 0 ...f011.cache => $b99baa0e80f987ddc888.cache} | 0 ...b092.cache => $bc99ac17cdce7fb9c74c.cache} | 0 .../scala-2.12/sbt-1.0/sync/copy-resource | 0 .../sbt-1.0/update/update_cache_2.12/inputs | 0 .../sbt-1.0/update/update_cache_2.12/output | 0 .../_global/_global/_global/streams/out | 0 .../_global/bloopInstall/_global/streams/out | 0 .../csrConfiguration/_global/streams/out | 0 .../_global/csrProject/_global/streams/out | 0 .../streams/update_cache_2.12/input_dsp | 0 .../streams/update_cache_2.12/output_dsp | 2 +- .../ivyConfiguration/_global/streams/out | 0 .../_global/ivySbt/_global/streams/out | 0 .../moduleSettings/_global/streams/out | 0 .../projectDescriptors/_global/streams/out | 0 .../_global/streams/out | 0 .../_global/update/_global/streams/out | 0 .../updateClassifiers/_global/streams/out | 3 - .../_global/streams/update_cache_2.12/inputs | 1 - .../_global/streams/update_cache_2.12/output | 1 - .../updateSbtClassifiers/_global/streams/out | 2 - .../_global/_global/compileOutputs/previous | 2 +- .../_global/discoveredMainClasses/data | 0 .../compile/bloopGenerate/_global/streams/out | 4 - .../bloopPostGenerate/_global/streams/out | 1 - .../compile/bspReporter/_global/streams/out | 0 .../compile/compile/_global/streams/out | 0 .../compileIncremental/_global/streams/export | 0 .../compileIncremental/_global/streams/out | 0 .../compile/copyResources/_global/streams/out | 0 .../_global/streams/export | 0 .../exportedProducts/_global/streams/export | 2 +- .../_global/streams/export | 0 .../compile/incOptions/_global/streams/out | 6 +- .../_global/streams/export | 0 .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 0 .../compile/scalacOptions/_global/streams/out | 0 .../unmanagedClasspath/_global/streams/export | 0 .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 0 .../it/bloopGenerate/_global/streams/out | 0 .../it/bloopPostGenerate/_global/streams/out | 0 .../_global/streams/export | 2 +- .../exportedProducts/_global/streams/export | 2 +- .../_global/streams/export | 0 .../fullClasspath/_global/streams/export | 2 +- .../_global/streams/export | 2 +- .../_global/streams/out | 0 .../managedClasspath/_global/streams/export | 0 .../unmanagedClasspath/_global/streams/export | 0 .../unmanagedClasspath/_global/streams/out | 0 .../unmanagedJars/_global/streams/export | 0 .../test/bloopGenerate/_global/streams/out | 0 .../bloopPostGenerate/_global/streams/out | 0 src/main/scala/common/Instructions.scala | 18 +- src/main/scala/micore/Core.scala | 18 +- src/main/scala/micore/Memory.scala | 2 +- src/main/scala/sicore/Core.scala | 28 +- src/main/scala/sicore/Memory.scala | 9 - target/scala-2.13/-name-_2.13-0.1.0.jar | Bin 92269 -> 113378 bytes target/scala-2.13/zinc/inc_compile_2.13.zip | Bin 21682 -> 21895 bytes .../_global/_global/compileOutputs/previous | 2 +- .../compileIncremental/_global/streams/out | 32 +- .../_global/streams/export | 2 +- .../exportedProducts/_global/streams/export | 2 +- .../compile/incOptions/_global/streams/out | 8 +- .../compile/packageBin/_global/streams/inputs | 2 +- .../compile/packageBin/_global/streams/out | 106 ++-- .../compile/packageBin/_global/streams/output | 2 +- .../_global/streams/export | 2 +- .../_global/streams/export | 2 +- .../_global/streams/export | 2 +- .../_global/streams/export | 2 +- .../TopOrigin.lo.fir | 487 +++++++++--------- .../TopOrigin.lo.fir | 314 ++++++----- 165 files changed, 645 insertions(+), 650 deletions(-) delete mode 100755 project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource delete mode 100755 project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs delete mode 100755 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_pc_plus4_T = pc_reg + 32'h4; - wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]}; - wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8; - wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0; - wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0; - wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]}; - wire _csignals_T_5 = _GEN_0 == 12'h20; - wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8; - wire _csignals_T_9 = _GEN_0 == 12'h22; - wire _csignals_T_11 = _GEN_0 == 12'h24; - wire _csignals_T_13 = _GEN_0 == 12'h25; - wire _csignals_T_15 = _GEN_0 == 12'h26; - wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC; - wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD; - wire _csignals_T_21 = _GEN_0 == 12'h2A; - wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4; - wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5; - wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]}; - wire _csignals_T_27 = _GEN_1 == 17'h0; - wire _csignals_T_29 = _GEN_1 == 17'h2; - wire _csignals_T_31 = _GEN_1 == 17'h3; - wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3; - wire _csignals_T_35 = _GEN == 10'h8; + wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]}; + wire jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8; + wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0; + wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0; + wire _csignals_T_1 = io_imem_inst[31:26] == 6'h23; + wire _csignals_T_3 = io_imem_inst[31:26] == 6'h2B; + wire _csignals_T_5 = _GEN == 12'h20; + wire _csignals_T_7 = io_imem_inst[31:26] == 6'h8; + wire _csignals_T_9 = _GEN == 12'h22; + wire _csignals_T_11 = _GEN == 12'h24; + wire _csignals_T_13 = _GEN == 12'h25; + wire _csignals_T_15 = _GEN == 12'h26; + wire _csignals_T_17 = io_imem_inst[31:26] == 6'hC; + wire _csignals_T_19 = io_imem_inst[31:26] == 6'hD; + wire _csignals_T_21 = _GEN == 12'h2A; + wire _csignals_T_23 = io_imem_inst[31:26] == 6'h4; + wire _csignals_T_25 = io_imem_inst[31:26] == 6'h5; + wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]}; + wire _csignals_T_27 = _GEN_0 == 17'h0; + wire _csignals_T_29 = _GEN_0 == 17'h2; + wire _csignals_T_31 = _GEN_0 == 17'h3; + wire _csignals_T_33 = io_imem_inst[31:26] == 6'h3; + wire _csignals_T_35 = _GEN == 12'h8; wire [4:0] csignals_0 = - _csignals_T_5 | _csignals_T_7 + _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 ? 5'h1 : _csignals_T_9 ? 5'h2 @@ -103,38 +104,56 @@ module Core( : _csignals_T_33 ? 5'h1 : _csignals_T_35 ? 5'hD : 5'h0; - wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31; - wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2; + wire _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31; + wire _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1; wire [1:0] csignals_1 = - _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33 + _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9 + | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 + | _GEN_2 | ~_csignals_T_33 ? 2'h1 : 2'h2; - wire [2:0] _csignals_T_85 = - _csignals_T_5 - ? 3'h1 - : _csignals_T_7 - ? 3'h2 - : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 - ? 3'h1 - : _csignals_T_17 | _csignals_T_19 - ? 3'h2 - : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35}; - wire _GEN_4 = _csignals_T_23 | _csignals_T_25; - wire _GEN_5 = + wire [2:0] csignals_2 = + _csignals_T_1 | _csignals_T_3 + ? 3'h2 + : _csignals_T_5 + ? 3'h1 + : _csignals_T_7 + ? 3'h2 + : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 + ? 3'h1 + : _csignals_T_17 | _csignals_T_19 + ? 3'h2 + : _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35}; + wire _GEN_3 = _csignals_T_23 | _csignals_T_25; + wire _GEN_4 = _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21; - wire [1:0] _csignals_T_136 = - _GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}}; + wire [1:0] csignals_4 = + _csignals_T_1 + ? 2'h1 + : _csignals_T_3 + ? 2'h0 + : _GEN_4 + ? 2'h1 + : _GEN_3 + ? 2'h0 + : {1'h0, + _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33}; + wire [2:0] csignals_5 = + _csignals_T_1 + ? 3'h2 + : _csignals_T_3 + ? 3'h0 + : _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0; wire _op1_data_T = csignals_1 == 2'h1; wire _op1_data_T_1 = csignals_1 == 2'h2; wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0; wire [31:0] op2_data = - _csignals_T_85 == 3'h1 + csignals_2 == 3'h1 ? rt_data - : _csignals_T_85 == 3'h2 + : csignals_2 == 3'h2 ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]} - : _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0; + : csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0; wire _alu_out_T = csignals_0 == 5'h1; wire [31:0] _alu_out_T_1 = op1_data + op2_data; wire _alu_out_T_3 = csignals_0 == 5'h2; @@ -148,13 +167,13 @@ module Core( wire _alu_out_T_12 = csignals_0 == 5'h6; wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0]; wire _alu_out_T_16 = csignals_0 == 5'h7; - wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]}; - wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6; + wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]}; + wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5; wire _alu_out_T_19 = csignals_0 == 5'h8; - wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6); + wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5); wire _alu_out_T_24 = csignals_0 == 5'h9; wire _alu_out_T_28 = csignals_0 == 5'hD; - wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)}; + wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)}; wire [31:0] alu_out = _alu_out_T ? _alu_out_T_1 @@ -173,24 +192,34 @@ module Core( : _alu_out_T_19 ? _alu_out_T_22 : _alu_out_T_24 - ? _GEN_7 + ? _GEN_6 : _alu_out_T_28 ? op1_data : 32'h0; wire _br_flg_T_3 = op1_data == op2_data; wire br_flg = csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3; wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg; wire [31:0] wb_data = - _csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out; + csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out; + wire [4:0] wb_addr = + csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0 + ? io_imem_inst[15:11] + : io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16]; `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset) begin $fwrite(32'h80000002, "---------------\n"); - $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst); + $fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst); + $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst); $fwrite(32'h80000002, "pc_next: 0x%x\n", br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T); + $fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0); $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]); + $fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]); $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]); + $fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data); + $fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4); $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data); + $fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data); $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data); $fwrite(32'h80000002, "---------------\n"); end @@ -219,7 +248,7 @@ module Core( else if (_alu_out_T_19) pc_reg <= _alu_out_T_22; else if (_alu_out_T_24) - pc_reg <= _GEN_7; + pc_reg <= _GEN_6; else if (_alu_out_T_28) begin if (_op1_data_T) pc_reg <= rs_data; @@ -233,24 +262,22 @@ module Core( pc_reg <= _pc_plus4_T; end // always @(posedge) regfile_32x32 regfile_ext ( - .R0_addr (io_imem_inst[20:16]), + .R0_addr (io_imem_inst[25:21]), .R0_en (1'h1), .R0_clk (clock), .R0_data (_regfile_ext_R0_data), - .R1_addr (io_imem_inst[25:21]), + .R1_addr (io_imem_inst[20:16]), .R1_en (1'h1), .R1_clk (clock), .R1_data (_regfile_ext_R1_data), - .W0_addr (io_imem_inst[15:11]), - .W0_en - (_GEN_5 | ~_GEN_4 - & (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)), + .W0_addr (wb_addr), + .W0_en (csignals_4 == 2'h1 & (|wb_addr)), .W0_clk (clock), .W0_data (wb_data) ); assign io_imem_addr = pc_reg; assign io_dmem_addr = alu_out; - assign io_dmem_wen = 1'h0; + assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3; assign io_dmem_wdata = rt_data; assign io_exit = io_imem_inst == 32'h114514; endmodule @@ -320,7 +347,7 @@ module mem_4096x8( end // always @(posedge) `ifdef ENABLE_INITIAL_MEM_ initial - $readmemh("src/hex/addi.hex", Memory); + $readmemh("src/hex/mem.hex", Memory); `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; diff --git a/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource b/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource deleted file mode 100755 index 9d348e7..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource +++ /dev/null @@ -1 +0,0 @@ -[[{},{}],{}] \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs deleted file mode 100755 index fd70f3c..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ --2109952146 \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output deleted file mode 100755 index 5cdd450..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/project/project/project/target/streams/_global/_global/_global/streams/out b/project/project/project/target/streams/_global/_global/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/csrConfiguration/_global/streams/out b/project/project/project/target/streams/_global/csrConfiguration/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/csrProject/_global/streams/out b/project/project/project/target/streams/_global/csrProject/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp deleted file mode 100755 index c09d4f8..0000000 --- a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp +++ /dev/null @@ -1 +0,0 @@ --2132504562 \ No newline at end of file diff --git a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp deleted file mode 100755 index 7a9f043..0000000 --- a/project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ /dev/null @@ -1 +0,0 @@ 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a/project/project/project/target/streams/_global/moduleSettings/_global/streams/out b/project/project/project/target/streams/_global/moduleSettings/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/projectDescriptors/_global/streams/out b/project/project/project/target/streams/_global/projectDescriptors/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/update/_global/streams/out b/project/project/project/target/streams/_global/update/_global/streams/out deleted file mode 100755 index 982166c..0000000 --- a/project/project/project/target/streams/_global/update/_global/streams/out +++ /dev/null @@ -1,3 +0,0 @@ -[debug] not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")... -[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build") diff --git a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous deleted file mode 100755 index d3be71e..0000000 --- a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data deleted file mode 100755 index 0637a08..0000000 --- a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data +++ /dev/null @@ -1 +0,0 @@ -[] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/project/target/streams/compile/bspReporter/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compile/_global/streams/out b/project/project/project/target/streams/compile/compile/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/project/target/streams/compile/compileIncremental/_global/streams/export deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out deleted file mode 100755 index 9cca155..0000000 --- a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out +++ /dev/null @@ -1,6 +0,0 @@ -[debug] [zinc] IncrementalCompile ----------- -[debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries -[debug] current source = Set() -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/project/target/streams/compile/copyResources/_global/streams/out deleted file mode 100755 index f25042f..0000000 --- a/project/project/project/target/streams/compile/copyResources/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Copy resource mappings:  -[debug]   diff --git a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/project/target/streams/compile/incOptions/_global/streams/out deleted file mode 100755 index 7231079..0000000 --- a/project/project/project/target/streams/compile/incOptions/_global/streams/out +++ /dev/null @@ -1,5 +0,0 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] About to delete class files: -[debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/project/target/streams/compile/scalacOptions/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export deleted file mode 100755 index 3f98510..0000000 --- a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index bbd3b52..0000000 --- a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export deleted file mode 100755 index 3f98510..0000000 --- a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export deleted file mode 100755 index bbd3b52..0000000 --- a/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/project/project/target/streams/_global/_global/_global/streams/out b/project/project/target/streams/_global/_global/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/csrConfiguration/_global/streams/out b/project/project/target/streams/_global/csrConfiguration/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/csrProject/_global/streams/out b/project/project/target/streams/_global/csrProject/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp deleted file mode 100755 index c09d4f8..0000000 --- a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp +++ /dev/null @@ -1 +0,0 @@ --2132504562 \ No newline at end of file diff --git a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp deleted file mode 100755 index 7a9f043..0000000 --- a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ /dev/null @@ -1 +0,0 @@ -{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) 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a/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/update/_global/streams/out b/project/project/target/streams/_global/update/_global/streams/out deleted file mode 100755 index 587fe53..0000000 --- a/project/project/target/streams/_global/update/_global/streams/out +++ /dev/null @@ -1,3 +0,0 @@ -[debug] not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")... -[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build") diff --git a/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/target/streams/compile/_global/_global/compileOutputs/previous deleted file mode 100755 index 29633ad..0000000 --- a/project/project/target/streams/compile/_global/_global/compileOutputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data deleted file mode 100755 index 0637a08..0000000 --- a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data +++ /dev/null @@ -1 +0,0 @@ -[] \ No newline at end of file diff --git a/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/target/streams/compile/bspReporter/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compile/_global/streams/out b/project/project/target/streams/compile/compile/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/target/streams/compile/compileIncremental/_global/streams/export deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/target/streams/compile/compileIncremental/_global/streams/out deleted file mode 100755 index 9cca155..0000000 --- a/project/project/target/streams/compile/compileIncremental/_global/streams/out +++ /dev/null @@ -1,6 +0,0 @@ -[debug] [zinc] IncrementalCompile ----------- -[debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries -[debug] current source = Set() -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/target/streams/compile/copyResources/_global/streams/out deleted file mode 100755 index f25042f..0000000 --- a/project/project/target/streams/compile/copyResources/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Copy resource mappings:  -[debug]   diff --git a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/target/streams/compile/exportedProducts/_global/streams/export deleted file mode 100755 index 454272b..0000000 --- a/project/project/target/streams/compile/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/target/streams/compile/incOptions/_global/streams/out deleted file mode 100755 index 66abc73..0000000 --- a/project/project/target/streams/compile/incOptions/_global/streams/out +++ /dev/null @@ -1,5 +0,0 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] About to delete class files: -[debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/target/streams/compile/managedClasspath/_global/streams/export deleted file mode 100755 index b1694c2..0000000 --- a/project/project/target/streams/compile/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/target/streams/compile/scalacOptions/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/target/streams/compile/unmanagedJars/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export deleted file mode 100755 index 4c93399..0000000 --- a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/target/streams/runtime/exportedProducts/_global/streams/export deleted file mode 100755 index 454272b..0000000 --- a/project/project/target/streams/runtime/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index bbd3b52..0000000 --- a/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/target/streams/runtime/fullClasspath/_global/streams/export deleted file mode 100755 index 4c93399..0000000 --- a/project/project/target/streams/runtime/fullClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 454272b..0000000 --- a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/project/target/streams/runtime/managedClasspath/_global/streams/export deleted file mode 100755 index bbd3b52..0000000 --- a/project/project/target/streams/runtime/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/project/project/target/streams/runtime/unmanagedClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/project/target/streams/runtime/unmanagedJars/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/runtime/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/target/config-classes/$948efd6ee3ba8f09824e.cache b/project/target/config-classes/$87709882d327edfdfbe4.cache old mode 100755 new mode 100644 similarity index 100% rename from project/target/config-classes/$948efd6ee3ba8f09824e.cache rename to project/target/config-classes/$87709882d327edfdfbe4.cache diff --git a/project/target/config-classes/$2b8c65d0a3a3f42e1015.cache b/project/target/config-classes/$92eace74df3dd60b2407.cache old mode 100755 new mode 100644 similarity index 100% rename from project/target/config-classes/$2b8c65d0a3a3f42e1015.cache rename to project/target/config-classes/$92eace74df3dd60b2407.cache diff --git a/project/target/config-classes/$add241eb0c1a6339f011.cache b/project/target/config-classes/$b99baa0e80f987ddc888.cache old mode 100755 new mode 100644 similarity index 100% rename from project/target/config-classes/$add241eb0c1a6339f011.cache rename to project/target/config-classes/$b99baa0e80f987ddc888.cache diff --git a/project/target/config-classes/$eac2b8278586e49cb092.cache b/project/target/config-classes/$bc99ac17cdce7fb9c74c.cache old mode 100755 new mode 100644 similarity index 100% rename from project/target/config-classes/$eac2b8278586e49cb092.cache rename to project/target/config-classes/$bc99ac17cdce7fb9c74c.cache diff --git a/project/target/scala-2.12/sbt-1.0/sync/copy-resource b/project/target/scala-2.12/sbt-1.0/sync/copy-resource old mode 100755 new mode 100644 diff --git a/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs old mode 100755 new mode 100644 diff --git a/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/_global/_global/streams/out b/project/target/streams/_global/_global/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/_global/bloopInstall/_global/streams/out b/project/target/streams/_global/_global/bloopInstall/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/target/streams/_global/csrConfiguration/_global/streams/out b/project/target/streams/_global/csrConfiguration/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/csrProject/_global/streams/out b/project/target/streams/_global/csrProject/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp old mode 100755 new mode 100644 index 00763b6..93fa874 --- a/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ b/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp @@ -1 +1 @@ -{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} \ No newline at end of file +{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}} \ No newline at end of file diff --git a/project/target/streams/_global/ivyConfiguration/_global/streams/out b/project/target/streams/_global/ivyConfiguration/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/ivySbt/_global/streams/out b/project/target/streams/_global/ivySbt/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/moduleSettings/_global/streams/out b/project/target/streams/_global/moduleSettings/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/projectDescriptors/_global/streams/out b/project/target/streams/_global/projectDescriptors/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/update/_global/streams/out b/project/target/streams/_global/update/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/_global/updateClassifiers/_global/streams/out b/project/target/streams/_global/updateClassifiers/_global/streams/out deleted file mode 100755 index 6e08f01..0000000 --- a/project/target/streams/_global/updateClassifiers/_global/streams/out +++ /dev/null @@ -1,3 +0,0 @@ -[debug] not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/"), "micore-build")... -[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/"), "micore-build") diff --git a/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs b/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs deleted file mode 100755 index 0120f9f..0000000 --- a/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ -606022120 \ No newline at end of file diff --git a/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output b/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output deleted file mode 100755 index a2b073f..0000000 --- a/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/project/target/streams/_global/updateSbtClassifiers/_global/streams/out b/project/target/streams/_global/updateSbtClassifiers/_global/streams/out deleted file mode 100755 index d06cba1..0000000 --- a/project/target/streams/_global/updateSbtClassifiers/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Other repositories: -[debug] Default repositories: diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous old mode 100755 new mode 100644 index 3f53060..3cd4ba7 --- a/project/target/streams/compile/_global/_global/compileOutputs/previous +++ b/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/target/streams/compile/_global/_global/discoveredMainClasses/data old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/bloopGenerate/_global/streams/out b/project/target/streams/compile/bloopGenerate/_global/streams/out deleted file mode 100755 index 0816633..0000000 --- a/project/target/streams/compile/bloopGenerate/_global/streams/out +++ /dev/null @@ -1,4 +0,0 @@ -[debug] [micore-build] Classpath dependencies List() -[debug] [micore-build] Dependencies from configurations List() -[debug] Bloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json' -[success] Generated .bloop/micore-build.json diff --git a/project/target/streams/compile/bloopPostGenerate/_global/streams/out b/project/target/streams/compile/bloopPostGenerate/_global/streams/out deleted file mode 100755 index 33f2857..0000000 --- a/project/target/streams/compile/bloopPostGenerate/_global/streams/out +++ /dev/null @@ -1 +0,0 @@ -[debug] Running postGenerate for micore-build diff --git a/project/target/streams/compile/bspReporter/_global/streams/out b/project/target/streams/compile/bspReporter/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/compile/_global/streams/out b/project/target/streams/compile/compile/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/compileIncremental/_global/streams/export b/project/target/streams/compile/compileIncremental/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export old mode 100755 new mode 100644 index 4006493..faf6770 --- a/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out old mode 100755 new mode 100644 index 44649e0..96aaeb5 --- a/project/target/streams/compile/incOptions/_global/streams/out +++ b/project/target/streams/compile/incOptions/_global/streams/out @@ -1,5 +1,5 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] About to delete class files: [debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/target/streams/compile/internalDependencyClasspath/_global/streams/out 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a/project/target/streams/it/bloopGenerate/_global/streams/out b/project/target/streams/it/bloopGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/target/streams/it/bloopPostGenerate/_global/streams/out b/project/target/streams/it/bloopPostGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export old mode 100755 new mode 100644 index f810de7..69ab39c --- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export old mode 100755 new mode 100644 index 4006493..faf6770 --- a/project/target/streams/runtime/exportedProducts/_global/streams/export +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export old mode 100755 new mode 100644 index f810de7..69ab39c --- a/project/target/streams/runtime/fullClasspath/_global/streams/export +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export old mode 100755 new mode 100644 index 4006493..faf6770 --- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/project/target/streams/runtime/unmanagedClasspath/_global/streams/out old mode 100755 new mode 100644 diff --git a/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/target/streams/runtime/unmanagedJars/_global/streams/export old mode 100755 new mode 100644 diff --git a/project/target/streams/test/bloopGenerate/_global/streams/out b/project/target/streams/test/bloopGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/target/streams/test/bloopPostGenerate/_global/streams/out b/project/target/streams/test/bloopPostGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/src/main/scala/common/Instructions.scala b/src/main/scala/common/Instructions.scala index 8bd1912..7d5f10f 100755 --- a/src/main/scala/common/Instructions.scala +++ b/src/main/scala/common/Instructions.scala @@ -5,13 +5,13 @@ import chisel3.util._ object Instructions { // * 加载 / 存储 - val LW = BitPat("b100011????????????????????????????") // lw rt, offset(rs) - val SW = BitPat("b101011????????????????????????????") // sw rt, offset(rs) + val LW = BitPat("b100011??????????????????????????") // lw rt, offset(rs) + val SW = BitPat("b101011??????????????????????????") // sw rt, offset(rs) // * 算术运算 val ADD = BitPat("b000000????????????????????100000") // add rd, rs, rt val ADDI = BitPat( - "b001000????????????????????????????" + "b001000??????????????????????????" ) // addi rt, rs, immediate val SUB = BitPat("b000000????????????????????100010") // sub rd, rs, rt @@ -20,18 +20,18 @@ object Instructions { val OR = BitPat("b000000????????????????????100101") // or rd, rs, rt val XOR = BitPat("b000000????????????????????100110") // xor rd, rs, rt val ANDI = BitPat( - "b001100????????????????????????????" + "b001100??????????????????????????" ) // andi rt, rs, immediate val ORI = BitPat( - "b001101????????????????????????????" + "b001101??????????????????????????" ) // ori rt, rs, immediate // * 比较 val SLT = BitPat("b000000????????????????????101010") // slt rd, rs, rt // * 条件分支 - val BEQ = BitPat("b000100????????????????????????????") // beq rs, rt, offset - val BNE = BitPat("b000101????????????????????????????") // bne rs, rt, offset + val BEQ = BitPat("b000100??????????????????????????") // beq rs, rt, offset + val BNE = BitPat("b000101??????????????????????????") // bne rs, rt, offset // * 移位 val SLL = BitPat("b00000000000???????????????000000") // sll rd, rt, shamt @@ -39,8 +39,8 @@ object Instructions { val SRA = BitPat("b00000000000???????????????000011") // sra rd, rt, shamt // * 跳转 - val JR = BitPat("b000000??????????????????????001000") // jr rs - val JAL = BitPat("b000011????????????????????????????") // jal target + val JR = BitPat("b000000????????????????????001000") // jr rs + val JAL = BitPat("b000011??????????????????????????") // jal target // * NOP val NOP = BitPat("b00100000000000000000000000000000") // nop (addi $0, $0, 0) diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala index 2bf205e..3b138d1 100755 --- a/src/main/scala/micore/Core.scala +++ b/src/main/scala/micore/Core.scala @@ -97,7 +97,17 @@ class Core extends Module { val id_rs1_addr = id_inst(25, 21) val id_rs2_addr = id_inst(20, 16) - val id_wb_addr = id_inst(15, 11) + // val id_wb_addr = id_inst(15, 11) + val id_wb_addr = MuxCase( + id_inst(20, 16), // 默认是 rt_addr + Seq( + (id_inst(31, 26) === "b000000".U) -> id_inst( + 15, + 11 + ), // R型指令，目标寄存器是 rd_addr + (id_inst === JAL) -> 31.U // JAL指令，目标寄存器是 $ra (寄存器31) + ) + ) val mem_wb_data = Wire(UInt(WORD_LEN.W)) val id_rs1_data = MuxCase( @@ -156,7 +166,6 @@ class Core extends Module { JR -> List(ALU_X, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X), JAL -> List(ALU_X, OP1_PC, OP2_X, MEN_X, REN_X, WB_X), NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X) - // LUI -> List(ALU_X, OP1_X, OP2_IMU, MEN_X, REN_X, WB_ALU), ) ) @@ -262,7 +271,10 @@ class Core extends Module { wb_reg_wb_addr := mem_reg_wb_addr // ********* Write Back (WB) Stage ********* - when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } + // when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } + when(wb_reg_rf_wen === REN_S && wb_reg_wb_addr =/= 0.U) { + regfile(wb_reg_wb_addr) := wb_reg_wb_data + } // ********* Debugging ********* io.exit := (id_reg_inst === UNIMP) diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala index 9eb8386..40d003d 100755 --- a/src/main/scala/micore/Memory.scala +++ b/src/main/scala/micore/Memory.scala @@ -31,7 +31,7 @@ class Memory extends Module { val mem = Mem(4096, UInt(8.W)) // 加载存储器的初始值。 - loadMemoryFromFileInline(mem, "src/hex/addi.hex") + loadMemoryFromFileInline(mem, "src/hex/mem.hex") // 连接四个地址存储的八位数据形成一个32位的指令。 io.imem.inst := Cat( diff --git a/src/main/scala/sicore/Core.scala b/src/main/scala/sicore/Core.scala index d49de9e..d1450b8 100755 --- a/src/main/scala/sicore/Core.scala +++ b/src/main/scala/sicore/Core.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ import common.Consts._ import common.Instructions._ +import os.list class Core extends Module { val io = IO(new Bundle { @@ -12,7 +13,6 @@ class Core extends Module { val exit = Output(Bool()) }) - // 寄存器文件 val regfile = Mem(32, UInt(WORD_LEN.W)) // ********* Instruction Fetch (IF) Stage ********* @@ -66,7 +66,7 @@ class Core extends Module { SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU), JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), - JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) // 添加JR指令 + JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X) ) ) @@ -103,7 +103,7 @@ class Core extends Module { (exe_fun === ALU_SRL) -> (op1_data >> op2_data(4, 0)).asUInt, (exe_fun === ALU_SRA) -> (op1_data.asSInt >> op2_data(4, 0)).asUInt, (exe_fun === ALU_SLT) -> (op1_data.asSInt < op2_data.asSInt).asUInt, - (exe_fun === ALU_COPY1) -> op1_data // 添加JR指令的处理 + (exe_fun === ALU_COPY1) -> op1_data ) ) @@ -132,20 +132,34 @@ class Core extends Module { ) ) - // 写回寄存器文件 - when(rf_wen === REN_S && rd_addr =/= 0.U) { - regfile(rd_addr) := wb_data + val wb_addr = MuxCase( + rt_addr, + Seq( + (wb_sel === WB_ALU && inst(31, 26) === "b000000".U) -> rd_addr, // R型指令 + (inst === JAL) -> 31.U + ) + ) + + when(rf_wen === REN_S && wb_addr =/= 0.U) { + regfile(wb_addr) := wb_data } io.exit := (inst === UNIMP) // ********* Debugging ********* printf(p"---------------\n") - printf(p"io.pc: 0x${Hexadecimal(pc_reg)}\ninst: 0x${Hexadecimal(inst)} \n") + printf(p"io.imem.inst: 0x${Hexadecimal(io.imem.inst)}\n") + printf(p"io.pc: 0x${Hexadecimal(pc_reg)}\ninst: 0x${Binary(inst)} \n") printf(p"pc_next: 0x${Hexadecimal(pc_next)}\n") + printf(p"exe_fun: 0x${Hexadecimal(exe_fun)}\n") printf(p"rs_addr: 0x${Hexadecimal(rs_addr)}\n") + printf(p"rt_addr: 0x${Hexadecimal(rt_addr)}\n") printf(p"rd_addr: 0x${Hexadecimal(rd_addr)}\n") + printf(p"reg: 0x${Hexadecimal(regfile(rt_addr))}\n") + printf(p"rf_wen: 0x${Hexadecimal(rf_wen)}\n") + // printf(p"imm_i: 0x${Hexadecimal(imm_i)}\n") printf(p"rs_data: 0x${Hexadecimal(rs_data)}\n") + printf(p"rt_data: 0x${Hexadecimal(rt_data)}\n") printf(p"wb_data: 0x${Hexadecimal(wb_data)}\n") printf(p"---------------\n") } diff --git a/src/main/scala/sicore/Memory.scala b/src/main/scala/sicore/Memory.scala index 97d4bca..4983e71 100755 --- a/src/main/scala/sicore/Memory.scala +++ b/src/main/scala/sicore/Memory.scala @@ -5,15 +5,11 @@ import chisel3.util._ import common.Consts._ import chisel3.util.experimental.loadMemoryFromFileInline -/** 表示一个指令内存端口接口的类 - */ class ImemPortIo extends Bundle { val addr = Input(UInt(WORD_LEN.W)) val inst = Output(UInt(WORD_LEN.W)) } -/** 表示一个数据内存端口接口的类 - */ class DmemPortIo extends Bundle { val addr = Input(UInt(WORD_LEN.W)) val rdata = Output(UInt(WORD_LEN.W)) @@ -27,13 +23,10 @@ class Memory extends Module { val dmem = new DmemPortIo() }) - // 生成八位宽x4096(4KB)寄存器的存储器。 val mem = Mem(4096, UInt(8.W)) - // 加载存储器的初始值。 loadMemoryFromFileInline(mem, "src/hex/mem.hex") - // 连接四个地址存储的八位数据形成一个32位的指令。 io.imem.inst := Cat( mem(io.imem.addr + 3.U(WORD_LEN.W)), mem(io.imem.addr + 2.U(WORD_LEN.W)), @@ -41,7 +34,6 @@ class Memory extends Module { mem(io.imem.addr) ) - // 连接四个地址存储的八位数据形成一个32位的数据。 io.dmem.rdata := Cat( mem(io.dmem.addr + 3.U(WORD_LEN.W)), mem(io.dmem.addr + 2.U(WORD_LEN.W)), @@ -49,7 +41,6 @@ class Memory extends Module { mem(io.dmem.addr) ) - // 写数据到存储器。 when(io.dmem.wen) { mem(io.dmem.addr) := io.dmem.wdata(7, 0) mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8) diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar 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zI8e3jur8$2)IomEI+y0LJNi!4F@IuXC9r*j%@FcxT8|0Usb8AvL!}wj9Hx+$Z+dx< z0Yk_uBq?cmlP9S$jddQ zq+4BHj}Y?O&2YFtzW=-CpsS#2g2y0g78J!CA}T{Mujn)Xbc9vJm{)(NuRFqDO3 initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/sicore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/micore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set()) [debug]  [debug] Initial source changes: [debug]  removed: Set() [debug]  added: Set() -[debug]  modified: Set(${BASE}/src/main/scala/sicore/Core.scala) +[debug]  modified: Set(${BASE}/src/main/scala/micore/Core.scala) [debug] Invalidated products: Set() [debug] External API changes: API Changes: Set() [debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(sicore.Core) +[debug] Initial directly invalidated classes: Set(micore.Core) [debug] Sources indirectly invalidated by: [debug]  product: Set() [debug]  binary dep: Set() [debug]  external source: Set() -[debug] All initially invalidated classes: Set(sicore.Core) -[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/sicore/Core.scala) -[debug] Initial set of included nodes: sicore.Core +[debug] All initially invalidated classes: Set(micore.Core) +[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/micore/Core.scala) +[debug] Initial set of included nodes: micore.Core [debug] compilation cycle 1 -[info] compiling 1 Scala source to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ... +[info] compiling 1 Scala source to /home/gh0s7/project/ddca/micore/target/scala-2.13/classes ... [debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar. -[debug] [zinc] Running cached compiler 486ef6c9 for Scala compiler version 2.13.12 +[debug] [zinc] Running cached compiler 26d066fe for Scala compiler version 2.13.12 [debug] [zinc] The Scala compiler is invoked with: [debug]  -language:reflectiveCalls [debug]  -deprecation @@ -33,22 +33,12 @@ [debug]  -bootclasspath [debug]  /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar [debug]  -classpath -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar -[debug] Invalidating (transitively) by inheritance from sicore.Core... -[debug] Initial set of included nodes: sicore.Core -[debug] Invalidated by transitive inheritance dependency: Set(sicore.Core) -[debug] None of the modified names appears in source file of sicore.TopOrigin. This dependency is not being considered for invalidation. -[debug] Change NamesChange(sicore.Core,ModifiedNames(changes = UsedName(rs_addr,[Default]), UsedName(imm_j,[Default]), UsedName(alu_result,[Default]), UsedName(opcode,[Default]), UsedName(rd,[Default]), UsedName(address,[Default]), UsedName(rt,[Default]), UsedName(imm,[Default]), UsedName(rf_wen,[Default]), UsedName(op1_sel,[Default]), UsedName(shamt,[Default]), UsedName(mem_wen,[Default]), UsedName(rs,[Default]), UsedName(csignals,[Default]), UsedName(pc_next,[Default]), UsedName(is_jump,[Default]), UsedName(br_target,[Default]), UsedName(imm_sext,[Default]), UsedName(rd_addr,[Default]), UsedName(alu_out,[Default]), UsedName(exe_fun,[Default]), UsedName(br_flg,[Default]), UsedName(pc_inc,[Default]), UsedName(is_branch,[Default]), UsedName(rt_addr,[Default]), UsedName(alu_op2,[Default]), UsedName(jmp_flg,[Default]), UsedName(funct,[Default]), UsedName(branch_target,[Default]), UsedName(imm_i,[Default]), UsedName(op2_data,[Default]), UsedName(pc_plus4,[Default]), UsedName(wb_sel,[Default]), UsedName(op1_data,[Default]), UsedName(wb_data,[Default]), UsedName(alu_op1,[Default]), UsedName(op2_sel,[Default]), UsedName(jump_target,[Default]), UsedName(imm_i_sext,[Default]))) invalidates 1 classes due to The sicore.Core has the following regular definitions changed: -[debug]  UsedName(rs_addr,[Default]), UsedName(imm_j,[Default]), UsedName(alu_result,[Default]), UsedName(opcode,[Default]), UsedName(rd,[Default]), UsedName(address,[Default]), UsedName(rt,[Default]), UsedName(imm,[Default]), UsedName(rf_wen,[Default]), UsedName(op1_sel,[Default]), UsedName(shamt,[Default]), UsedName(mem_wen,[Default]), UsedName(rs,[Default]), UsedName(csignals,[Default]), UsedName(pc_next,[Default]), UsedName(is_jump,[Default]), UsedName(br_target,[Default]), UsedName(imm_sext,[Default]), UsedName(rd_addr,[Default]), UsedName(alu_out,[Default]), UsedName(exe_fun,[Default]), UsedName(br_flg,[Default]), UsedName(pc_inc,[Default]), UsedName(is_branch,[Default]), UsedName(rt_addr,[Default]), UsedName(alu_op2,[Default]), UsedName(jmp_flg,[Default]), UsedName(funct,[Default]), UsedName(branch_target,[Default]), UsedName(imm_i,[Default]), UsedName(op2_data,[Default]), UsedName(pc_plus4,[Default]), UsedName(wb_sel,[Default]), UsedName(op1_data,[Default]), UsedName(wb_data,[Default]), UsedName(alu_op1,[Default]), UsedName(op2_sel,[Default]), UsedName(jump_target,[Default]), UsedName(imm_i_sext,[Default]). -[debug]  > by transitive inheritance: Set(sicore.Core) -[debug]  >  -[debug]  >  -[debug]   +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar [debug] New invalidations: [debug] Initial set of included nodes:  [debug] Previously invalidated, but (transitively) depend on new invalidations: [debug] Final step, transitive dependencies: [debug]  Set() [debug] No classes were invalidated. -[debug] Scala compilation took 2.296694362 s +[debug] Scala compilation took 3.12228093 s [debug] done compiling diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/compile/exportedProductJars/_global/streams/export +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export index 21cdc14..3c15dcc 100755 --- a/target/streams/compile/exportedProducts/_global/streams/export +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes +/home/gh0s7/project/ddca/micore/target/scala-2.13/classes diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out index dae7507..feff054 100755 --- a/target/streams/compile/incOptions/_global/streams/out +++ b/target/streams/compile/incOptions/_global/streams/out @@ -1,11 +1,11 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak [debug] About to delete class files: -[debug]  Core.class [debug]  Core$$anon$1.class +[debug]  Core.class [debug] We backup class files: -[debug]  Core.class [debug]  Core$$anon$1.class +[debug]  Core.class [debug] Registering generated classes: [debug]  Core$$anon$1.class [debug]  Core.class -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak +[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs index 35c218e..f25655c 100755 --- a/target/streams/compile/packageBin/_global/streams/inputs +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ -175918183 \ No newline at end of file +160837087 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out index 873cb34..e08e3d0 100755 --- a/target/streams/compile/packageBin/_global/streams/out +++ b/target/streams/compile/packageBin/_global/streams/out @@ -1,57 +1,73 @@ -[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... +[debug] Packaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... [debug] Input file mappings: +[debug]  gcd +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd +[debug]  gcd/GcdInputBundle.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class +[debug]  gcd/GcdOutputBundle.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class +[debug]  gcd/DecoupledGcd.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class +[debug]  gcd/GCD.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class +[debug]  gcd/GCD$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class +[debug]  gcd/GCD$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class +[debug]  gcd/GCD$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class [debug]  common -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common [debug]  common/Consts$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class [debug]  common/Consts.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class [debug]  common/Instructions$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class [debug]  common/Instructions.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class [debug]  micore -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore -[debug]  micore/Core$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore [debug]  micore/Core.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class -[debug]  micore/DmemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class -[debug]  micore/ImemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class -[debug]  micore/Memory$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class -[debug]  micore/Memory.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class -[debug]  micore/TopOrigin$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class -[debug]  micore/TopOrigin$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class -[debug]  micore/TopOrigin$delayedInit$body.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class +[debug]  micore/Core$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class [debug]  micore/TopOrigin.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class +[debug]  micore/TopOrigin$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class +[debug]  micore/TopOrigin$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class +[debug]  micore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class +[debug]  micore/ImemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class +[debug]  micore/DmemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class +[debug]  micore/Memory.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class +[debug]  micore/Memory$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class [debug]  sicore -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore -[debug]  sicore/Core$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class -[debug]  sicore/Core.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Core.class -[debug]  sicore/DmemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/DmemPortIo.class -[debug]  sicore/ImemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/ImemPortIo.class -[debug]  sicore/Memory$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class -[debug]  sicore/Memory.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/Memory.class -[debug]  sicore/TopOrigin$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class -[debug]  sicore/TopOrigin$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$.class -[debug]  sicore/TopOrigin$delayedInit$body.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore [debug]  sicore/TopOrigin.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/sicore/TopOrigin.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin.class +[debug]  sicore/TopOrigin$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$.class +[debug]  sicore/TopOrigin$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$$anon$1.class +[debug]  sicore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/TopOrigin$delayedInit$body.class +[debug]  sicore/Core.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core.class +[debug]  sicore/Core$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Core$$anon$1.class +[debug]  sicore/ImemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/ImemPortIo.class +[debug]  sicore/DmemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/DmemPortIo.class +[debug]  sicore/Memory.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory.class +[debug]  sicore/Memory$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/sicore/Memory$$anon$1.class [debug] Done packaging. diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output index ccc866e..4e9041f 100755 --- a/target/streams/compile/packageBin/_global/streams/output +++ b/target/streams/compile/packageBin/_global/streams/output @@ -1 +1 @@ --1359482768 \ No newline at end of file +1488086236 \ No newline at end of file diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export index 112ae53..ddc45ce 100755 --- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/re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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/runtime/exportedProductJars/_global/streams/export +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export index 112ae53..ddc45ce 100755 --- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir index caeb25a..b40fce7 100755 --- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -50,83 +50,79 @@ circuit TopOrigin : reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 34:35] reg exe_reg_imm_u_shifted : UInt<32>, clock with : reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 35:38] - reg exe_reg_imm_z_uext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:35] reg mem_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 39:27] + reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 38:27] reg mem_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 40:32] + reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 39:32] reg mem_reg_op1_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 41:33] + reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 40:33] reg mem_reg_rs2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 42:33] + reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 41:33] reg mem_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 43:32] + reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 42:32] reg mem_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 44:31] + reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 43:31] reg mem_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 45:31] - reg mem_reg_imm_z_uext : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 46:35] + reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 44:31] reg mem_reg_alu_out : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 47:32] + reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 45:32] reg wb_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 50:31] + reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 48:31] reg wb_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 51:30] + reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 49:30] reg wb_reg_wb_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 52:31] + reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 50:31] reg if_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 55:26] - node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 65:31] - node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 65:31] - node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] - node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 87:34] - node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50] - node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] - node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77] - node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59] - node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21] - node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 88:34] - node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:50] - node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32] - node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:77] - node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:59] - node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36] - node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 59:23 95:13] + reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 53:26] + node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 63:31] + node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 63:31] + node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 90:21] + node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 85:34] + node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 90:50] + node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 90:32] + node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 90:77] + node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 90:59] + node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] + node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 86:34] + node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50] + node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] + node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77] + node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59] + node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 93:36] + node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 57:23 93:13] node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 239:34] - node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 239:15 62:25] - node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 204:24] - node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 204:58] - node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 204:58] - node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 205:24] - node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 205:58] - node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 205:58] - node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 206:24] - node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:58] - node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 207:24] - node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 207:57] - node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 208:24] - node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:58] - node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 209:24] - node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 209:77] - node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 209:58] - node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 212:9] - node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 213:24] - node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 213:77] - node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 213:58] - node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 217:24] - node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 217:58] - node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 217:84] - node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 217:65] - node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 220:10] - node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 221:24] - node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 221:58] - node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 221:84] - node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 221:65] - node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 222:24] - node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 222:59] + node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 243:34] + node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 243:15 60:25] + node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 211:24] + node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 211:58] + node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 211:58] + node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 212:24] + node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 212:58] + node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 212:58] + node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 213:24] + node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 213:58] + node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 214:24] + node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 214:57] + node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 215:24] + node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 215:58] + node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 216:24] + node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 216:77] + node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 216:58] + node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 219:9] + node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 220:24] + node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 220:77] + node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 220:58] + node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 224:24] + node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 224:58] + node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 224:84] + node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 224:65] + node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 227:10] + node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 228:24] + node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 228:58] + node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 228:84] + node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 228:65] + node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 229:24] + node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 229:59] node _exe_alu_out_T_30 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_31 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_32 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_31) @[src/main/scala/chisel3/util/Mux.scala 126:16] @@ -137,83 +133,90 @@ circuit TopOrigin : node _exe_alu_out_T_37 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_38 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_alu_out_T_39 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 201:15 63:25] + node exe_alu_out = _exe_alu_out_T_39 @[src/main/scala/micore/Core.scala 208:15 61:25] node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 232:24] - node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 232:57] - node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 233:24] - node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 233:58] - node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 233:39] + node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 236:24] + node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 236:57] + node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 237:24] + node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 237:58] + node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 237:39] node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 229:14 60:24] - node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 237:31] - node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 237:31] - node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 237:17 61:27] + node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 233:14 58:24] + node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 241:31] + node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 241:31] + node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 241:17 59:27] node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 77:19] - node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 81:19] + node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 75:19] + node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 79:19] node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h20000000"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21] - node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36] - node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8] - node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 100:28] - node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 101:28] - node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 102:27] - node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 108:20] - node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 109:21] - node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 109:61] - node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 109:42] - node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:21] - node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:59] - node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 110:41] + node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 96:21] + node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 96:36] + node id_inst = mux(_id_inst_T_1, UInt<32>("h20000000"), id_reg_inst) @[src/main/scala/micore/Core.scala 96:8] + node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 98:28] + node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 99:28] + node _id_wb_addr_T = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 102:12] + node _id_wb_addr_T_1 = bits(id_inst, 31, 26) @[src/main/scala/micore/Core.scala 104:15] + node _id_wb_addr_T_2 = eq(_id_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 104:24] + node _id_wb_addr_T_3 = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 104:51] + node _id_wb_addr_T_4 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/micore/Core.scala 108:16] + node _id_wb_addr_T_5 = eq(UInt<28>("hc000000"), _id_wb_addr_T_4) @[src/main/scala/micore/Core.scala 108:16] + node _id_wb_addr_T_6 = mux(_id_wb_addr_T_5, UInt<5>("h1f"), _id_wb_addr_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_wb_addr = mux(_id_wb_addr_T_2, _id_wb_addr_T_3, _id_wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20] + node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21] + node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61] + node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 117:42] + node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] + node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59] + node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 118:41] node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 260:23] - node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 261:23] - node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 261:49] - node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 261:49] + node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 263:23] + node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 264:23] + node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 264:49] + node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 264:49] node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 104:25 257:15] + node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 112:25 260:15] node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_wb_data, _id_rs1_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20] - node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21] - node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61] - node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:42] - node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] - node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59] - node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 118:41] + node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 124:20] + node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 125:21] + node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 125:61] + node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 125:42] + node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 126:21] + node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 126:59] + node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 126:41] node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_wb_data, _id_rs2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 122:25] - node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 123:44] - node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 123:31] - node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 123:26] - node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 125:12] - node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 124:21] - node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 128:44] - node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 128:31] - node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 128:26] - node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 130:12] - node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 129:21] - node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 133:43] - node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 133:31] - node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 133:26] - node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 134:25] - node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 135:44] - node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 135:29] - node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 136:29] - node _csignals_T = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 130:25] + node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 131:44] + node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 131:31] + node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 131:26] + node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 133:12] + node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 132:21] + node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 136:44] + node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 136:31] + node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 136:26] + node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 138:12] + node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 137:21] + node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 141:43] + node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 141:31] + node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 141:26] + node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 142:25] + node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 143:44] + node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 143:29] + node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 144:29] + node _csignals_T = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_2 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_3 = eq(UInt<32>("hac000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_4 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_6 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_6 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_7 = eq(UInt<30>("h20000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_8 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_10 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -222,26 +225,26 @@ circuit TopOrigin : node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_14 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_16 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_18 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_16 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_17 = eq(UInt<30>("h30000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_18 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_19 = eq(UInt<30>("h34000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_20 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_22 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_24 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_22 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_23 = eq(UInt<29>("h10000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_24 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_25 = eq(UInt<29>("h14000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_26 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_28 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_32 = and(id_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(id_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_34 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_35 = eq(UInt<30>("h30000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(id_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_35 = eq(UInt<28>("hc000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_36 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_37 = eq(UInt<30>("h20000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_38 = mux(_csignals_T_37, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -358,124 +361,124 @@ circuit TopOrigin : node _csignals_T_144 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_145 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 171:19] - node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 172:19] + node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 178:19] + node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 179:19] node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 179:19] - node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 180:19] - node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 181:19] - node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 182:19] + node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 186:19] + node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 187:19] + node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 188:19] + node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 189:19] node _id_op2_data_T_4 = mux(_id_op2_data_T_3, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_op2_data_T_5 = mux(_id_op2_data_T_2, id_imm_j_sext, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_op2_data_T_6 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 271:22] - node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:{33,42}] - node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 271:{33,42}] - node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 15:20 271:{33,42}] - node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 271:{33,59}] - node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 271:{33,59}] - node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 274:27] - node _T_1 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9] - node _T_2 = eq(_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9] - node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9] - node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9] - node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9] - node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9] - node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9] - node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9] - node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9] - node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9] - node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] - node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] - node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] - node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] - node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] - node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] - node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] - node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] - node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] - node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] - node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] - node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] - node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] - node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] - node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9] - node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9] - node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9] - node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9] - io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 56:16] - io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 253:16] - io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 254:15] - io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 255:17] - io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 274:11] - regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 106:12] - regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 106:12] - regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 106:12] - regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 114:12] - regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12] - regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12] + node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 275:22] + node _T_1 = neq(wb_reg_wb_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:50] + node _T_2 = and(_T, _T_1) @[src/main/scala/micore/Core.scala 275:32] + node _GEN_0 = validif(_T_2, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 275:59 276:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/micore/Core.scala 275:59 276:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:59 276:12 15:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 275:59 276:29] + node _GEN_4 = validif(_T_2, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 275:59 276:29] + node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 280:27] + node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9] + node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9] + node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9] + node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] + node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] + node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] + node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] + node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] + node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] + node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] + node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 291:9] + node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 291:9] + node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 292:9] + node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 292:9] + node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 293:9] + node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 293:9] + node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9] + node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9] + node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9] + node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9] + node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9] + node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9] + node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9] + node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9] + node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9] + node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9] + io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 54:16] + io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 256:16] + io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 257:15] + io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 258:17] + io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 280:11] + regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 114:12] + regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12] + regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12] + regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:12] + regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 122:12] + regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:12] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 77:13] - id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 78:15] - exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 187:14 23:{27,27}] - exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 191:19 24:{32,32}] - exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 188:20 25:{33,33}] - exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 189:20 26:{33,33}] - exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 190:20 27:{33,33}] - exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 198:19 28:{32,32}] - exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 193:19 29:{32,32}] - exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 194:18 30:{31,31}] - exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 192:18 31:{31,31}] - exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 195:22 32:{35,35}] + id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 75:13] + id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 76:15] + exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 194:14 23:{27,27}] + exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 198:19 24:{32,32}] + exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 195:20 25:{33,33}] + exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 196:20 26:{33,33}] + exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 197:20 27:{33,33}] + exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 205:19 28:{32,32}] + exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 200:19 29:{32,32}] + exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 201:18 30:{31,31}] + exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 199:18 31:{31,31}] + exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 202:22 32:{35,35}] exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:{35,35,35}] - exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 196:22 34:{35,35}] - exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 197:25 35:{38,38}] - exe_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:{35,35,35}] - mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 242:14 39:{27,27}] - mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 245:19 40:{32,32}] - mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 243:20 41:{33,33}] - mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 244:20 42:{33,33}] - mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 250:19 43:{32,32}] - mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 247:18 44:{31,31}] - mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 248:18 45:{31,31}] - mem_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 249:22 46:{35,35}] - mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 246:19 47:{32,32}] - wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:18 50:{31,31}] - wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 267:17 51:{30,30}] - wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 266:18 52:{31,31}] - if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13] - printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 275:9] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 276:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 277:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 278:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 279:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 280:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 281:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 282:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 283:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 284:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 285:9] - printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 286:9] - printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9] - printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 288:9] - printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 289:9] - printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 290:9] - printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 291:9] - printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 292:9] + exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 203:22 34:{35,35}] + exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 204:25 35:{38,38}] + mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 246:14 38:{27,27}] + mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 249:19 39:{32,32}] + mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 247:20 40:{33,33}] + mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 248:20 41:{33,33}] + mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 253:19 42:{32,32}] + mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 251:18 43:{31,31}] + mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 252:18 44:{31,31}] + mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 250:19 45:{32,32}] + wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:18 48:{31,31}] + wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 270:17 49:{30,30}] + wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 269:18 50:{31,31}] + if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 53:{26,26} 72:13] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 281:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 282:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 283:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 284:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 285:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 286:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 287:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 288:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 289:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_9 @[src/main/scala/micore/Core.scala 290:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_10 @[src/main/scala/micore/Core.scala 291:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_11 @[src/main/scala/micore/Core.scala 292:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_12 @[src/main/scala/micore/Core.scala 293:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_13 @[src/main/scala/micore/Core.scala 294:9] + printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_14 @[src/main/scala/micore/Core.scala 295:9] + printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_15 @[src/main/scala/micore/Core.scala 296:9] + printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_16 @[src/main/scala/micore/Core.scala 297:9] + printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "---------------------\n") : printf_17 @[src/main/scala/micore/Core.scala 298:9] module Memory : @[src/main/scala/micore/Memory.scala 24:7] input clock : Clock @[src/main/scala/micore/Memory.scala 24:7] diff --git a/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir index 0176dec..366d2f3 100755 --- a/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Sicore_should_run_the_C_program/TopOrigin.lo.fir @@ -1,42 +1,43 @@ FIRRTL version 1.2.0 circuit TopOrigin : - module Core : @[src/main/scala/sicore/Core.scala 8:7] - input clock : Clock @[src/main/scala/sicore/Core.scala 8:7] - input reset : UInt<1> @[src/main/scala/sicore/Core.scala 8:7] - output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] - input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] - output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] - input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] - output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 9:14] - output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 9:14] - output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 9:14] + module Core : @[src/main/scala/sicore/Core.scala 9:7] + input clock : Clock @[src/main/scala/sicore/Core.scala 9:7] + input reset : UInt<1> @[src/main/scala/sicore/Core.scala 9:7] + output io_imem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] + input io_imem_inst : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] + output io_dmem_addr : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] + input io_dmem_rdata : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] + output io_dmem_wen : UInt<1> @[src/main/scala/sicore/Core.scala 10:14] + output io_dmem_wdata : UInt<32> @[src/main/scala/sicore/Core.scala 10:14] + output io_exit : UInt<1> @[src/main/scala/sicore/Core.scala 10:14] - mem regfile : @[src/main/scala/sicore/Core.scala 16:20] + mem regfile : @[src/main/scala/sicore/Core.scala 17:20] data-type => UInt<32> depth => 32 read-latency => 0 write-latency => 1 reader => rs_data_MPORT reader => rt_data_MPORT + reader => MPORT_1 writer => MPORT read-under-write => undefined reg pc_reg : UInt<32>, clock with : - reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 19:23] - node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 22:25] - node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 22:25] - node _jmp_flg_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/sicore/Core.scala 25:23] - node _jmp_flg_T_1 = eq(UInt<30>("h30000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 25:23] - node _jmp_flg_T_2 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/sicore/Core.scala 25:39] - node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 25:39] - node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 25:31] - node _csignals_T = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_2 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + reset => (UInt<1>("h0"), pc_reg) @[src/main/scala/sicore/Core.scala 20:23] + node _pc_plus4_T = add(pc_reg, UInt<32>("h4")) @[src/main/scala/sicore/Core.scala 23:25] + node pc_plus4 = tail(_pc_plus4_T, 1) @[src/main/scala/sicore/Core.scala 23:25] + node _jmp_flg_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 26:23] + node _jmp_flg_T_1 = eq(UInt<28>("hc000000"), _jmp_flg_T) @[src/main/scala/sicore/Core.scala 26:23] + node _jmp_flg_T_2 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/sicore/Core.scala 26:39] + node _jmp_flg_T_3 = eq(UInt<4>("h8"), _jmp_flg_T_2) @[src/main/scala/sicore/Core.scala 26:39] + node jmp_flg = or(_jmp_flg_T_1, _jmp_flg_T_3) @[src/main/scala/sicore/Core.scala 26:31] + node _csignals_T = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_1 = eq(UInt<32>("h8c000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_2 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_3 = eq(UInt<32>("hac000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_4 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_6 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_6 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_7 = eq(UInt<30>("h20000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_8 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_10 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -45,25 +46,25 @@ circuit TopOrigin : node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_14 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_16 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_18 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_16 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_17 = eq(UInt<30>("h30000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_18 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_19 = eq(UInt<30>("h34000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_20 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_22 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_24 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_22 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_23 = eq(UInt<29>("h10000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_24 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_25 = eq(UInt<29>("h14000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_26 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_28 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_30 = and(io_imem_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_32 = and(io_imem_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_33 = eq(UInt<30>("h30000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_34 = and(io_imem_inst, UInt<34>("h3f000003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(io_imem_inst, UInt<32>("hfc00003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_36 = mux(_csignals_T_35, UInt<5>("hd"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_37 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -83,7 +84,7 @@ circuit TopOrigin : node _csignals_T_51 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_52 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 97:16] + node _alu_out_T = eq(csignals_0, UInt<5>("h1")) @[src/main/scala/sicore/Core.scala 98:16] node _csignals_T_53 = mux(_csignals_T_35, UInt<2>("h1"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_54 = mux(_csignals_T_33, UInt<2>("h2"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_55 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -102,11 +103,11 @@ circuit TopOrigin : node _csignals_T_68 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_69 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 79:16] - node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 39:21] - node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 42:30] - node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 42:20] - node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 80:16] + node _op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 80:16] + node rs_addr = bits(io_imem_inst, 25, 21) @[src/main/scala/sicore/Core.scala 40:21] + node _rs_data_T = neq(rs_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30] + node rs_data = mux(_rs_data_T, regfile.rs_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20] + node _op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/sicore/Core.scala 81:16] node _op1_data_T_2 = mux(_op1_data_T_1, pc_reg, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node op1_data = mux(_op1_data_T, rs_data, _op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _csignals_T_70 = mux(_csignals_T_35, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -127,50 +128,50 @@ circuit TopOrigin : node _csignals_T_85 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_86 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 87:16] - node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 40:21] - node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 43:30] - node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 43:20] - node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 88:16] - node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 44:19] - node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 45:38] - node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 45:28] - node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 45:23] - node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 89:16] - node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 46:23] - node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 46:36] - node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 46:18] + node _op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 88:16] + node rt_addr = bits(io_imem_inst, 20, 16) @[src/main/scala/sicore/Core.scala 41:21] + node _rt_data_T = neq(rt_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 44:30] + node rt_data = mux(_rt_data_T, regfile.rt_data_MPORT.data, UInt<32>("h0")) @[src/main/scala/sicore/Core.scala 44:20] + node _op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 89:16] + node imm_i = bits(io_imem_inst, 15, 0) @[src/main/scala/sicore/Core.scala 45:19] + node _imm_i_sext_T = bits(imm_i, 15, 15) @[src/main/scala/sicore/Core.scala 46:38] + node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/sicore/Core.scala 46:28] + node imm_i_sext = cat(_imm_i_sext_T_1, imm_i) @[src/main/scala/sicore/Core.scala 46:23] + node _op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/sicore/Core.scala 90:16] + node _imm_j_T = bits(io_imem_inst, 25, 0) @[src/main/scala/sicore/Core.scala 47:23] + node _imm_j_T_1 = mux(UInt<1>("h0"), UInt<2>("h3"), UInt<2>("h0")) @[src/main/scala/sicore/Core.scala 47:36] + node imm_j = cat(_imm_j_T, _imm_j_T_1) @[src/main/scala/sicore/Core.scala 47:18] node _op2_data_T_3 = mux(_op2_data_T_2, imm_j, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _op2_data_T_4 = mux(_op2_data_T_1, imm_i_sext, _op2_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] node op2_data = mux(_op2_data_T, rt_data, _op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 97:42] - node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 97:42] - node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 98:16] - node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42] - node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 98:42] - node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 99:16] - node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42] - node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 100:16] - node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:41] - node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 101:16] - node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:42] - node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 102:16] - node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 102:53] - node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 102:42] - node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 102:60] - node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 103:16] - node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53] - node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 103:42] - node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 104:16] - node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 104:42] - node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:60] - node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 104:49] - node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 104:68] - node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 105:16] - node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42] - node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 105:60] - node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 105:49] - node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 106:16] + node _alu_out_T_1 = add(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_2 = tail(_alu_out_T_1, 1) @[src/main/scala/sicore/Core.scala 98:42] + node _alu_out_T_3 = eq(csignals_0, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 99:16] + node _alu_out_T_4 = sub(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 99:42] + node _alu_out_T_5 = tail(_alu_out_T_4, 1) @[src/main/scala/sicore/Core.scala 99:42] + node _alu_out_T_6 = eq(csignals_0, UInt<5>("h3")) @[src/main/scala/sicore/Core.scala 100:16] + node _alu_out_T_7 = and(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 100:42] + node _alu_out_T_8 = eq(csignals_0, UInt<5>("h4")) @[src/main/scala/sicore/Core.scala 101:16] + node _alu_out_T_9 = or(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 101:41] + node _alu_out_T_10 = eq(csignals_0, UInt<5>("h5")) @[src/main/scala/sicore/Core.scala 102:16] + node _alu_out_T_11 = xor(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 102:42] + node _alu_out_T_12 = eq(csignals_0, UInt<5>("h6")) @[src/main/scala/sicore/Core.scala 103:16] + node _alu_out_T_13 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 103:53] + node _alu_out_T_14 = dshl(op1_data, _alu_out_T_13) @[src/main/scala/sicore/Core.scala 103:42] + node _alu_out_T_15 = bits(_alu_out_T_14, 31, 0) @[src/main/scala/sicore/Core.scala 103:60] + node _alu_out_T_16 = eq(csignals_0, UInt<5>("h7")) @[src/main/scala/sicore/Core.scala 104:16] + node _alu_out_T_17 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 104:53] + node _alu_out_T_18 = dshr(op1_data, _alu_out_T_17) @[src/main/scala/sicore/Core.scala 104:42] + node _alu_out_T_19 = eq(csignals_0, UInt<5>("h8")) @[src/main/scala/sicore/Core.scala 105:16] + node _alu_out_T_20 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 105:42] + node _alu_out_T_21 = bits(op2_data, 4, 0) @[src/main/scala/sicore/Core.scala 105:60] + node _alu_out_T_22 = dshr(_alu_out_T_20, _alu_out_T_21) @[src/main/scala/sicore/Core.scala 105:49] + node _alu_out_T_23 = asUInt(_alu_out_T_22) @[src/main/scala/sicore/Core.scala 105:68] + node _alu_out_T_24 = eq(csignals_0, UInt<5>("h9")) @[src/main/scala/sicore/Core.scala 106:16] + node _alu_out_T_25 = asSInt(op1_data) @[src/main/scala/sicore/Core.scala 106:42] + node _alu_out_T_26 = asSInt(op2_data) @[src/main/scala/sicore/Core.scala 106:60] + node _alu_out_T_27 = lt(_alu_out_T_25, _alu_out_T_26) @[src/main/scala/sicore/Core.scala 106:49] + node _alu_out_T_28 = eq(csignals_0, UInt<5>("hd")) @[src/main/scala/sicore/Core.scala 107:16] node _alu_out_T_29 = mux(_alu_out_T_28, op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_30 = mux(_alu_out_T_24, _alu_out_T_27, _alu_out_T_29) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_31 = mux(_alu_out_T_19, _alu_out_T_23, _alu_out_T_30) @[src/main/scala/chisel3/util/Mux.scala 126:16] @@ -181,22 +182,22 @@ circuit TopOrigin : node _alu_out_T_36 = mux(_alu_out_T_6, _alu_out_T_7, _alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_37 = mux(_alu_out_T_3, _alu_out_T_5, _alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _alu_out_T_38 = mux(_alu_out_T, _alu_out_T_2, _alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 26:21 94:11] + node alu_out = _alu_out_T_38 @[src/main/scala/sicore/Core.scala 27:21 95:11] node _pc_next_T = mux(jmp_flg, alu_out, pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 113:16] - node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 113:41] - node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 114:16] - node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:42] - node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 114:31] + node _br_flg_T = eq(csignals_0, UInt<5>("hb")) @[src/main/scala/sicore/Core.scala 114:16] + node _br_flg_T_1 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 114:41] + node _br_flg_T_2 = eq(csignals_0, UInt<5>("hc")) @[src/main/scala/sicore/Core.scala 115:16] + node _br_flg_T_3 = eq(op1_data, op2_data) @[src/main/scala/sicore/Core.scala 115:42] + node _br_flg_T_4 = eq(_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 115:31] node _br_flg_T_5 = mux(_br_flg_T_2, _br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _br_flg_T_6 = mux(_br_flg_T, _br_flg_T_1, _br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 110:10 23:20] - node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 119:37] - node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 119:23] - node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 119:23] - node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 119:13 24:23] + node br_flg = _br_flg_T_6 @[src/main/scala/sicore/Core.scala 111:10 24:20] + node _br_target_T = dshl(imm_i_sext, UInt<5>("h2")) @[src/main/scala/sicore/Core.scala 120:37] + node _br_target_T_1 = add(pc_reg, _br_target_T) @[src/main/scala/sicore/Core.scala 120:23] + node _br_target_T_2 = tail(_br_target_T_1, 1) @[src/main/scala/sicore/Core.scala 120:23] + node br_target = bits(_br_target_T_2, 31, 0) @[src/main/scala/sicore/Core.scala 120:13 25:23] node pc_next = mux(br_flg, br_target, _pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 41:21] + node rd_addr = bits(io_imem_inst, 15, 11) @[src/main/scala/sicore/Core.scala 42:21] node _csignals_T_87 = mux(_csignals_T_35, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_88 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_89 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] @@ -251,60 +252,89 @@ circuit TopOrigin : node _csignals_T_136 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node _csignals_T_137 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 130:15] - node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 131:15] + node _wb_data_T = eq(csignals_5, UInt<3>("h2")) @[src/main/scala/sicore/Core.scala 131:15] + node _wb_data_T_1 = eq(csignals_5, UInt<3>("h3")) @[src/main/scala/sicore/Core.scala 132:15] node _wb_data_T_2 = mux(_wb_data_T_1, pc_plus4, alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] node wb_data = mux(_wb_data_T, io_dmem_rdata, _wb_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 136:15] - node _T_1 = neq(rd_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:36] - node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 136:25] - node _GEN_0 = validif(_T_2, rd_addr) @[src/main/scala/sicore/Core.scala 136:45 137:12] - node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 136:45 137:12] - node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 136:45 137:12 16:20] - node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 136:45 137:22] - node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 136:45 137:22] - node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 140:20] - node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 143:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 143:9] - node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 144:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 144:9] - node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 145:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 145:9] - node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 146:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:9] - node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 147:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 147:9] - node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 148:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 148:9] - node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 149:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 149:9] - node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 150:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 150:9] - io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 20:16] - io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 122:16] - io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 123:15] - io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 124:17] - io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 140:11] - regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 42:47] - regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 42:47] - regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 42:47] - regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 43:47] - regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47] - regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47] + node _wb_addr_T = eq(csignals_5, UInt<3>("h1")) @[src/main/scala/sicore/Core.scala 140:15] + node _wb_addr_T_1 = bits(io_imem_inst, 31, 26) @[src/main/scala/sicore/Core.scala 140:33] + node _wb_addr_T_2 = eq(_wb_addr_T_1, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 140:42] + node _wb_addr_T_3 = and(_wb_addr_T, _wb_addr_T_2) @[src/main/scala/sicore/Core.scala 140:26] + node _wb_addr_T_4 = and(io_imem_inst, UInt<32>("hfc000000")) @[src/main/scala/sicore/Core.scala 141:13] + node _wb_addr_T_5 = eq(UInt<28>("hc000000"), _wb_addr_T_4) @[src/main/scala/sicore/Core.scala 141:13] + node _wb_addr_T_6 = mux(_wb_addr_T_5, UInt<5>("h1f"), rt_addr) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node wb_addr = mux(_wb_addr_T_3, rd_addr, _wb_addr_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _T = eq(csignals_4, UInt<2>("h1")) @[src/main/scala/sicore/Core.scala 146:15] + node _T_1 = neq(wb_addr, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:36] + node _T_2 = and(_T, _T_1) @[src/main/scala/sicore/Core.scala 146:25] + node _GEN_0 = validif(_T_2, wb_addr) @[src/main/scala/sicore/Core.scala 146:45 147:12] + node _GEN_1 = validif(_T_2, clock) @[src/main/scala/sicore/Core.scala 146:45 147:12] + node _GEN_2 = mux(_T_2, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 146:45 147:12 17:20] + node _GEN_3 = validif(_T_2, UInt<1>("h1")) @[src/main/scala/sicore/Core.scala 146:45 147:22] + node _GEN_4 = validif(_T_2, wb_data) @[src/main/scala/sicore/Core.scala 146:45 147:22] + node _io_exit_T = eq(io_imem_inst, UInt<32>("h114514")) @[src/main/scala/sicore/Core.scala 150:20] + node _T_3 = asUInt(reset) @[src/main/scala/sicore/Core.scala 153:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 153:9] + node _T_5 = asUInt(reset) @[src/main/scala/sicore/Core.scala 154:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 154:9] + node _T_7 = asUInt(reset) @[src/main/scala/sicore/Core.scala 155:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 155:9] + node _T_9 = asUInt(reset) @[src/main/scala/sicore/Core.scala 156:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 156:9] + node _T_11 = asUInt(reset) @[src/main/scala/sicore/Core.scala 157:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 157:9] + node _T_13 = asUInt(reset) @[src/main/scala/sicore/Core.scala 158:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 158:9] + node _T_15 = asUInt(reset) @[src/main/scala/sicore/Core.scala 159:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 159:9] + node _T_17 = asUInt(reset) @[src/main/scala/sicore/Core.scala 160:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 160:9] + node _T_19 = asUInt(reset) @[src/main/scala/sicore/Core.scala 161:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 161:9] + node _T_21 = asUInt(reset) @[src/main/scala/sicore/Core.scala 162:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 162:9] + node _T_23 = asUInt(reset) @[src/main/scala/sicore/Core.scala 164:9] + node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 164:9] + node _T_25 = asUInt(reset) @[src/main/scala/sicore/Core.scala 165:9] + node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 165:9] + node _T_27 = asUInt(reset) @[src/main/scala/sicore/Core.scala 166:9] + node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 166:9] + node _T_29 = asUInt(reset) @[src/main/scala/sicore/Core.scala 167:9] + node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/sicore/Core.scala 167:9] + io_imem_addr <= pc_reg @[src/main/scala/sicore/Core.scala 21:16] + io_dmem_addr <= alu_out @[src/main/scala/sicore/Core.scala 123:16] + io_dmem_wen <= bits(csignals_3, 0, 0) @[src/main/scala/sicore/Core.scala 124:15] + io_dmem_wdata <= rt_data @[src/main/scala/sicore/Core.scala 125:17] + io_exit <= _io_exit_T @[src/main/scala/sicore/Core.scala 150:11] + regfile.rs_data_MPORT.addr <= rs_addr @[src/main/scala/sicore/Core.scala 43:47] + regfile.rs_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 43:47] + regfile.rs_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 43:47] + regfile.rt_data_MPORT.addr <= rt_addr @[src/main/scala/sicore/Core.scala 44:47] + regfile.rt_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 44:47] + regfile.rt_data_MPORT.clk <= clock @[src/main/scala/sicore/Core.scala 44:47] + regfile.MPORT_1.addr <= rt_addr @[src/main/scala/sicore/Core.scala 161:40] + regfile.MPORT_1.en <= UInt<1>("h1") @[src/main/scala/sicore/Core.scala 161:40] + regfile.MPORT_1.clk <= clock @[src/main/scala/sicore/Core.scala 161:40] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 19:{23,23} 36:10] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 143:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 144:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_2 @[src/main/scala/sicore/Core.scala 145:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_3 @[src/main/scala/sicore/Core.scala 146:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_4 @[src/main/scala/sicore/Core.scala 147:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_5 @[src/main/scala/sicore/Core.scala 148:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_6 @[src/main/scala/sicore/Core.scala 149:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "---------------\n") : printf_7 @[src/main/scala/sicore/Core.scala 150:9] + pc_reg <= mux(reset, UInt<32>("h0"), pc_next) @[src/main/scala/sicore/Core.scala 20:{23,23} 37:10] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "---------------\n") : printf @[src/main/scala/sicore/Core.scala 153:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "io.imem.inst: 0x%x\n", io_imem_inst) : printf_1 @[src/main/scala/sicore/Core.scala 154:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst) : printf_2 @[src/main/scala/sicore/Core.scala 155:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "pc_next: 0x%x\n", pc_next) : printf_3 @[src/main/scala/sicore/Core.scala 156:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "exe_fun: 0x%x\n", csignals_0) : printf_4 @[src/main/scala/sicore/Core.scala 157:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "rs_addr: 0x%x\n", rs_addr) : printf_5 @[src/main/scala/sicore/Core.scala 158:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "rt_addr: 0x%x\n", rt_addr) : printf_6 @[src/main/scala/sicore/Core.scala 159:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "rd_addr: 0x%x\n", rd_addr) : printf_7 @[src/main/scala/sicore/Core.scala 160:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "reg: 0x%x\n", regfile.MPORT_1.data) : printf_8 @[src/main/scala/sicore/Core.scala 161:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "rf_wen: 0x%x\n", csignals_4) : printf_9 @[src/main/scala/sicore/Core.scala 162:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "rs_data: 0x%x\n", rs_data) : printf_10 @[src/main/scala/sicore/Core.scala 164:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "rt_data: 0x%x\n", rt_data) : printf_11 @[src/main/scala/sicore/Core.scala 165:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_data: 0x%x\n", wb_data) : printf_12 @[src/main/scala/sicore/Core.scala 166:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------\n") : printf_13 @[src/main/scala/sicore/Core.scala 167:9] module Memory : @[src/main/scala/sicore/Memory.scala 24:7] input clock : Clock @[src/main/scala/sicore/Memory.scala 24:7]