diff --git a/TopOrigin.sv b/TopOrigin.sv index 8600283..002ff0d 100755 --- a/TopOrigin.sv +++ b/TopOrigin.sv @@ -53,52 +53,47 @@ module Core( output [31:0] io_gp ); - wire [31:0] mem_wb_data; - wire exe_jmp_flg; - wire exe_br_flg; - wire [31:0] _regfile_ext_R1_data; - wire [31:0] _regfile_ext_R2_data; - reg [31:0] id_reg_pc; - reg [31:0] id_reg_inst; - reg [31:0] exe_reg_pc; - reg [4:0] exe_reg_wb_addr; - reg [31:0] exe_reg_op1_data; - reg [31:0] exe_reg_op2_data; - reg [31:0] exe_reg_rs2_data; - reg [4:0] exe_reg_exe_fun; - reg [1:0] exe_reg_mem_wen; - reg [1:0] exe_reg_rf_wen; - reg [2:0] exe_reg_wb_sel; - reg [31:0] exe_reg_imm_b_sext; - reg [31:0] mem_reg_pc; - reg [4:0] mem_reg_wb_addr; - reg [31:0] mem_reg_rs2_data; - reg [1:0] mem_reg_mem_wen; - reg [1:0] mem_reg_rf_wen; - reg [2:0] mem_reg_wb_sel; - reg [31:0] mem_reg_alu_out; - reg [4:0] wb_reg_wb_addr; - reg [1:0] wb_reg_rf_wen; - reg [31:0] wb_reg_wb_data; - reg [31:0] if_reg_pc; - wire _id_inst_T = exe_br_flg | exe_jmp_flg; - wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; - wire stall_flg = + wire [31:0] mem_wb_data; + wire exe_jmp_flg; + wire exe_br_flg; + wire [31:0] _regfile_ext_R1_data; + wire [31:0] _regfile_ext_R2_data; + reg [31:0] id_reg_pc; + reg [31:0] id_reg_inst; + reg [31:0] exe_reg_pc; + reg [4:0] exe_reg_wb_addr; + reg [31:0] exe_reg_op1_data; + reg [31:0] exe_reg_op2_data; + reg [31:0] exe_reg_rs2_data; + reg [4:0] exe_reg_exe_fun; + reg [1:0] exe_reg_mem_wen; + reg [1:0] exe_reg_rf_wen; + reg [2:0] exe_reg_wb_sel; + reg [31:0] exe_reg_imm_b_sext; + reg [31:0] mem_reg_pc; + reg [4:0] mem_reg_wb_addr; + reg [31:0] mem_reg_rs2_data; + reg [1:0] mem_reg_mem_wen; + reg [1:0] mem_reg_rf_wen; + reg [2:0] mem_reg_wb_sel; + reg [31:0] mem_reg_alu_out; + reg [4:0] wb_reg_wb_addr; + reg [1:0] wb_reg_rf_wen; + reg [31:0] wb_reg_wb_data; + reg [31:0] if_reg_pc; + wire _id_inst_T = exe_br_flg | exe_jmp_flg; + wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; + wire stall_flg = _id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; - wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; - wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; - wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; - wire [31:0] id_rs1_data = - id_inst[25:21] == 5'h0 - ? 32'h0 - : id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2 - ? mem_wb_data - : id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5 - ? wb_reg_wb_data - : _regfile_ext_R2_data; - wire [31:0] id_rs2_data = + wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; + wire _id_rs1_data_T = id_inst[25:21] == 5'h0; + wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; + wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2; + wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; + wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5; + wire [31:0] id_rs2_data = id_inst[20:16] == 5'h0 ? 32'h0 : id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 @@ -106,24 +101,31 @@ module Core( : id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 ? wb_reg_wb_data : _regfile_ext_R1_data; - wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; - wire _csignals_T_5 = _GEN == 17'h20; - wire [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]}; - wire _csignals_T_7 = _GEN_0 == 20'h80000; - wire _csignals_T_9 = _GEN == 17'h22; - wire _csignals_T_11 = _GEN == 17'h24; - wire _csignals_T_13 = _GEN == 17'h25; - wire _csignals_T_15 = _GEN == 17'h26; - wire _csignals_T_17 = _GEN_0 == 20'hC0000; - wire _csignals_T_19 = _GEN_0 == 20'hD0000; - wire _csignals_T_21 = _GEN == 17'h2A; - wire _csignals_T_23 = _GEN_0 == 20'h40000; - wire _csignals_T_25 = _GEN_0 == 20'h50000; - wire _csignals_T_27 = id_inst == 32'hC000000; - wire _csignals_T_29 = {id_inst[31:22], id_inst[9:0]} == 20'h78000; - wire _GEN_1 = _csignals_T_23 | _csignals_T_25; - wire _GEN_2 = _csignals_T_21 | _GEN_1; - wire [2:0] _csignals_T_70 = + wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; + wire _csignals_T_5 = _GEN == 17'h20; + wire _csignals_T_7 = id_inst[31:28] == 4'h8; + wire _csignals_T_9 = _GEN == 17'h22; + wire _csignals_T_11 = _GEN == 17'h24; + wire _csignals_T_13 = _GEN == 17'h25; + wire _csignals_T_15 = _GEN == 17'h26; + wire _csignals_T_17 = id_inst[31:28] == 4'hC; + wire _csignals_T_19 = id_inst[31:28] == 4'hD; + wire _csignals_T_21 = _GEN == 17'h2A; + wire _csignals_T_23 = id_inst[31:28] == 4'h4; + wire _csignals_T_25 = id_inst[31:28] == 4'h5; + wire _csignals_T_27 = id_inst[31:28] == 4'h3; + wire _csignals_T_29 = id_inst[31:23] == 9'h1E0; + wire _GEN_0 = _csignals_T_27 | _csignals_T_29; + wire [4:0] _csignals_T_31 = {4'h0, _GEN_0}; + wire _GEN_1 = _csignals_T_5 | _csignals_T_7; + wire _GEN_2 = _csignals_T_23 | _csignals_T_25; + wire _GEN_3 = _csignals_T_21 | _GEN_2; + wire [1:0] csignals_1 = + _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 + | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 + ? 2'h1 + : _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29}; + wire [2:0] _csignals_T_70 = _csignals_T_5 ? 3'h1 : _csignals_T_7 @@ -132,28 +134,28 @@ module Core( ? 3'h1 : _csignals_T_17 | _csignals_T_19 ? 3'h2 - : _GEN_2 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1}; - wire [3:0][31:0] _GEN_3 = - {{{27'h0, id_inst[15:11]}}, {32'h0}, {id_reg_pc}, {id_rs1_data}}; - wire [31:0] id_op1_data = - _GEN_3[_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_2 - ? 2'h0 - : _csignals_T_27 ? 2'h1 : {_csignals_T_29, 1'h0}]; - wire [33:0] id_op2_data = + : _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1}; + wire [1:0] _csignals_T_87 = {1'h0, _GEN_0}; + wire _GEN_4 = + _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 + | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21; + wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29}; + wire _id_op1_data_T = csignals_1 == 2'h1; + wire _id_op1_data_T_1 = csignals_1 == 2'h2; + wire [35:0] id_op2_data = _csignals_T_70 == 3'h1 - ? {2'h0, id_rs2_data} + ? {4'h0, id_rs2_data} : _csignals_T_70 == 3'h2 - ? {2'h0, {16{id_inst[15]}}, id_inst[15:0]} + ? {4'h0, {16{id_inst[15]}}, id_inst[15:0]} : _csignals_T_70 == 3'h3 - ? {2'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]} + ? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]} : _csignals_T_70 == 3'h4 - ? {{6{id_inst[23]}}, id_inst[25:0], 2'h0} - : {2'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0}; - wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data; - wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; - wire [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]}; - wire [31:0] _exe_alu_out_T_46 = + ? {{6{id_inst[23]}}, id_inst[25:0], 4'h0} + : {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0}; + wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data; + wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; + wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]}; + wire [31:0] _exe_alu_out_T_46 = exe_reg_exe_fun == 5'h1 ? _exe_alu_out_T_30 : exe_reg_exe_fun == 5'h2 @@ -167,9 +169,9 @@ module Core( : exe_reg_exe_fun == 5'h6 ? _exe_alu_out_T_14[31:0] : exe_reg_exe_fun == 5'h7 - ? exe_reg_op1_data >> _GEN_4 + ? exe_reg_op1_data >> _GEN_5 : exe_reg_exe_fun == 5'h8 - ? $signed($signed(exe_reg_op1_data) >>> _GEN_4) + ? $signed($signed(exe_reg_op1_data) >>> _GEN_5) : exe_reg_exe_fun == 5'h9 ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} @@ -180,7 +182,7 @@ module Core( : exe_reg_exe_fun == 5'h12 ? exe_reg_op1_data : 32'h0; - wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data; + wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data; assign exe_br_flg = exe_reg_exe_fun == 5'hB ? _exe_br_flg_T_3 @@ -193,18 +195,56 @@ module Core( `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset) begin + automatic logic [31:0] id_rs1_data = + _id_rs1_data_T + ? 32'h0 + : _id_rs1_data_T_3 + ? mem_wb_data + : _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data; $fwrite(32'h80000002, "---------------------\n"); - $fwrite(32'h80000002, "if_reg_pc: 0x%x\n", if_reg_pc); $fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc); $fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst); $fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst); + $fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]); + $fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]); + $fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]); + $fwrite(32'h80000002, "id_exe_fun: 0x%x\n", + _GEN_1 + ? 5'h1 + : _csignals_T_9 + ? 5'h2 + : _csignals_T_11 + ? 5'h3 + : _csignals_T_13 + ? 5'h4 + : _csignals_T_15 + ? 5'h5 + : _csignals_T_17 + ? 5'h3 + : _csignals_T_19 + ? 5'h4 + : _csignals_T_21 + ? 5'h9 + : _csignals_T_23 + ? 5'hB + : _csignals_T_25 + ? 5'hC + : _csignals_T_31); + $fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1); + $fwrite(32'h80000002, "id_op1_data: 0x%x\n", + _id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0); + $fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70); + $fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data); + $fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0); + $fwrite(32'h80000002, "id_rf_wen: 0x%x\n", + _GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87); + $fwrite(32'h80000002, "id_wb_sel: 0x%x\n", + _GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100); $fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data); $fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data); - $fwrite(32'h80000002, "exe_reg_pc: 0x%x\n", exe_reg_pc); - $fwrite(32'h80000002, "exe_reg_op1_data: 0x%x\n", id_op1_data); - $fwrite(32'h80000002, "exe_reg_op2_data: 0x%x\n", id_op2_data); $fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46); $fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc); + $fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out); $fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data); $fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data); $fwrite(32'h80000002, "---------------------\n"); @@ -238,8 +278,6 @@ module Core( if_reg_pc <= 32'h400000; end else begin - automatic logic _GEN_5; - _GEN_5 = _csignals_T_27 | _csignals_T_29; if (~stall_flg) id_reg_pc <= if_reg_pc; if (_id_inst_T) @@ -248,10 +286,23 @@ module Core( id_reg_inst <= io_imem_inst; exe_reg_pc <= id_reg_pc; exe_reg_wb_addr <= id_inst[15:11]; - exe_reg_op1_data <= id_op1_data; + if (_id_op1_data_T) begin + if (_id_rs1_data_T) + exe_reg_op1_data <= 32'h0; + else if (_id_rs1_data_T_3) + exe_reg_op1_data <= mem_wb_data; + else if (_id_rs1_data_T_6) + exe_reg_op1_data <= wb_reg_wb_data; + else + exe_reg_op1_data <= _regfile_ext_R2_data; + end + else if (_id_op1_data_T_1) + exe_reg_op1_data <= id_reg_pc; + else + exe_reg_op1_data <= 32'h0; exe_reg_op2_data <= id_op2_data[31:0]; exe_reg_rs2_data <= id_rs2_data; - if (_csignals_T_5 | _csignals_T_7) + if (_GEN_1) exe_reg_exe_fun <= 5'h1; else if (_csignals_T_9) exe_reg_exe_fun <= 5'h2; @@ -272,23 +323,22 @@ module Core( else if (_csignals_T_25) exe_reg_exe_fun <= 5'hC; else - exe_reg_exe_fun <= {4'h0, _GEN_5}; + exe_reg_exe_fun <= _csignals_T_31; exe_reg_mem_wen <= 2'h0; - if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 - | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21) begin + if (_GEN_4) begin exe_reg_rf_wen <= 2'h1; exe_reg_wb_sel <= 3'h1; end - else if (_GEN_1) begin + else if (_GEN_2) begin exe_reg_rf_wen <= 2'h0; exe_reg_wb_sel <= 3'h0; end else begin - exe_reg_rf_wen <= {1'h0, _GEN_5}; + exe_reg_rf_wen <= _csignals_T_87; if (_csignals_T_27) exe_reg_wb_sel <= 3'h3; else - exe_reg_wb_sel <= {2'h0, _csignals_T_29}; + exe_reg_wb_sel <= _csignals_T_100; end exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0}; mem_reg_pc <= exe_reg_pc; diff --git a/project/project/metals.sbt b/project/project/metals.sbt deleted file mode 100755 index e069ffa..0000000 --- a/project/project/metals.sbt +++ /dev/null @@ -1,8 +0,0 @@ -// format: off -// DO NOT EDIT! This file is auto-generated. - -// This file enables sbt-bloop to create bloop config files. - -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6") - -// format: on diff --git a/project/project/project/metals.sbt b/project/project/project/metals.sbt deleted file mode 100755 index e069ffa..0000000 --- a/project/project/project/metals.sbt +++ /dev/null @@ -1,8 +0,0 @@ -// format: off -// DO NOT EDIT! This file is auto-generated. - -// This file enables sbt-bloop to create bloop config files. - -addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "2.0.6") - -// format: on diff --git a/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource b/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource deleted file mode 100755 index 9d348e7..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/sync/copy-resource +++ /dev/null @@ -1 +0,0 @@ -[[{},{}],{}] \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs deleted file mode 100755 index 6ed8b2a..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ --1633561639 \ No newline at end of file diff --git a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output deleted file mode 100755 index f3e910b..0000000 --- a/project/project/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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a/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/_global/update/_global/streams/out b/project/project/project/target/streams/_global/update/_global/streams/out deleted file mode 100755 index 1ed207b..0000000 --- a/project/project/project/target/streams/_global/update/_global/streams/out +++ /dev/null @@ -1,8 +0,0 @@ -[warn] sbt-bloop_2.12_1.0-2.0.6.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar -[debug] not up to date. inChanged = false, force = false -[debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build")... -[info] Updating  -[info] Resolved dependencies -[info] Fetching artifacts of  -[info] Fetched artifacts of  -[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/project/"), "micore-build-build-build") diff --git a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous deleted file mode 100755 index d3be71e..0000000 --- a/project/project/project/target/streams/compile/_global/_global/compileOutputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data deleted file mode 100755 index 0637a08..0000000 --- a/project/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data +++ /dev/null @@ -1 +0,0 @@ -[] \ No newline at end of file diff --git a/project/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/project/target/streams/compile/bspReporter/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compile/_global/streams/out b/project/project/project/target/streams/compile/compile/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/project/target/streams/compile/compileIncremental/_global/streams/export deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/project/target/streams/compile/compileIncremental/_global/streams/out deleted file mode 100755 index 9cca155..0000000 --- a/project/project/project/target/streams/compile/compileIncremental/_global/streams/out +++ /dev/null @@ -1,6 +0,0 @@ -[debug] [zinc] IncrementalCompile ----------- -[debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries -[debug] current source = Set() -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/project/target/streams/compile/copyResources/_global/streams/out deleted file mode 100755 index f25042f..0000000 --- a/project/project/project/target/streams/compile/copyResources/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Copy resource mappings:  -[debug]   diff --git a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export deleted file mode 100755 index 98ed4e4..0000000 --- a/project/project/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/project/target/streams/compile/exportedProducts/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/compile/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index 98ed4e4..0000000 --- a/project/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/project/target/streams/compile/incOptions/_global/streams/out deleted file mode 100755 index 7231079..0000000 --- a/project/project/project/target/streams/compile/incOptions/_global/streams/out +++ /dev/null @@ -1,5 +0,0 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] About to delete class files: -[debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/project/target/streams/compile/managedClasspath/_global/streams/export deleted file mode 100755 index 98ed4e4..0000000 --- a/project/project/project/target/streams/compile/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/project/target/streams/compile/scalacOptions/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/project/target/streams/compile/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export deleted file mode 100755 index aef0f5a..0000000 --- a/project/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/runtime/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index e2c8173..0000000 --- a/project/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export deleted file mode 100755 index aef0f5a..0000000 --- a/project/project/project/target/streams/runtime/fullClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8d01fa8..0000000 --- a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export deleted file mode 100755 index e2c8173..0000000 --- a/project/project/project/target/streams/runtime/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp deleted file mode 100755 index ab6c5ba..0000000 --- a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp +++ /dev/null @@ -1 +0,0 @@ -644413116 \ No newline at end of file diff --git a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp deleted file mode 100755 index 07ec83b..0000000 --- a/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/project/project/target/streams/_global/ivyConfiguration/_global/streams/out b/project/project/target/streams/_global/ivyConfiguration/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/ivySbt/_global/streams/out b/project/project/target/streams/_global/ivySbt/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/moduleSettings/_global/streams/out b/project/project/target/streams/_global/moduleSettings/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/projectDescriptors/_global/streams/out b/project/project/target/streams/_global/projectDescriptors/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/project/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/_global/update/_global/streams/out b/project/project/target/streams/_global/update/_global/streams/out deleted file mode 100755 index 6743020..0000000 --- a/project/project/target/streams/_global/update/_global/streams/out +++ /dev/null @@ -1,3 +0,0 @@ -[debug] not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")... -[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build") diff --git a/project/project/target/streams/_global/updateClassifiers/_global/streams/out b/project/project/target/streams/_global/updateClassifiers/_global/streams/out deleted file mode 100755 index 4d9a95a..0000000 --- a/project/project/target/streams/_global/updateClassifiers/_global/streams/out +++ /dev/null @@ -1,6 +0,0 @@ -[warn] sbt-bloop_2.12_1.0-2.0.6-sources.jar no longer exists at /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6-sources.jar -[debug] not up to date. inChanged = false, force = false -[debug] Updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build")... -[info] Fetching artifacts of  -[info] Fetched artifacts of  -[debug] Done updating ProjectRef(uri("file:/home/gh0s7/nfs/project/micore/project/project/"), "micore-build-build") diff --git a/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs b/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs deleted file mode 100755 index f40f285..0000000 --- a/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ -1606726032 \ No newline at end of file diff --git a/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output b/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output deleted file mode 100755 index a2b073f..0000000 --- a/project/project/target/streams/_global/updateClassifiers/_global/streams/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file diff --git a/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out b/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out deleted file mode 100755 index d06cba1..0000000 --- a/project/project/target/streams/_global/updateSbtClassifiers/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Other repositories: -[debug] Default repositories: diff --git a/project/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/project/target/streams/compile/_global/_global/compileOutputs/previous deleted file mode 100755 index 29633ad..0000000 --- a/project/project/target/streams/compile/_global/_global/compileOutputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data deleted file mode 100755 index 0637a08..0000000 --- a/project/project/target/streams/compile/_global/_global/discoveredMainClasses/data +++ /dev/null @@ -1 +0,0 @@ -[] \ No newline at end of file diff --git a/project/project/target/streams/compile/bloopGenerate/_global/streams/out b/project/project/target/streams/compile/bloopGenerate/_global/streams/out deleted file mode 100755 index c6e9ce7..0000000 --- a/project/project/target/streams/compile/bloopGenerate/_global/streams/out +++ /dev/null @@ -1,4 +0,0 @@ -[debug] [micore-build-build] Classpath dependencies List() -[debug] [micore-build-build] Dependencies from configurations List() -[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json' -[success] Generated .bloop/micore-build-build.json diff --git a/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out b/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out deleted file mode 100755 index d94fa9e..0000000 --- a/project/project/target/streams/compile/bloopPostGenerate/_global/streams/out +++ /dev/null @@ -1 +0,0 @@ -[debug] Running postGenerate for micore-build-build diff --git a/project/project/target/streams/compile/bspReporter/_global/streams/out b/project/project/target/streams/compile/bspReporter/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compile/_global/streams/out b/project/project/target/streams/compile/compile/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/export b/project/project/target/streams/compile/compileIncremental/_global/streams/export deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/compileIncremental/_global/streams/out b/project/project/target/streams/compile/compileIncremental/_global/streams/out deleted file mode 100755 index 9cca155..0000000 --- a/project/project/target/streams/compile/compileIncremental/_global/streams/out +++ /dev/null @@ -1,6 +0,0 @@ -[debug] [zinc] IncrementalCompile ----------- -[debug] IncrementalCompile.incrementalCompile -[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries -[debug] current source = Set() -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set()) -[debug] Full compilation, no sources in previous analysis. diff --git a/project/project/target/streams/compile/copyResources/_global/streams/out b/project/project/target/streams/compile/copyResources/_global/streams/out deleted file mode 100755 index f25042f..0000000 --- a/project/project/target/streams/compile/copyResources/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Copy resource mappings:  -[debug]   diff --git a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/project/target/streams/compile/dependencyClasspath/_global/streams/export deleted file mode 100755 index 7d0296f..0000000 --- a/project/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/exportedProducts/_global/streams/export b/project/project/target/streams/compile/exportedProducts/_global/streams/export deleted file mode 100755 index 454272b..0000000 --- a/project/project/target/streams/compile/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index 7d0296f..0000000 --- a/project/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/2.2.0/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.4.2/launcher-interface-1.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.8.5/caffeine-2.8.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.1.2/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.17.1/log4j-api-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.17.1/log4j-core-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.17.1/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.9.3/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.9.3/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.9.5/compiler-interface-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.9.5/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.12/file-tree-views-2.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.13.0/jna-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.13.0/jna-platform-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.9.1/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal/3.19.0/jline-terminal-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.9.5/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.9.5/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.9.5/zinc_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.9.1/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.9.5/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/jline/jline/2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jna/3.19.0/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jansi/3.19.0/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/checkerframework/checker-qual/3.4.1/checker-qual-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/errorprone/error_prone_annotations/2.4.0/error_prone_annotations-2.4.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.12/2.10.0/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-apache-http_2.12/0.7.0/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-reader/3.19.0/jline-reader-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-builtins/3.19.0/jline-builtins-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-jawn-parser_2.12/0.9.1/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.9.5/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.9.5/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.9.5/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.9.5/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.9.1/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.6.2/ipcsocket-1.6.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/openhft/zero-allocation-hashing/0.10.1/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/2.1.0/jansi-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.7.0/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/incOptions/_global/streams/out b/project/project/target/streams/compile/incOptions/_global/streams/out deleted file mode 100755 index 66abc73..0000000 --- a/project/project/target/streams/compile/incOptions/_global/streams/out +++ /dev/null @@ -1,5 +0,0 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] About to delete class files: -[debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/project/target/streams/compile/internalDependencyClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/managedClasspath/_global/streams/export b/project/project/target/streams/compile/managedClasspath/_global/streams/export deleted file mode 100755 index 7d0296f..0000000 --- a/project/project/target/streams/compile/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/2.2.0/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.4.2/launcher-interface-1.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.8.5/caffeine-2.8.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.1.2/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.17.1/log4j-api-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.17.1/log4j-core-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.17.1/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.9.3/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.9.3/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.9.5/compiler-interface-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.9.5/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.12/file-tree-views-2.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.13.0/jna-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.13.0/jna-platform-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.9.1/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal/3.19.0/jline-terminal-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.9.5/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.9.5/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.9.5/zinc_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.9.1/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.9.5/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/jline/jline/2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jna/3.19.0/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal-jansi/3.19.0/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/checkerframework/checker-qual/3.4.1/checker-qual-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/errorprone/error_prone_annotations/2.4.0/error_prone_annotations-2.4.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.12/2.10.0/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-apache-http_2.12/0.7.0/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-reader/3.19.0/jline-reader-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-builtins/3.19.0/jline-builtins-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-jawn-parser_2.12/0.9.1/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.9.5/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.9.5/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.9.5/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.9.5/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.9.1/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.6.2/ipcsocket-1.6.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/openhft/zero-allocation-hashing/0.10.1/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/2.1.0/jansi-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.7.0/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar diff --git a/project/project/target/streams/compile/scalacOptions/_global/streams/out b/project/project/target/streams/compile/scalacOptions/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/project/target/streams/compile/unmanagedClasspath/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/project/target/streams/compile/unmanagedJars/_global/streams/export deleted file mode 100755 index 8b13789..0000000 --- a/project/project/target/streams/compile/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/project/project/target/streams/it/bloopGenerate/_global/streams/out b/project/project/target/streams/it/bloopGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/it/bloopPostGenerate/_global/streams/out b/project/project/target/streams/it/bloopPostGenerate/_global/streams/out deleted file mode 100755 index e69de29..0000000 diff --git a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export deleted file mode 100755 index bde13f8..0000000 --- a/project/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar diff --git a/project/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/project/target/streams/runtime/exportedProducts/_global/streams/export deleted file mode 100755 index 454272b..0000000 --- a/project/project/target/streams/runtime/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export deleted file mode 100755 index a7fbfb8..0000000 --- a/project/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export index 4006493..faf6770 100755 --- a/project/target/streams/compile/exportedProducts/_global/streams/export +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export index 7d0296f..98ed4e4 100755 --- a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -1 +1 @@ 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+/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-compiler.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-reflect.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-xml_2.12-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-library-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/launcher-interface-1.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/caffeine-2.8.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-api-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-core-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-interface-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/file-tree-views-2.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jna-platform-5.13.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-apiinfo_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/core-macros_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-cache_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-control_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/protocol_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-core_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/template-resolver-0.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-position_2.12-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-compile-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/util-interface-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-2.14.7-sbt-a1b0ffbb8f64bb820f4f84a0c07a0c0964507493.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jna-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-terminal-jansi-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/disruptor-3.4.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-reflect-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/checker-qual-3.4.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/error_prone_annotations-2.4.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-collection-compat_2.12-2.10.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/slf4j-api-1.7.36.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-compiler-2.12.18.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jsch-0.1.54.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-apache-http_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ivy-2.3.0-sbt-396a783bba347016e7fe30dacc60d355be607fe2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-reader-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-builtins-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-agent-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/test-interface-1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-jawn-parser_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-scalajson_2.12-1.0.0-M4.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/compiler-bridge_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-classfile_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-core_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist_2.12-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sjson-new-murmurhash_2.12-0.9.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ipcsocket-1.6.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/scala-parser-combinators_2.12-1.1.2.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zero-allocation-hashing-0.10.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jansi-2.1.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/gigahorse-core_2.12-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/jline-style-3.19.0.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/sbinary_2.12-0.5.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/reactive-streams-1.0.3.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/org.scala-sbt/sbt/1.9.7/config-1.4.2.jar diff --git a/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out index 44649e0..96aaeb5 100755 --- a/project/target/streams/compile/incOptions/_global/streams/out +++ b/project/target/streams/compile/incOptions/_global/streams/out @@ -1,5 +1,5 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] About to delete class files: [debug] We backup class files: -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak +[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export index 7d0296f..98ed4e4 100755 --- a/project/target/streams/compile/managedClasspath/_global/streams/export +++ b/project/target/streams/compile/managedClasspath/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.9.7/sbt-1.9.7.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.9.7/main_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.9.7/io_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.9.7/logic_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.9.7/actions_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.9.7/main-settings_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.9.7/run_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.9.7/command_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.9.7/collections_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.9.7/scripted-plugin_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.9.7/zinc-lm-integration_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.9.7/util-logging_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/2.2.0/scala-xml_2.12-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.4.2/launcher-interface-1.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.8.5/caffeine-2.8.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.1.2/lm-coursier-shaded_2.12-2.1.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.17.1/log4j-api-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.17.1/log4j-core-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.17.1/log4j-slf4j-impl-2.17.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.9.3/librarymanagement-core_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.9.3/librarymanagement-ivy_2.12-1.9.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.9.5/compiler-interface-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.9.5/zinc-compile_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.12/file-tree-views-2.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.13.0/jna-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.13.0/jna-platform-5.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.9.7/util-relation_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.9.7/completion_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.9.7/task-system_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.9.7/tasks_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.9.7/testing_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.9.7/util-tracking_2.12-1.9.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.9.1/sjson-new-scalajson_2.12-0.9.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-terminal/3.19.0/jline-terminal-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.9.5/zinc-classpath_2.12-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/ma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gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-apache-httpasyncclient/0.7.0/shaded-apache-httpasyncclient-0.7.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/jline/jline-style/3.19.0/jline-style-3.19.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist-core-assembly/1.9.5/zinc-persist-core-assembly-1.9.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.1/sbinary_2.12-0.5.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.6.1/ssl-config-core_2.12-0.6.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.3/reactive-streams-1.0.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.4.2/config-1.4.2.jar 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diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export index b0b5605..69ab39c 100755 --- a/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export index 4006493..faf6770 100755 --- a/project/target/streams/runtime/exportedProducts/_global/streams/export +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export index a7fbfb8..e2c8173 100755 --- a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export index b0b5605..69ab39c 100755 --- a/project/target/streams/runtime/fullClasspath/_global/streams/export +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -1 +1 @@ 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diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export index 4006493..faf6770 100755 --- a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes +/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export index a7fbfb8..e2c8173 100755 --- a/project/target/streams/runtime/managedClasspath/_global/streams/export +++ b/project/target/streams/runtime/managedClasspath/_global/streams/export @@ -1 +1 @@ -/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar 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diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala index 2ab76c0..162c274 100755 --- a/src/main/scala/common/Consts.scala +++ b/src/main/scala/common/Consts.scala @@ -28,22 +28,18 @@ object Consts { val ALU_SLTU = 10.U(EXE_FUN_LEN.W) // 无符号比较小于操作 val BR_BEQ = 11.U(EXE_FUN_LEN.W) // 分支相等 val BR_BNE = 12.U(EXE_FUN_LEN.W) // 分支不等 - val BR_BLT = 13.U(EXE_FUN_LEN.W) // 有符号小于分支 - val BR_BGE = 14.U(EXE_FUN_LEN.W) // 有符号大于等于分支 - val BR_BLTU = 15.U(EXE_FUN_LEN.W) // 无符号小于分支 - val BR_BGEU = 16.U(EXE_FUN_LEN.W) // 无符号大于等于分支 - val ALU_JALR = 17.U(EXE_FUN_LEN.W) // JALR跳转（MIPS中没有JALR，但可以模拟） - val ALU_COPY1 = 18.U(EXE_FUN_LEN.W) // 复制操作 + val ALU_JALR = 13.U(EXE_FUN_LEN.W) // JALR跳转（MIPS中没有JALR，但可以模拟） + val ALU_COPY1 = 14.U(EXE_FUN_LEN.W) // 复制操作 // 操作数选择 val OP1_LEN = 2 // 操作数1的选择宽度为2位 val OP1_X = 0.U(OP1_LEN.W) // 未定义操作数1 - val OP1_RS = 1.U(OP1_LEN.W) // 选择rs + val OP1_RS1 = 1.U(OP1_LEN.W) // 选择rs val OP1_PC = 2.U(OP1_LEN.W) // 选择PC val OP2_LEN = 3 // 操作数2的选择宽度为3位 val OP2_X = 0.U(OP2_LEN.W) // 未定义操作数2 - val OP2_RT = 1.U(OP2_LEN.W) // 选择rt + val OP2_RS2 = 1.U(OP2_LEN.W) // 选择rt val OP2_IMI = 2.U(OP2_LEN.W) // 立即数操作数2（immI） val OP2_IMS = 3.U(OP2_LEN.W) // 立即数操作数2（immS） val OP2_IMJ = 4.U(OP2_LEN.W) // 立即数操作数2（immJ） diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala index f424fff..5b0971f 100755 --- a/src/main/scala/micore/Core.scala +++ b/src/main/scala/micore/Core.scala @@ -10,7 +10,6 @@ class Core extends Module { val imem = Flipped(new ImemPortIo()) val dmem = Flipped(new DmemPortIo()) val exit = Output(Bool()) - val gp = Output(UInt(WORD_LEN.W)) }) val regfile = Mem(32, UInt(WORD_LEN.W)) @@ -85,10 +84,10 @@ class Core extends Module { ) // ********* Decode (ID) Stage ********* - val id_rs1_addr_b = id_reg_inst(25, 21) // MIPS rs字段 - val id_rs2_addr_b = id_reg_inst(20, 16) // MIPS rt字段 + val id_rs1_addr_b = id_reg_inst(25, 21) + val id_rs2_addr_b = id_reg_inst(20, 16) -// 与EX数据冒险 -> stall + // 与EX数据冒险 -> stall val id_rs1_data_hazard = (exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr) val id_rs2_data_hazard = @@ -98,16 +97,16 @@ class Core extends Module { val id_inst = Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst) - val id_rs1_addr = id_inst(25, 21) // MIPS rs字段 - val id_rs2_addr = id_inst(20, 16) // MIPS rt字段 - val id_wb_addr = id_inst(15, 11) // MIPS rt字段（写回地址） + val id_rs1_addr = id_inst(25, 21) + val id_rs2_addr = id_inst(20, 16) + val id_wb_addr = id_inst(15, 11) val mem_wb_data = Wire(UInt(WORD_LEN.W)) val id_rs1_data = MuxCase( regfile(id_rs1_addr), Seq( (id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通 + ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEN直通 ((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 ) ) @@ -115,43 +114,51 @@ class Core extends Module { regfile(id_rs2_addr), Seq( (id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W), - ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通 + ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEN直通 ((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通 ) ) - val id_imm_i = id_inst(15, 0) // MIPS立即数字段 + val id_imm_i = id_inst(15, 0) val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i) - val id_imm_s = Cat(id_inst(15, 11), id_inst(25, 21)) // 生成 10 位的立即数字段 - val id_imm_s_sext = Cat(Fill(22, id_imm_s(9)), id_imm_s) // 符号扩展到 32 位 - val id_imm_b = Cat(id_inst(15, 0), 0.U(2.W)) // MIPS分支指令的立即数字段 + val id_imm_b = Cat( + id_inst(15, 0), + 0.U(2.W) + ) val id_imm_b_sext = Cat(Fill(14, id_imm_b(17)), id_imm_b) - val id_imm_j = Cat(id_inst(25, 0), 0.U(2.W)) // MIPS跳转指令的立即数字段 - val id_imm_j_sext = Cat(Fill(6, id_imm_j(25)), id_imm_j, 0.U(2.W)) - val id_imm_u = id_inst(15, 0) // MIPS lui指令的立即数字段 + val id_imm_j = Cat( + id_inst(25, 0), + 0.U(2.W) + ) + val id_imm_j_sext = Cat(Fill(6, id_imm_j(25)), id_imm_j) + val id_imm_u = id_inst(15, 0) val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U)) - val id_imm_z = id_inst(15, 11) // MIPS立即数字段 - val id_imm_z_uext = Cat(Fill(27, 0.U), id_imm_z) + val id_imm_shamt = id_inst(10, 6) val csignals = ListLookup( id_inst, - List(ALU_X, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X), + List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), Array( - LW -> List(ALU_ADD, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_MEM), - SW -> List(ALU_ADD, OP1_RS, OP2_IMS, MEN_S, REN_X, WB_X), - ADD -> List(ALU_ADD, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - ADDI -> List(ALU_ADD, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU), - SUB -> List(ALU_SUB, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - AND -> List(ALU_AND, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - OR -> List(ALU_OR, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - XOR -> List(ALU_XOR, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - ANDI -> List(ALU_AND, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU), - ORI -> List(ALU_OR, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU), - SLT -> List(ALU_SLT, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU), - BEQ -> List(BR_BEQ, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X), - BNE -> List(BR_BNE, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X), - JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC), - LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU) + LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_S, WB_MEM), + SW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_S, REN_S, WB_MEM), + ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), + SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), + ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_X, WB_ALU), + SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), + BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X), + SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_ALU), + JR -> List(ALU_X, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X), + JAL -> List(ALU_X, OP1_PC, OP2_X, MEN_X, REN_X, WB_X), + LUI -> List(ALU_X, OP1_X, OP2_IMU, MEN_X, REN_X, WB_ALU), + NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X) ) ) @@ -161,18 +168,16 @@ class Core extends Module { val id_op1_data = MuxCase( 0.U(WORD_LEN.W), Seq( - (id_op1_sel === OP1_RS) -> id_rs1_data, + (id_op1_sel === OP1_RS1) -> id_rs1_data, (id_op1_sel === OP1_PC) -> id_reg_pc - // (id_op1_sel === OP1_IMZ) -> id_imm_z_uext ) ) val id_op2_data = MuxCase( 0.U(WORD_LEN.W), Seq( - (id_op2_sel === OP2_RT) -> id_rs2_data, + (id_op2_sel === OP2_RS2) -> id_rs2_data, (id_op2_sel === OP2_IMI) -> id_imm_i_sext, - (id_op2_sel === OP2_IMS) -> id_imm_s_sext, (id_op2_sel === OP2_IMJ) -> id_imm_j_sext, (id_op2_sel === OP2_IMU) -> id_imm_u_shifted ) @@ -188,10 +193,8 @@ class Core extends Module { exe_reg_mem_wen := id_mem_wen exe_reg_rf_wen := id_rf_wen exe_reg_imm_i_sext := id_imm_i_sext - exe_reg_imm_s_sext := id_imm_s_sext exe_reg_imm_b_sext := id_imm_b_sext exe_reg_imm_u_shifted := id_imm_u_shifted - exe_reg_imm_z_uext := id_imm_z_uext exe_reg_exe_fun := id_exe_fun // ********* Execute (EX) Stage ********* @@ -206,7 +209,7 @@ class Core extends Module { (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data( 4, 0 - )), + ))(31, 0), (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data( 4, 0 @@ -226,8 +229,8 @@ class Core extends Module { exe_br_flg := MuxCase( false.B, Seq( - (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data).asBool, - (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data).asBool + (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data), + (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data) ) ) @@ -268,33 +271,40 @@ class Core extends Module { when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data } // ********* Debugging ********* - io.gp := regfile(3) io.exit := (id_reg_inst === UNIMP) printf(p"---------------------\n") - // printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") + printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n") printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n") printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n") printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n") - printf(p"id_rs1_addr: 0x${Hexadecimal(id_rs1_addr)}\n") - printf(p"id_rs2_addr: 0x${Hexadecimal(id_rs2_addr)}\n") - printf(p"id_wb_addr: 0x${Hexadecimal(id_wb_addr)}\n") - printf(p"id_exe_fun: 0x${Hexadecimal(id_exe_fun)}\n") - printf(p"id_op1_sel: 0x${Hexadecimal(id_op1_sel)}\n") - printf(p"id_op1_data: 0x${Hexadecimal(id_op1_data)}\n") - printf(p"id_op2_sel: 0x${Hexadecimal(id_op2_sel)}\n") - printf(p"id_op2_data: 0x${Hexadecimal(id_op2_data)}\n") - printf(p"id_mem_wen: 0x${Hexadecimal(id_mem_wen)}\n") - printf(p"id_rf_wen: 0x${Hexadecimal(id_rf_wen)}\n") - printf(p"id_wb_sel: 0x${Hexadecimal(id_wb_sel)}\n") printf(p"id_rs1_data: 0x${Hexadecimal(id_rs1_data)}\n") printf(p"id_rs2_data: 0x${Hexadecimal(id_rs2_data)}\n") - // printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") - // printf(p"exe_reg_op1_data: 0x${Hexadecimal(id_op1_data)}\n") - // printf(p"exe_reg_op2_data: 0x${Hexadecimal(id_op2_data)}\n") + printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n") + printf(p"exe_reg_op1_data: 0x${Hexadecimal(id_op1_data)}\n") + printf(p"exe_reg_op2_data: 0x${Hexadecimal(id_op2_data)}\n") printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n") printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n") - printf(p"mem_reg_alu_out: 0x${Hexadecimal(mem_reg_alu_out)}\n") printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n") - printf(p"wb_reg_wb_data: 0${Hexadecimal(wb_reg_wb_data)}\n") + printf(p"wb_reg_wb_data: 0x${Hexadecimal(wb_reg_wb_data)}\n") printf(p"---------------------\n") + + // io.gp := regfile(3) + // printf(p"---------------\n") + // printf( + // p"io.pc: 0x${Hexadecimal(pc_reg)}\ninst: 0x${Hexadecimal(inst)} \n" + // ) + // // printf( + // // p"rs1_addr: 0x${Hexadecimal(rs1_addr)} rs2_addr: 0x${Hexadecimal(rs2_addr)} wb_addr: 0x${Hexadecimal(wb_addr)}\n" + // // ) + // // printf(p"gp: 0x${Hexadecimal(regfile(3))}\n") + // printf(p"rs1_addr: 0x${Hexadecimal(rs1_addr)}\n") + // // printf(p"rs2_data: 0x${Hexadecimal(rs2_data)}\n") + // printf(p"wb_addr: 0x${Hexadecimal(wb_addr)}\n") + // printf(p"rs1_data: 0x${Hexadecimal(rs1_data)}\n") + // printf(p"wb_data: 0x${Hexadecimal(wb_data)}\n") + // // printf(p"dmem.addr: 0x${Hexadecimal(io.dmem.addr)}\n") + // // printf(p"dmem.wen: ${io.dmem.wen}\n") + // // printf(p"dmem.wdata: 0x${Hexadecimal(io.dmem.wdata)}\n") + // printf(p"---------------\n") + } diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala index 43cecdc..40d003d 100755 --- a/src/main/scala/micore/Memory.scala +++ b/src/main/scala/micore/Memory.scala @@ -2,7 +2,6 @@ package micore import chisel3._ import chisel3.util._ -import chisel3.util.experimental.loadMemoryFromFile import common.Consts._ import chisel3.util.experimental.loadMemoryFromFileInline diff --git a/src/main/scala/micore/Top.scala b/src/main/scala/micore/Top.scala index 70becd8..77e8c23 100755 --- a/src/main/scala/micore/Top.scala +++ b/src/main/scala/micore/Top.scala @@ -8,14 +8,12 @@ import common.Consts._ class TopOrigin extends Module { val io = IO(new Bundle { val exit = Output(Bool()) - val gp = Output(UInt(WORD_LEN.W)) }) val core = Module(new Core()) val memory = Module(new Memory()) core.io.imem <> memory.io.imem core.io.dmem <> memory.io.dmem io.exit := core.io.exit - io.gp := core.io.gp } /** Generate Verilog sources and save it in file diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar old mode 100755 new mode 100644 index 8c2320e..a9270ff Binary files a/target/scala-2.13/-name-_2.13-0.1.0.jar and b/target/scala-2.13/-name-_2.13-0.1.0.jar differ diff --git a/target/scala-2.13/zinc/inc_compile_2.13.zip b/target/scala-2.13/zinc/inc_compile_2.13.zip old mode 100755 new mode 100644 index c9de057..f980154 Binary files a/target/scala-2.13/zinc/inc_compile_2.13.zip and b/target/scala-2.13/zinc/inc_compile_2.13.zip differ diff --git a/target/streams/_global/update/_global/streams/out b/target/streams/_global/update/_global/streams/out index 58b0a88..e0eb067 100755 --- a/target/streams/_global/update/_global/streams/out +++ b/target/streams/_global/update/_global/streams/out @@ -1,3 +1,3 @@ -[debug] not up to date. inChanged = true, force = false +[debug] not up to date. inChanged = false, force = true [debug] Updating ... [debug] Done updating  diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous index 422b9f2..6e27812 100755 --- a/target/streams/compile/_global/_global/compileOutputs/previous +++ b/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class","/home/gh0s7/project/ddca/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]] \ No newline at end of file diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index debaacf..f3c3491 100755 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -2,27 +2,28 @@ [debug] IncrementalCompile.incrementalCompile [debug] previous = Stamps for: 14 products, 5 sources, 2 libraries [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala) -[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set()) +[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala), unmodified = ...),Set(),Set(),API Changes: Set()) [debug]  [debug] Initial source changes: [debug]  removed: Set() [debug]  added: Set() -[debug]  modified: Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala) +[debug]  modified: Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala) [debug] Invalidated products: Set() [debug] External API changes: API Changes: Set() [debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(common.Consts, micore.Core) +[debug] Initial directly invalidated classes: Set(micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo) [debug] Sources indirectly invalidated by: [debug]  product: Set() [debug]  binary dep: Set() [debug]  external source: Set() -[debug] All initially invalidated classes: Set(common.Consts, micore.Core) -[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala) -[debug] Initial set of included nodes: common.Consts, micore.Core +[debug] All initially invalidated classes: Set(micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo) +[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala) +[debug] Initial set of included nodes: micore.TopOrigin, micore.ImemPortIo, micore.Core, micore.Memory, common.Consts, micore.DmemPortIo +[debug] Recompiling all sources: number of invalidated sources > 50.0 percent of all sources [debug] compilation cycle 1 -[info] compiling 2 Scala sources to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ... +[info] compiling 5 Scala sources to /home/gh0s7/project/ddca/micore/target/scala-2.13/classes ... [debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar. -[debug] [zinc] Running cached compiler 6e7cf61b for Scala compiler version 2.13.12 +[debug] [zinc] Running cached compiler 53b08b84 for Scala compiler version 2.13.12 [debug] [zinc] The Scala compiler is invoked with: [debug]  -language:reflectiveCalls [debug]  -deprecation @@ -33,26 +34,6 @@ [debug]  -bootclasspath [debug]  /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar [debug]  -classpath -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar -[debug] Invalidating (transitively) by inheritance from common.Consts... -[debug] Initial set of included nodes: common.Consts -[debug] Invalidated by transitive inheritance dependency: Set(common.Consts) -[debug] None of the modified names appears in source file of micore.TopOrigin. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of micore.ImemPortIo. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of micore.Core. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of micore.Memory. This dependency is not being considered for invalidation. -[debug] None of the modified names appears in source file of micore.DmemPortIo. This dependency is not being considered for invalidation. -[debug] Change NamesChange(common.Consts,ModifiedNames(changes = UsedName(OP1_IMZ,[Default]))) invalidates 1 classes due to The common.Consts has the following regular definitions changed: -[debug]  UsedName(OP1_IMZ,[Default]). -[debug]  > by transitive inheritance: Set(common.Consts) -[debug]  >  -[debug]  >  -[debug]   -[debug] New invalidations: -[debug] Initial set of included nodes:  -[debug] Previously invalidated, but (transitively) depend on new invalidations: -[debug] Final step, transitive dependencies: -[debug]  Set() -[debug] No classes were invalidated. -[debug] Scala compilation took 2.955256556 s +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar +[debug] Scala compilation took 3.902681144 s [debug] done compiling diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/compile/exportedProductJars/_global/streams/export +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export index 21cdc14..3c15dcc 100755 --- a/target/streams/compile/exportedProducts/_global/streams/export +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes +/home/gh0s7/project/ddca/micore/target/scala-2.13/classes diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out index a11cadf..4a34f08 100755 --- a/target/streams/compile/incOptions/_global/streams/out +++ b/target/streams/compile/incOptions/_global/streams/out @@ -1,17 +1,47 @@ -[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak +[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak [debug] About to delete class files: -[debug]  Consts$.class -[debug]  Consts.class [debug]  Core$$anon$1.class +[debug]  Consts$.class +[debug]  TopOrigin$delayedInit$body.class +[debug]  Instructions$.class +[debug]  TopOrigin.class +[debug]  TopOrigin$$anon$1.class +[debug]  Memory$$anon$1.class +[debug]  ImemPortIo.class [debug]  Core.class +[debug]  Consts.class +[debug]  DmemPortIo.class +[debug]  Memory.class +[debug]  TopOrigin$.class +[debug]  Instructions.class [debug] We backup class files: -[debug]  Consts$.class -[debug]  Consts.class [debug]  Core$$anon$1.class +[debug]  Consts$.class +[debug]  TopOrigin$delayedInit$body.class +[debug]  Instructions$.class +[debug]  TopOrigin.class +[debug]  TopOrigin$$anon$1.class +[debug]  Memory$$anon$1.class +[debug]  ImemPortIo.class [debug]  Core.class +[debug]  Consts.class +[debug]  DmemPortIo.class +[debug]  Memory.class +[debug]  TopOrigin$.class +[debug]  Instructions.class [debug] Registering generated classes: -[debug]  Consts.class -[debug]  Consts$.class [debug]  Core$$anon$1.class +[debug]  Consts$.class +[debug]  TopOrigin$delayedInit$body.class +[debug]  Instructions$.class +[debug]  TopOrigin.class +[debug]  TopOrigin$$anon$1.class +[debug]  Memory$$anon$1.class +[debug]  ImemPortIo.class [debug]  Core.class -[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak +[debug]  Consts.class +[debug]  DmemPortIo.class +[debug]  Memory.class +[debug]  TopOrigin$.class +[debug]  Instructions.class +[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs index d9a0ca3..66c2ab4 100755 --- a/target/streams/compile/packageBin/_global/streams/inputs +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ --627113868 \ No newline at end of file +-1320494222 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out index 766e80b..f991401 100755 --- a/target/streams/compile/packageBin/_global/streams/out +++ b/target/streams/compile/packageBin/_global/streams/out @@ -1,35 +1,51 @@ -[debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... +[debug] Packaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... [debug] Input file mappings: +[debug]  gcd +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd +[debug]  gcd/GcdInputBundle.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class +[debug]  gcd/GcdOutputBundle.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class +[debug]  gcd/DecoupledGcd.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class +[debug]  gcd/GCD.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class +[debug]  gcd/GCD$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class +[debug]  gcd/GCD$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class +[debug]  gcd/GCD$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class [debug]  common -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common [debug]  common/Consts$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts$.class [debug]  common/Consts.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Consts.class [debug]  common/Instructions$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions$.class [debug]  common/Instructions.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/common/Instructions.class [debug]  micore -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore -[debug]  micore/Core$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore [debug]  micore/Core.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class -[debug]  micore/DmemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core.class +[debug]  micore/Core$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Core$$anon$1.class [debug]  micore/ImemPortIo.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class -[debug]  micore/Memory$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/ImemPortIo.class +[debug]  micore/DmemPortIo.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/DmemPortIo.class [debug]  micore/Memory.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class -[debug]  micore/TopOrigin$$anon$1.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class -[debug]  micore/TopOrigin$.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class -[debug]  micore/TopOrigin$delayedInit$body.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory.class +[debug]  micore/Memory$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class [debug]  micore/TopOrigin.class -[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin.class +[debug]  micore/TopOrigin$.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$.class +[debug]  micore/TopOrigin$$anon$1.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class +[debug]  micore/TopOrigin$delayedInit$body.class +[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class [debug] Done packaging. diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output index ccc866e..4e9041f 100755 --- a/target/streams/compile/packageBin/_global/streams/output +++ b/target/streams/compile/packageBin/_global/streams/output @@ -1 +1 @@ --1359482768 \ No newline at end of file +1488086236 \ No newline at end of file diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export index 112ae53..ddc45ce 100755 --- a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/re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diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/runtime/exportedProductJars/_global/streams/export +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export index 112ae53..ddc45ce 100755 --- a/target/streams/runtime/fullClasspathAsJars/_global/streams/export +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -1 +1 @@ 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maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export index 671555b..26fe379 100755 --- a/target/streams/runtime/internalDependencyAsJars/_global/streams/export +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -1 +1 @@ -/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar +/home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir index 49b023a..908c5e5 100755 --- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir +++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir @@ -10,220 +10,210 @@ circuit TopOrigin : output io_dmem_wen : UInt<1> @[src/main/scala/micore/Core.scala 9:14] output io_dmem_wdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14] output io_exit : UInt<1> @[src/main/scala/micore/Core.scala 9:14] - output io_gp : UInt<32> @[src/main/scala/micore/Core.scala 9:14] - mem regfile : @[src/main/scala/micore/Core.scala 16:20] + mem regfile : @[src/main/scala/micore/Core.scala 15:20] data-type => UInt<32> depth => 32 read-latency => 0 write-latency => 1 reader => id_rs1_data_MPORT reader => id_rs2_data_MPORT - reader => io_gp_MPORT writer => MPORT read-under-write => undefined reg id_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 20:26] + reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 19:26] reg id_reg_inst : UInt<32>, clock with : - reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 21:28] + reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 20:28] reg exe_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 24:27] + reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 23:27] reg exe_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 25:32] + reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 24:32] reg exe_reg_op1_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 26:33] + reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 25:33] reg exe_reg_op2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 27:33] + reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 26:33] reg exe_reg_rs2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 28:33] + reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 27:33] reg exe_reg_exe_fun : UInt<5>, clock with : - reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 29:32] + reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 28:32] reg exe_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 30:32] + reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 29:32] reg exe_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 31:31] + reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 30:31] reg exe_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 32:31] + reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 31:31] reg exe_reg_imm_i_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 33:35] + reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 32:35] reg exe_reg_imm_s_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 34:35] + reset => (UInt<1>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:35] reg exe_reg_imm_b_sext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 35:35] + reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 34:35] reg exe_reg_imm_u_shifted : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 36:38] + reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 35:38] reg exe_reg_imm_z_uext : UInt<32>, clock with : - reset => (UInt<1>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 37:35] + reset => (UInt<1>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:35] reg mem_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 40:27] + reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 39:27] reg mem_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 41:32] + reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 40:32] reg mem_reg_op1_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 42:33] + reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 41:33] reg mem_reg_rs2_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 43:33] + reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 42:33] reg mem_reg_mem_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 44:32] + reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 43:32] reg mem_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 45:31] + reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 44:31] reg mem_reg_wb_sel : UInt<3>, clock with : - reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 46:31] + reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 45:31] reg mem_reg_imm_z_uext : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 47:35] + reset => (UInt<1>("h0"), mem_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 46:35] reg mem_reg_alu_out : UInt<32>, clock with : - reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 48:32] + reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 47:32] reg wb_reg_wb_addr : UInt<5>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 51:31] + reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 50:31] reg wb_reg_rf_wen : UInt<2>, clock with : - reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 52:30] + reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 51:30] reg wb_reg_wb_data : UInt<32>, clock with : - reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 53:31] + reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 52:31] reg if_reg_pc : UInt<32>, clock with : - reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 56:26] - node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 66:31] - node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 66:31] - node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 93:21] - node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 88:34] - node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 93:50] - node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 93:32] - node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 93:77] - node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 93:59] - node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 95:21] - node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 89:34] - node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 95:50] - node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 95:32] - node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 95:77] - node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 95:59] - node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 96:36] - node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 60:23 96:13] + reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 55:26] + node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 65:31] + node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 65:31] + node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21] + node id_rs1_addr_b = bits(id_reg_inst, 19, 15) @[src/main/scala/micore/Core.scala 87:34] + node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:50] + node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32] + node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:77] + node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:59] + node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21] + node id_rs2_addr_b = bits(id_reg_inst, 24, 20) @[src/main/scala/micore/Core.scala 88:34] + node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:50] + node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32] + node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:77] + node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:59] + node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36] + node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 59:23 95:13] node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 236:34] - node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 236:15 63:25] - node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 201:24] - node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:58] - node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 201:58] - node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 202:24] - node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:58] - node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 202:58] - node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 203:24] - node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 203:58] - node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 204:24] - node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 204:57] - node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 205:24] - node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 205:58] - node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 206:24] - node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 206:77] - node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 206:58] - node _exe_alu_out_T_15 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 210:24] - node _exe_alu_out_T_16 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 210:77] - node _exe_alu_out_T_17 = dshr(exe_reg_op1_data, _exe_alu_out_T_16) @[src/main/scala/micore/Core.scala 210:58] - node _exe_alu_out_T_18 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 214:24] - node _exe_alu_out_T_19 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 214:58] - node _exe_alu_out_T_20 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 214:84] - node _exe_alu_out_T_21 = dshr(_exe_alu_out_T_19, _exe_alu_out_T_20) @[src/main/scala/micore/Core.scala 214:65] - node _exe_alu_out_T_22 = asUInt(_exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 217:10] - node _exe_alu_out_T_23 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 218:24] - node _exe_alu_out_T_24 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 218:58] - node _exe_alu_out_T_25 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 218:84] - node _exe_alu_out_T_26 = lt(_exe_alu_out_T_24, _exe_alu_out_T_25) @[src/main/scala/micore/Core.scala 218:65] - node _exe_alu_out_T_27 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 219:24] - node _exe_alu_out_T_28 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 219:59] - node _exe_alu_out_T_29 = eq(exe_reg_exe_fun, UInt<5>("h11")) @[src/main/scala/micore/Core.scala 220:24] - node _exe_alu_out_T_30 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 220:60] - node _exe_alu_out_T_31 = tail(_exe_alu_out_T_30, 1) @[src/main/scala/micore/Core.scala 220:60] - node _exe_alu_out_T_32 = not(UInt<32>("h1")) @[src/main/scala/micore/Core.scala 220:83] - node _exe_alu_out_T_33 = and(_exe_alu_out_T_31, _exe_alu_out_T_32) @[src/main/scala/micore/Core.scala 220:80] - node _exe_alu_out_T_34 = eq(exe_reg_exe_fun, UInt<5>("h12")) @[src/main/scala/micore/Core.scala 222:24] - node _exe_alu_out_T_35 = mux(_exe_alu_out_T_34, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_36 = mux(_exe_alu_out_T_29, _exe_alu_out_T_33, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_37 = mux(_exe_alu_out_T_27, _exe_alu_out_T_28, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_38 = mux(_exe_alu_out_T_23, _exe_alu_out_T_26, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_39 = mux(_exe_alu_out_T_18, _exe_alu_out_T_22, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_40 = mux(_exe_alu_out_T_15, _exe_alu_out_T_17, _exe_alu_out_T_39) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_41 = mux(_exe_alu_out_T_12, _exe_alu_out_T_14, _exe_alu_out_T_40) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_42 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_41) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_43 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_42) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_44 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_43) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_45 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_44) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_alu_out_T_46 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_45) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_alu_out = bits(_exe_alu_out_T_46, 31, 0) @[src/main/scala/micore/Core.scala 198:15 64:25] + node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 239:34] + node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 239:15 62:25] + node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 204:24] + node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 204:58] + node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 204:58] + node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 205:24] + node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 205:58] + node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 205:58] + node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 206:24] + node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:58] + node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 207:24] + node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 207:57] + node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 208:24] + node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 208:58] + node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 209:24] + node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 209:77] + node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 209:58] + node _exe_alu_out_T_15 = bits(_exe_alu_out_T_14, 31, 0) @[src/main/scala/micore/Core.scala 212:9] + node _exe_alu_out_T_16 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 213:24] + node _exe_alu_out_T_17 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 213:77] + node _exe_alu_out_T_18 = dshr(exe_reg_op1_data, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 213:58] + node _exe_alu_out_T_19 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 217:24] + node _exe_alu_out_T_20 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 217:58] + node _exe_alu_out_T_21 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 217:84] + node _exe_alu_out_T_22 = dshr(_exe_alu_out_T_20, _exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 217:65] + node _exe_alu_out_T_23 = asUInt(_exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 220:10] + node _exe_alu_out_T_24 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 221:24] + node _exe_alu_out_T_25 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 221:58] + node _exe_alu_out_T_26 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 221:84] + node _exe_alu_out_T_27 = lt(_exe_alu_out_T_25, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 221:65] + node _exe_alu_out_T_28 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 222:24] + node _exe_alu_out_T_29 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 222:59] + node _exe_alu_out_T_30 = eq(exe_reg_exe_fun, UInt<5>("hd")) @[src/main/scala/micore/Core.scala 223:24] + node _exe_alu_out_T_31 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 223:60] + node _exe_alu_out_T_32 = tail(_exe_alu_out_T_31, 1) @[src/main/scala/micore/Core.scala 223:60] + node _exe_alu_out_T_33 = not(UInt<32>("h1")) @[src/main/scala/micore/Core.scala 223:83] + node _exe_alu_out_T_34 = and(_exe_alu_out_T_32, _exe_alu_out_T_33) @[src/main/scala/micore/Core.scala 223:80] + node _exe_alu_out_T_35 = eq(exe_reg_exe_fun, UInt<5>("he")) @[src/main/scala/micore/Core.scala 225:24] + node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_37 = mux(_exe_alu_out_T_30, _exe_alu_out_T_34, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_38 = mux(_exe_alu_out_T_28, _exe_alu_out_T_29, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_39 = mux(_exe_alu_out_T_24, _exe_alu_out_T_27, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_40 = mux(_exe_alu_out_T_19, _exe_alu_out_T_23, _exe_alu_out_T_39) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_41 = mux(_exe_alu_out_T_16, _exe_alu_out_T_18, _exe_alu_out_T_40) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_42 = mux(_exe_alu_out_T_12, _exe_alu_out_T_15, _exe_alu_out_T_41) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_43 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_42) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_44 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_43) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_45 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_44) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_46 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_45) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _exe_alu_out_T_47 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_46) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node exe_alu_out = _exe_alu_out_T_47 @[src/main/scala/micore/Core.scala 201:15 63:25] node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 229:24] - node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 229:57] - node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 230:24] - node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 230:58] - node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 230:39] + node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 232:24] + node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 232:57] + node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 233:24] + node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 233:58] + node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 233:39] node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 226:14 61:24] - node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 234:31] - node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 234:31] - node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 234:17 62:27] + node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 229:14 60:24] + node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 237:31] + node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 237:31] + node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 237:17 61:27] node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 78:19] - node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 82:19] + node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 77:19] + node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 81:19] node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 99:21] - node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 99:36] - node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 99:8] - node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 101:28] - node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 102:28] - node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 103:27] - node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 109:20] - node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:21] - node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:61] - node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 110:42] - node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 111:21] - node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 111:59] - node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 111:41] + node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21] + node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36] + node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8] + node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 100:28] + node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 101:28] + node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 102:27] + node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 108:20] + node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 109:21] + node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 109:61] + node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 109:42] + node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:21] + node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:59] + node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 110:41] node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 257:23] - node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 258:23] - node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 258:49] - node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 258:49] + node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 260:23] + node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 261:23] + node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 261:49] + node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 261:49] node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 105:25 254:15] + node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 104:25 257:15] node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_wb_data, _id_rs1_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 117:20] - node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] - node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:61] - node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 118:42] - node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 119:21] - node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 119:59] - node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 119:41] + node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 116:20] + node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:21] + node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:61] + node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:42] + node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21] + node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:59] + node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 118:41] node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16] node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_wb_data, _id_rs2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 123:25] - node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 124:44] - node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 124:31] - node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 124:26] - node _id_imm_s_T = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 125:29] - node _id_imm_s_T_1 = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 125:46] - node id_imm_s = cat(_id_imm_s_T, _id_imm_s_T_1) @[src/main/scala/micore/Core.scala 125:21] - node _id_imm_s_sext_T = bits(id_imm_s, 9, 9) @[src/main/scala/micore/Core.scala 126:44] - node _id_imm_s_sext_T_1 = mux(_id_imm_s_sext_T, UInt<22>("h3fffff"), UInt<22>("h0")) @[src/main/scala/micore/Core.scala 126:31] - node id_imm_s_sext = cat(_id_imm_s_sext_T_1, id_imm_s) @[src/main/scala/micore/Core.scala 126:26] - node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 127:29] - node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 127:21] + node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 122:25] + node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 123:44] + node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 123:31] + node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 123:26] + node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 125:12] + node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 124:21] node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 128:44] node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 128:31] node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 128:26] - node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 129:29] + node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 130:12] node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 129:21] - node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 130:43] - node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 130:31] - node id_imm_j_sext_hi = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 130:26] - node id_imm_j_sext = cat(id_imm_j_sext_hi, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 130:26] - node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 131:25] - node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 132:44] - node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 132:29] - node id_imm_z = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 133:25] - node _id_imm_z_uext_T = mux(UInt<1>("h0"), UInt<27>("h7ffffff"), UInt<27>("h0")) @[src/main/scala/micore/Core.scala 134:31] - node id_imm_z_uext = cat(_id_imm_z_uext_T, id_imm_z) @[src/main/scala/micore/Core.scala 134:26] + node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 133:43] + node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 133:31] + node id_imm_j_sext = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 133:26] + node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 134:25] + node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 135:44] + node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 135:29] + node id_imm_shamt = bits(id_inst, 10, 6) @[src/main/scala/micore/Core.scala 136:29] node _csignals_T = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] @@ -250,253 +240,261 @@ circuit TopOrigin : node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_24 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_26 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_27 = eq(UInt<30>("h30000000"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_28 = and(id_inst, UInt<34>("h3ff800000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_29 = eq(UInt<32>("hf0000000"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] - node _csignals_T_30 = mux(_csignals_T_29, UInt<5>("h1"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_31 = mux(_csignals_T_27, UInt<5>("h1"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_32 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_31) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_33 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_34 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_33) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_35 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_36 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_35) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_37 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_38 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_39 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_40 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_41 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_42 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_43 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_44 = mux(_csignals_T_29, UInt<2>("h2"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_45 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_46 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_47 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_48 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_49 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_50 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_51 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_52 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_53 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_54 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_55 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_56 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_57 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_1 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_58 = mux(_csignals_T_29, UInt<3>("h5"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_59 = mux(_csignals_T_27, UInt<3>("h4"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_60 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_61 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_62 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_63 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_64 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_65 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_66 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_67 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_68 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_69 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_70 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_71 = mux(_csignals_T_3, UInt<3>("h3"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_72 = mux(_csignals_T_29, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_73 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_74 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_75 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_76 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_77 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_78 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_79 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_80 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_81 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_82 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_83 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_84 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_85 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_86 = mux(_csignals_T_29, UInt<2>("h1"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_87 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_88 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_89 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_90 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_91 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_92 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_93 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_94 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_95 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_96 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_97 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_98 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_99 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_100 = mux(_csignals_T_29, UInt<3>("h1"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_101 = mux(_csignals_T_27, UInt<3>("h3"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_102 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_103 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_104 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_105 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_106 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_107 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_108 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_109 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_110 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_111 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_112 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _csignals_T_113 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] - node _id_op1_data_T = eq(csignals_1, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 164:19] - node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 165:19] - node _id_op1_data_T_2 = eq(csignals_1, UInt<2>("h3")) @[src/main/scala/micore/Core.scala 166:19] - node _id_op1_data_T_3 = mux(_id_op1_data_T_2, id_imm_z_uext, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op1_data_T_4 = mux(_id_op1_data_T_1, id_reg_pc, _id_op1_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 173:19] - node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 174:19] - node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 175:19] - node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 176:19] - node _id_op2_data_T_4 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 177:19] - node _id_op2_data_T_5 = mux(_id_op2_data_T_4, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T_6 = mux(_id_op2_data_T_3, id_imm_j_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T_7 = mux(_id_op2_data_T_2, id_imm_s_sext, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _id_op2_data_T_8 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16] - node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 268:22] - node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:{33,42}] - node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 268:{33,42}] - node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 16:20 268:{33,42}] - node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 268:{33,59}] - node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 268:{33,59}] - node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 272:27] - node _T_1 = asUInt(reset) @[src/main/scala/micore/Core.scala 273:9] - node _T_2 = eq(_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 273:9] - node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9] - node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9] - node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9] - node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9] - node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9] - node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9] - node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9] - node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9] - node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9] - node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9] - node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9] - node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9] - node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9] - node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9] - node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9] - node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9] - node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9] - node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9] - node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] - node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] - node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] - node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] - node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] - node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] - node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] - node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] - node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] - node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] - node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] - node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] - node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9] - node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9] - node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9] - node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9] - node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9] - node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9] - node _T_39 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9] - node _T_40 = eq(_T_39, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9] - node _T_41 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9] - node _T_42 = eq(_T_41, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9] - node _T_43 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9] - node _T_44 = eq(_T_43, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9] - node _T_45 = asUInt(reset) @[src/main/scala/micore/Core.scala 299:9] - node _T_46 = eq(_T_45, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 299:9] - io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 57:16] - io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 250:16] - io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 251:15] - io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 252:17] - io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 272:11] - io_gp <= regfile.io_gp_MPORT.data @[src/main/scala/micore/Core.scala 271:9] - regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 107:12] - regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 107:12] - regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 107:12] - regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 115:12] - regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 115:12] - regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 115:12] - regfile.io_gp_MPORT.addr <= UInt<5>("h3") @[src/main/scala/micore/Core.scala 271:19] - regfile.io_gp_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 271:19] - regfile.io_gp_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 271:19] + node _csignals_T_26 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_27 = eq(UInt<1>("h0"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_28 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_29 = eq(UInt<2>("h2"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_30 = and(id_inst, UInt<32>("hffe0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_31 = eq(UInt<2>("h3"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_32 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_33 = eq(UInt<4>("h8"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_34 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_35 = eq(UInt<30>("h30000000"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_36 = and(id_inst, UInt<34>("h3ff800000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_37 = eq(UInt<32>("hf0000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_38 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38] + node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h0"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("h0"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h0"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("h8"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("h7"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h6"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h2"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h1"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h1"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_1 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_3 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h0"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h2"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39] + node _id_op1_data_T = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 171:19] + node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h2")) @[src/main/scala/micore/Core.scala 172:19] + node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 179:19] + node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 180:19] + node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 181:19] + node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 182:19] + node _id_op2_data_T_4 = mux(_id_op2_data_T_3, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_op2_data_T_5 = mux(_id_op2_data_T_2, id_imm_j_sext, _id_op2_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _id_op2_data_T_6 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16] + node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 271:22] + node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 271:{33,42}] + node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 271:{33,42}] + node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 15:20 271:{33,42}] + node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 271:{33,59}] + node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 271:{33,59}] + node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 274:27] + node _T_1 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9] + node _T_2 = eq(_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9] + node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9] + node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9] + node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9] + node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9] + node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9] + node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9] + node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9] + node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9] + node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9] + node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9] + node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9] + node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9] + node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9] + node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9] + node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9] + node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9] + node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9] + node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9] + node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9] + node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9] + node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9] + node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9] + node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9] + node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9] + node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9] + node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9] + node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9] + node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9] + io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 56:16] + io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 253:16] + io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 254:15] + io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 255:17] + io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 274:11] + regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 106:12] + regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 106:12] + regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 106:12] + regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 114:12] + regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 114:12] + regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 114:12] regfile.MPORT.addr <= _GEN_0 regfile.MPORT.en <= _GEN_2 regfile.MPORT.clk <= _GEN_1 regfile.MPORT.data <= _GEN_4 regfile.MPORT.mask <= _GEN_3 - id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 20:{26,26} 78:13] - id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 21:{28,28} 79:15] - exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 182:14 24:{27,27}] - exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 186:19 25:{32,32}] - exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 183:20 26:{33,33}] - exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 184:20 27:{33,33}] - exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 185:20 28:{33,33}] - exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 195:19 29:{32,32}] - exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 188:19 30:{32,32}] - exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 189:18 31:{31,31}] - exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 187:18 32:{31,31}] - exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 190:22 33:{35,35}] - exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), id_imm_s_sext) @[src/main/scala/micore/Core.scala 191:22 34:{35,35}] - exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 192:22 35:{35,35}] - exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 193:25 36:{38,38}] - exe_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), id_imm_z_uext) @[src/main/scala/micore/Core.scala 194:22 37:{35,35}] - mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 239:14 40:{27,27}] - mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 242:19 41:{32,32}] - mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 240:20 42:{33,33}] - mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 241:20 43:{33,33}] - mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 247:19 44:{32,32}] - mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 244:18 45:{31,31}] - mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 245:18 46:{31,31}] - mem_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 246:22 47:{35,35}] - mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 243:19 48:{32,32}] - wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 265:18 51:{31,31}] - wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 264:17 52:{30,30}] - wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 263:18 53:{31,31}] - if_reg_pc <= mux(reset, UInt<32>("h400000"), if_pc_next) @[src/main/scala/micore/Core.scala 56:{26,26} 75:13] - printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 273:9] - printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 275:9] - printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_2 @[src/main/scala/micore/Core.scala 276:9] - printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_3 @[src/main/scala/micore/Core.scala 277:9] - printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_rs1_addr: 0x%x\n", id_rs1_addr) : printf_4 @[src/main/scala/micore/Core.scala 278:9] - printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs2_addr: 0x%x\n", id_rs2_addr) : printf_5 @[src/main/scala/micore/Core.scala 279:9] - printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_wb_addr: 0x%x\n", id_wb_addr) : printf_6 @[src/main/scala/micore/Core.scala 280:9] - printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 281:9] - printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 282:9] - printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op1_data: 0x%x\n", id_op1_data) : printf_9 @[src/main/scala/micore/Core.scala 283:9] - printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_10 @[src/main/scala/micore/Core.scala 284:9] - printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "id_op2_data: 0x%x\n", id_op2_data) : printf_11 @[src/main/scala/micore/Core.scala 285:9] - printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "id_mem_wen: 0x%x\n", csignals_3) : printf_12 @[src/main/scala/micore/Core.scala 286:9] - printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "id_rf_wen: 0x%x\n", csignals_4) : printf_13 @[src/main/scala/micore/Core.scala 287:9] - printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "id_wb_sel: 0x%x\n", csignals_5) : printf_14 @[src/main/scala/micore/Core.scala 288:9] - printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_15 @[src/main/scala/micore/Core.scala 289:9] - printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_16 @[src/main/scala/micore/Core.scala 290:9] - printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_17 @[src/main/scala/micore/Core.scala 294:9] - printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_18 @[src/main/scala/micore/Core.scala 295:9] - printf(clock, and(and(UInt<1>("h1"), _T_40), UInt<1>("h1")), "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out) : printf_19 @[src/main/scala/micore/Core.scala 296:9] - printf(clock, and(and(UInt<1>("h1"), _T_42), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_20 @[src/main/scala/micore/Core.scala 297:9] - printf(clock, and(and(UInt<1>("h1"), _T_44), UInt<1>("h1")), "wb_reg_wb_data: 0%x\n", wb_reg_wb_data) : printf_21 @[src/main/scala/micore/Core.scala 298:9] - printf(clock, and(and(UInt<1>("h1"), _T_46), UInt<1>("h1")), "---------------------\n") : printf_22 @[src/main/scala/micore/Core.scala 299:9] + id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 19:{26,26} 77:13] + id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 20:{28,28} 78:15] + exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 187:14 23:{27,27}] + exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 191:19 24:{32,32}] + exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 188:20 25:{33,33}] + exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 189:20 26:{33,33}] + exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 190:20 27:{33,33}] + exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 198:19 28:{32,32}] + exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 193:19 29:{32,32}] + exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 194:18 30:{31,31}] + exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 192:18 31:{31,31}] + exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 195:22 32:{35,35}] + exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 33:{35,35,35}] + exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 196:22 34:{35,35}] + exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 197:25 35:{38,38}] + exe_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 36:{35,35,35}] + mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 242:14 39:{27,27}] + mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 245:19 40:{32,32}] + mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 243:20 41:{33,33}] + mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 244:20 42:{33,33}] + mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 250:19 43:{32,32}] + mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 247:18 44:{31,31}] + mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 248:18 45:{31,31}] + mem_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 249:22 46:{35,35}] + mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 246:19 47:{32,32}] + wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:18 50:{31,31}] + wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 267:17 51:{30,30}] + wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 266:18 52:{31,31}] + if_reg_pc <= mux(reset, UInt<32>("h400000"), if_pc_next) @[src/main/scala/micore/Core.scala 55:{26,26} 74:13] + printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 275:9] + printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "if_reg_pc: 0x%x\n", if_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 276:9] + printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_2 @[src/main/scala/micore/Core.scala 277:9] + printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_3 @[src/main/scala/micore/Core.scala 278:9] + printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_4 @[src/main/scala/micore/Core.scala 279:9] + printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_5 @[src/main/scala/micore/Core.scala 280:9] + printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_6 @[src/main/scala/micore/Core.scala 281:9] + printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "exe_reg_pc: 0x%x\n", exe_reg_pc) : printf_7 @[src/main/scala/micore/Core.scala 282:9] + printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "exe_reg_op1_data: 0x%x\n", id_op1_data) : printf_8 @[src/main/scala/micore/Core.scala 283:9] + printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "exe_reg_op2_data: 0x%x\n", id_op2_data) : printf_9 @[src/main/scala/micore/Core.scala 284:9] + printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_10 @[src/main/scala/micore/Core.scala 285:9] + printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_11 @[src/main/scala/micore/Core.scala 286:9] + printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_12 @[src/main/scala/micore/Core.scala 287:9] + printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "wb_reg_wb_data: 0x%x\n", wb_reg_wb_data) : printf_13 @[src/main/scala/micore/Core.scala 288:9] + printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "---------------------\n") : printf_14 @[src/main/scala/micore/Core.scala 289:9] - module Memory : @[src/main/scala/micore/Memory.scala 25:7] - input clock : Clock @[src/main/scala/micore/Memory.scala 25:7] - input reset : UInt<1> @[src/main/scala/micore/Memory.scala 25:7] - input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 26:14] - output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 26:14] - input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 26:14] - output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 26:14] - input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 26:14] - input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 26:14] + module Memory : @[src/main/scala/micore/Memory.scala 24:7] + input clock : Clock @[src/main/scala/micore/Memory.scala 24:7] + input reset : UInt<1> @[src/main/scala/micore/Memory.scala 24:7] + input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] + output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] + input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] + output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] + input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 25:14] + input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 25:14] - mem mem : @[src/main/scala/micore/Memory.scala 32:16] + mem mem : @[src/main/scala/micore/Memory.scala 31:16] data-type => UInt<8> depth => 4096 read-latency => 0 @@ -514,83 +512,83 @@ circuit TopOrigin : writer => MPORT_2 writer => MPORT_3 read-under-write => undefined - node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 39:22] - node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 39:22] - node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 39:8] - node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 40:22] - node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 40:22] - node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 40:8] - node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 41:22] - node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 41:22] - node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 41:8] - node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 42:8] - node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 38:22] - node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 38:22] - node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 38:22] - node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 47:22] - node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 47:22] - node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 47:8] - node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 48:22] - node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 48:22] - node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 48:8] - node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 49:22] - node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 49:22] - node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 49:8] - node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 50:8] - node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 46:23] - node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 46:23] - node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 46:23] - node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 55:8] - node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 55:39] - node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 56:22] - node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 56:22] - node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 56:8] - node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 56:57] - node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 57:22] - node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 57:22] - node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 57:8] - node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 57:57] - node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 58:22] - node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 58:22] - node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 58:8] - node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 58:57] - node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 54:21 55:8] - node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 54:21 55:8] - node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 32:16 54:21 55:8] - node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 54:21 55:23] - node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 54:21 55:23] - node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 54:21 56:8] - node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 54:21 56:41] - node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 54:21 57:8] - node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 54:21 57:41] - node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 54:21 58:8] - node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 54:21 58:41] - io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 38:16] - io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 46:17] - mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 39:8] - mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 40:8] - mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 41:8] - mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 42:8] - mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 42:8] - mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 42:8] - mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 47:8] - mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 48:8] - mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 49:8] - mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 50:8] - mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 50:8] - mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 50:8] + node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 38:22] + node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 38:22] + node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 38:8] + node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 39:22] + node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 39:22] + node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 39:8] + node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 40:22] + node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 40:22] + node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 40:8] + node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 41:8] + node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 37:22] + node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 37:22] + node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 37:22] + node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 46:22] + node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 46:22] + node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 46:8] + node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 47:22] + node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 47:22] + node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 47:8] + node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 48:22] + node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 48:22] + node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 48:8] + node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 49:8] + node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 45:23] + node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 45:23] + node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 45:23] + node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 54:8] + node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 54:39] + node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 55:22] + node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 55:22] + node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 55:8] + node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 55:57] + node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 56:22] + node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 56:22] + node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 56:8] + node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 56:57] + node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 57:22] + node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 57:22] + node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 57:8] + node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 57:57] + node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 53:21 54:8] + node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 53:21 54:8] + node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 31:16 53:21 54:8] + node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 53:21 54:23] + node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 53:21 54:23] + node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 53:21 55:8] + node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 53:21 55:41] + node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 53:21 56:8] + node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 53:21 56:41] + node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 53:21 57:8] + node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 53:21 57:41] + io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 37:16] + io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 45:17] + mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 38:8] + mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 38:8] + mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 38:8] + mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 39:8] + mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 40:8] + mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 41:8] + mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8] + mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 41:8] + mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 46:8] + mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 47:8] + mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 48:8] + mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 49:8] + mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 49:8] + mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 49:8] mem.MPORT.addr <= _GEN_0 mem.MPORT.en <= _GEN_2 mem.MPORT.clk <= _GEN_1 @@ -616,19 +614,17 @@ circuit TopOrigin : input clock : Clock @[src/main/scala/micore/Top.scala 8:7] input reset : UInt<1> @[src/main/scala/micore/Top.scala 8:7] output io_exit : UInt<1> @[src/main/scala/micore/Top.scala 9:14] - output io_gp : UInt<32> @[src/main/scala/micore/Top.scala 9:14] - inst core of Core @[src/main/scala/micore/Top.scala 13:20] - inst memory of Memory @[src/main/scala/micore/Top.scala 14:22] - io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 17:11] - io_gp <= core.io_gp @[src/main/scala/micore/Top.scala 18:9] + inst core of Core @[src/main/scala/micore/Top.scala 12:20] + inst memory of Memory @[src/main/scala/micore/Top.scala 13:22] + io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 16:11] core.clock <= clock core.reset <= reset - core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 15:16] - core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/micore/Top.scala 16:16] + core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 14:16] + core.io_dmem_rdata <= memory.io_dmem_rdata @[src/main/scala/micore/Top.scala 15:16] memory.clock <= clock memory.reset <= reset - memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/micore/Top.scala 15:16] - memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/micore/Top.scala 16:16] - memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/micore/Top.scala 16:16] - memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/micore/Top.scala 16:16] + memory.io_imem_addr <= core.io_imem_addr @[src/main/scala/micore/Top.scala 14:16] + memory.io_dmem_addr <= core.io_dmem_addr @[src/main/scala/micore/Top.scala 15:16] + memory.io_dmem_wen <= core.io_dmem_wen @[src/main/scala/micore/Top.scala 15:16] + memory.io_dmem_wdata <= core.io_dmem_wdata @[src/main/scala/micore/Top.scala 15:16]