From e8e6b6ddb3fd7e0f84d555cca05cfc40b9d19de0 Mon Sep 17 00:00:00 2001
From: CGH0S7 <776459475@qq.com>
Date: Mon, 30 Dec 2024 00:36:45 +0800
Subject: [PATCH] Still need to fix

---
 TopOrigin.sv                                  | 697 +++++++------
 src/hex/mem.hex                               |  44 +-
 src/main/scala/common/Consts.scala            |  30 +-
 src/main/scala/common/Instructions.scala      |  27 +-
 src/main/scala/micore/Core.scala              | 365 ++++---
 src/main/scala/micore/Memory.scala            |  38 +-
 src/main/scala/micore/Top.scala               |  11 +-
 src/test/scala/micore/MicoreSpec.scala        |   3 +-
 target/scala-2.13/-name-_2.13-0.1.0.jar       | Bin 66919 -> 60652 bytes
 target/scala-2.13/zinc/inc_compile_2.13.zip   | Bin 14709 -> 15351 bytes
 .../_global/_global/compileOutputs/previous   |   2 +-
 .../compileIncremental/_global/streams/out    |  58 +-
 .../compile/incOptions/_global/streams/out    |  15 +
 .../compile/packageBin/_global/streams/inputs |   2 +-
 .../compile/packageBin/_global/streams/out    |   8 -
 .../TopOrigin.lo.fir                          | 938 ++++++++++--------
 16 files changed, 1317 insertions(+), 921 deletions(-)

diff --git a/TopOrigin.sv b/TopOrigin.sv
index 881df86..8600283 100755
--- a/TopOrigin.sv
+++ b/TopOrigin.sv
@@ -1,4 +1,15 @@
 // Generated by CIRCT firtool-1.62.0
+// Standard header to adapt well known macros for prints and assertions.
+
+// Users can define 'PRINTF_COND' to add an extra gate to prints.
+`ifndef PRINTF_COND_
+  `ifdef PRINTF_COND
+    `define PRINTF_COND_ (`PRINTF_COND)
+  `else  // PRINTF_COND
+    `define PRINTF_COND_ 1
+  `endif // PRINTF_COND
+`endif // not def PRINTF_COND_
+
 // VCS coverage exclude_file
 module regfile_32x32(
   input  [4:0]  R0_addr,
@@ -9,6 +20,10 @@ module regfile_32x32(
   input         R1_en,
                 R1_clk,
   output [31:0] R1_data,
+  input  [4:0]  R2_addr,
+  input         R2_en,
+                R2_clk,
+  output [31:0] R2_data,
   input  [4:0]  W0_addr,
   input         W0_en,
                 W0_clk,
@@ -16,24 +31,13 @@ module regfile_32x32(
 );
 
   reg [31:0] Memory[0:31];
-  reg        _R0_en_d0;
-  reg [4:0]  _R0_addr_d0;
-  always @(posedge R0_clk) begin
-    _R0_en_d0 <= R0_en;
-    _R0_addr_d0 <= R0_addr;
-  end // always @(posedge)
-  reg        _R1_en_d0;
-  reg [4:0]  _R1_addr_d0;
-  always @(posedge R1_clk) begin
-    _R1_en_d0 <= R1_en;
-    _R1_addr_d0 <= R1_addr;
-  end // always @(posedge)
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr] <= W0_data;
   end // always @(posedge)
-  assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-  assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
+  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+  assign R2_data = R2_en ? Memory[R2_addr] : 32'bx;
 endmodule
 
 module Core(
@@ -45,277 +49,279 @@ module Core(
   input  [31:0] io_dmem_rdata,
   output        io_dmem_wen,
   output [31:0] io_dmem_wdata,
-  output        io_exit
+  output        io_exit,
+  output [31:0] io_gp
 );
 
-  wire [31:0] _regfile_ext_R0_data;
-  wire [31:0] _regfile_ext_R1_data;
-  reg  [31:0] id_reg_pc;
-  reg  [31:0] id_reg_inst;
-  reg  [31:0] exe_reg_pc;
-  reg  [4:0]  exe_reg_wb_addr;
-  reg  [31:0] exe_reg_op1_data;
-  reg  [31:0] exe_reg_op2_data;
-  reg  [31:0] exe_reg_rs2_data;
-  reg  [4:0]  exe_reg_exe_fun;
-  reg  [1:0]  exe_reg_mem_wen;
-  reg  [1:0]  exe_reg_rf_wen;
-  reg  [2:0]  exe_reg_wb_sel;
-  reg  [31:0] exe_reg_imm_b_sext;
-  reg  [31:0] mem_reg_pc;
-  reg  [4:0]  mem_reg_wb_addr;
-  reg  [31:0] mem_reg_alu_out;
-  reg  [31:0] mem_reg_rs2_data;
-  reg  [1:0]  mem_reg_rf_wen;
-  reg  [2:0]  mem_reg_wb_sel;
-  reg  [1:0]  mem_reg_mem_wen;
-  reg  [4:0]  wb_reg_wb_addr;
-  reg  [1:0]  wb_reg_rf_wen;
-  reg  [31:0] wb_reg_wb_data;
-  reg  [31:0] if_reg_pc;
-  wire        _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
-  wire        exe_br_flg =
-    exe_reg_exe_fun == 5'hC
-      ? exe_reg_op1_data != exe_reg_op2_data
-      : exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
-  wire        exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+  wire [31:0]      mem_wb_data;
+  wire             exe_jmp_flg;
+  wire             exe_br_flg;
+  wire [31:0]      _regfile_ext_R1_data;
+  wire [31:0]      _regfile_ext_R2_data;
+  reg  [31:0]      id_reg_pc;
+  reg  [31:0]      id_reg_inst;
+  reg  [31:0]      exe_reg_pc;
+  reg  [4:0]       exe_reg_wb_addr;
+  reg  [31:0]      exe_reg_op1_data;
+  reg  [31:0]      exe_reg_op2_data;
+  reg  [31:0]      exe_reg_rs2_data;
+  reg  [4:0]       exe_reg_exe_fun;
+  reg  [1:0]       exe_reg_mem_wen;
+  reg  [1:0]       exe_reg_rf_wen;
+  reg  [2:0]       exe_reg_wb_sel;
+  reg  [31:0]      exe_reg_imm_b_sext;
+  reg  [31:0]      mem_reg_pc;
+  reg  [4:0]       mem_reg_wb_addr;
+  reg  [31:0]      mem_reg_rs2_data;
+  reg  [1:0]       mem_reg_mem_wen;
+  reg  [1:0]       mem_reg_rf_wen;
+  reg  [2:0]       mem_reg_wb_sel;
+  reg  [31:0]      mem_reg_alu_out;
+  reg  [4:0]       wb_reg_wb_addr;
+  reg  [1:0]       wb_reg_rf_wen;
+  reg  [31:0]      wb_reg_wb_data;
+  reg  [31:0]      if_reg_pc;
+  wire             _id_inst_T = exe_br_flg | exe_jmp_flg;
+  wire             _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
+  wire             stall_flg =
+    _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
+    & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
+    & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+  wire [31:0]      id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
+  wire             _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
+  wire             _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
+  wire [31:0]      id_rs1_data =
+    id_inst[25:21] == 5'h0
+      ? 32'h0
+      : id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
+          ? mem_wb_data
+          : id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
+              ? wb_reg_wb_data
+              : _regfile_ext_R2_data;
+  wire [31:0]      id_rs2_data =
+    id_inst[20:16] == 5'h0
+      ? 32'h0
+      : id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
+          ? mem_wb_data
+          : id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
+              ? wb_reg_wb_data
+              : _regfile_ext_R1_data;
+  wire [16:0]      _GEN = {id_inst[31:26], id_inst[10:0]};
+  wire             _csignals_T_5 = _GEN == 17'h20;
+  wire [19:0]      _GEN_0 = {id_inst[31:28], id_inst[15:0]};
+  wire             _csignals_T_7 = _GEN_0 == 20'h80000;
+  wire             _csignals_T_9 = _GEN == 17'h22;
+  wire             _csignals_T_11 = _GEN == 17'h24;
+  wire             _csignals_T_13 = _GEN == 17'h25;
+  wire             _csignals_T_15 = _GEN == 17'h26;
+  wire             _csignals_T_17 = _GEN_0 == 20'hC0000;
+  wire             _csignals_T_19 = _GEN_0 == 20'hD0000;
+  wire             _csignals_T_21 = _GEN == 17'h2A;
+  wire             _csignals_T_23 = _GEN_0 == 20'h40000;
+  wire             _csignals_T_25 = _GEN_0 == 20'h50000;
+  wire             _csignals_T_27 = id_inst == 32'hC000000;
+  wire             _csignals_T_29 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
+  wire             _GEN_1 = _csignals_T_23 | _csignals_T_25;
+  wire             _GEN_2 = _csignals_T_21 | _GEN_1;
+  wire [2:0]       _csignals_T_70 =
+    _csignals_T_5
+      ? 3'h1
+      : _csignals_T_7
+          ? 3'h2
+          : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+              ? 3'h1
+              : _csignals_T_17 | _csignals_T_19
+                  ? 3'h2
+                  : _GEN_2 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1};
+  wire [3:0][31:0] _GEN_3 =
+    {{{27'h0, id_inst[15:11]}}, {32'h0}, {id_reg_pc}, {id_rs1_data}};
+  wire [31:0]      id_op1_data =
+    _GEN_3[_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+           | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_2
+             ? 2'h0
+             : _csignals_T_27 ? 2'h1 : {_csignals_T_29, 1'h0}];
+  wire [33:0]      id_op2_data =
+    _csignals_T_70 == 3'h1
+      ? {2'h0, id_rs2_data}
+      : _csignals_T_70 == 3'h2
+          ? {2'h0, {16{id_inst[15]}}, id_inst[15:0]}
+          : _csignals_T_70 == 3'h3
+              ? {2'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]}
+              : _csignals_T_70 == 3'h4
+                  ? {{6{id_inst[23]}}, id_inst[25:0], 2'h0}
+                  : {2'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0};
+  wire [31:0]      _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data;
+  wire [62:0]      _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+  wire [31:0]      _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
+  wire [31:0]      _exe_alu_out_T_46 =
+    exe_reg_exe_fun == 5'h1
+      ? _exe_alu_out_T_30
+      : exe_reg_exe_fun == 5'h2
+          ? exe_reg_op1_data - exe_reg_op2_data
+          : exe_reg_exe_fun == 5'h3
+              ? exe_reg_op1_data & exe_reg_op2_data
+              : exe_reg_exe_fun == 5'h4
+                  ? exe_reg_op1_data | exe_reg_op2_data
+                  : exe_reg_exe_fun == 5'h5
+                      ? exe_reg_op1_data ^ exe_reg_op2_data
+                      : exe_reg_exe_fun == 5'h6
+                          ? _exe_alu_out_T_14[31:0]
+                          : exe_reg_exe_fun == 5'h7
+                              ? exe_reg_op1_data >> _GEN_4
+                              : exe_reg_exe_fun == 5'h8
+                                  ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
+                                  : exe_reg_exe_fun == 5'h9
+                                      ? {31'h0,
+                                         $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
+                                      : exe_reg_exe_fun == 5'hA
+                                          ? {31'h0, exe_reg_op1_data < exe_reg_op2_data}
+                                          : exe_reg_exe_fun == 5'h11
+                                              ? _exe_alu_out_T_30 & 32'hFFFFFFFE
+                                              : exe_reg_exe_fun == 5'h12
+                                                  ? exe_reg_op1_data
+                                                  : 32'h0;
+  wire             _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data;
+  assign exe_br_flg =
+    exe_reg_exe_fun == 5'hB
+      ? _exe_br_flg_T_3
+      : exe_reg_exe_fun == 5'hC & ~_exe_br_flg_T_3;
+  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+  assign mem_wb_data =
+    mem_reg_wb_sel == 3'h2
+      ? io_dmem_rdata
+      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
+  `ifndef SYNTHESIS
+    always @(posedge clock) begin
+      if ((`PRINTF_COND_) & ~reset) begin
+        $fwrite(32'h80000002, "---------------------\n");
+        $fwrite(32'h80000002, "if_reg_pc: 0x%x\n", if_reg_pc);
+        $fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc);
+        $fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst);
+        $fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst);
+        $fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data);
+        $fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data);
+        $fwrite(32'h80000002, "exe_reg_pc: 0x%x\n", exe_reg_pc);
+        $fwrite(32'h80000002, "exe_reg_op1_data: 0x%x\n", id_op1_data);
+        $fwrite(32'h80000002, "exe_reg_op2_data: 0x%x\n", id_op2_data);
+        $fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46);
+        $fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc);
+        $fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data);
+        $fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data);
+        $fwrite(32'h80000002, "---------------------\n");
+      end
+    end // always @(posedge)
+  `endif // not def SYNTHESIS
   always @(posedge clock) begin
-    automatic logic        _id_inst_T = exe_br_flg | exe_jmp_flg;
-    automatic logic        _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
-    automatic logic        stall_flg;
-    automatic logic [31:0] id_inst;
-    automatic logic        _id_rs2_data_T_2;
-    automatic logic        _id_rs2_data_T;
-    automatic logic [31:0] _id_rs2_data_T_8;
-    automatic logic [16:0] _GEN;
-    automatic logic        _csignals_T_5;
-    automatic logic [19:0] _GEN_0;
-    automatic logic        _csignals_T_7;
-    automatic logic        _csignals_T_9;
-    automatic logic        _csignals_T_11;
-    automatic logic        _csignals_T_13;
-    automatic logic        _csignals_T_15;
-    automatic logic        _csignals_T_17;
-    automatic logic        _csignals_T_19;
-    automatic logic [16:0] _GEN_1;
-    automatic logic        _csignals_T_21;
-    automatic logic        _csignals_T_23;
-    automatic logic        _csignals_T_25;
-    automatic logic        _csignals_T_27;
-    automatic logic        _csignals_T_29;
-    automatic logic        _csignals_T_31;
-    automatic logic        _csignals_T_33;
-    automatic logic        _csignals_T_35;
-    automatic logic        _csignals_T_37;
-    automatic logic        _csignals_T_39;
-    automatic logic        _GEN_2;
-    automatic logic        _GEN_3;
-    automatic logic [1:0]  csignals_1;
-    automatic logic [2:0]  _csignals_T_95;
-    automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
-    automatic logic [62:0] _exe_alu_out_T_8 =
-      {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
-    automatic logic [31:0] exe_alu_out;
-    stall_flg =
-      _id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
-      & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
-      & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
-    id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
-    _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
-    _id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
-    _id_rs2_data_T_8 =
-      id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
-        ? mem_reg_alu_out
-        : id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
-            ? wb_reg_wb_data
-            : _regfile_ext_R0_data;
-    _GEN = {id_inst[31:26], id_inst[10:0]};
-    _csignals_T_5 = _GEN == 17'h20;
-    _GEN_0 = {id_inst[31:28], id_inst[15:0]};
-    _csignals_T_7 = _GEN_0 == 20'h80000;
-    _csignals_T_9 = _GEN == 17'h22;
-    _csignals_T_11 = _GEN == 17'h24;
-    _csignals_T_13 = _GEN == 17'h25;
-    _csignals_T_15 = _GEN == 17'h26;
-    _csignals_T_17 = _GEN_0 == 20'hC0000;
-    _csignals_T_19 = _GEN_0 == 20'hD0000;
-    _GEN_1 = {id_inst[30:20], id_inst[5:0]};
-    _csignals_T_21 = _GEN_1 == 17'h0;
-    _csignals_T_23 = _GEN_1 == 17'h2;
-    _csignals_T_25 = _GEN_1 == 17'h3;
-    _csignals_T_27 = _GEN == 17'h2A;
-    _csignals_T_29 = _GEN_0 == 20'h40000;
-    _csignals_T_31 = _GEN_0 == 20'h50000;
-    _csignals_T_33 = id_inst == 32'hC000000;
-    _csignals_T_35 = _GEN_0 == 20'h8;
-    _csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
-    _csignals_T_39 = id_inst == 32'h0;
-    _GEN_2 = _csignals_T_29 | _csignals_T_31;
-    _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
-    csignals_1 =
-      _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-      | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
-        ? 2'h0
-        : _csignals_T_33
-            ? 2'h1
-            : _csignals_T_35 ? 2'h0 : {_csignals_T_37 | _csignals_T_39, 1'h0};
-    _csignals_T_95 =
-      _csignals_T_5
-        ? 3'h1
-        : _csignals_T_7
-            ? 3'h2
-            : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
-                ? 3'h1
-                : _csignals_T_17 | _csignals_T_19
-                    ? 3'h2
-                    : _GEN_3
-                        ? 3'h1
-                        : _csignals_T_33
-                            ? 3'h4
-                            : _csignals_T_35
-                                ? 3'h0
-                                : _csignals_T_37 ? 3'h5 : {2'h0, ~_csignals_T_39};
-    exe_alu_out =
-      exe_reg_exe_fun == 5'hE
-        ? exe_reg_op1_data
-        : exe_reg_exe_fun == 5'h9
-            ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
-            : exe_reg_exe_fun == 5'h8
-                ? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
-                : exe_reg_exe_fun == 5'h7
-                    ? exe_reg_op1_data >> _GEN_4
-                    : exe_reg_exe_fun == 5'h6
-                        ? _exe_alu_out_T_8[31:0]
-                        : exe_reg_exe_fun == 5'h5
-                            ? exe_reg_op1_data ^ exe_reg_op2_data
-                            : exe_reg_exe_fun == 5'h4
-                                ? exe_reg_op1_data | exe_reg_op2_data
-                                : exe_reg_exe_fun == 5'h3
-                                    ? exe_reg_op1_data & exe_reg_op2_data
-                                    : exe_reg_exe_fun == 5'h2
-                                        ? exe_reg_op1_data - exe_reg_op2_data
-                                        : exe_reg_exe_fun == 5'h1
-                                            ? exe_reg_op1_data + exe_reg_op2_data
-                                            : 32'h0;
-    if (~stall_flg)
-      id_reg_pc <= if_reg_pc;
-    if (_id_inst_T)
+    if (reset) begin
+      id_reg_pc <= 32'h0;
       id_reg_inst <= 32'h0;
-    else if (~stall_flg)
-      id_reg_inst <= io_imem_inst;
-    exe_reg_pc <= id_reg_pc;
-    exe_reg_wb_addr <= id_reg_inst[15:11];
-    if (csignals_1 == 2'h0)
-      exe_reg_op1_data <=
-        id_reg_inst[25:21] == 5'h0
-          ? 32'h0
-          : id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
-              ? mem_reg_alu_out
-              : id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
-                  ? wb_reg_wb_data
-                  : _regfile_ext_R1_data;
-    else if (csignals_1 == 2'h1)
-      exe_reg_op1_data <= id_reg_pc;
-    else
+      exe_reg_pc <= 32'h0;
+      exe_reg_wb_addr <= 5'h0;
       exe_reg_op1_data <= 32'h0;
-    if (_csignals_T_95 == 3'h5)
-      exe_reg_op2_data <= {id_inst[15:0], 16'h0};
-    else if (_csignals_T_95 == 3'h4)
-      exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
-    else if (_csignals_T_95 == 3'h3 | _csignals_T_95 == 3'h2)
-      exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
-    else if (_csignals_T_95 != 3'h1 | _id_rs2_data_T)
       exe_reg_op2_data <= 32'h0;
-    else
-      exe_reg_op2_data <= _id_rs2_data_T_8;
-    exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
-    if (_csignals_T_5 | _csignals_T_7)
-      exe_reg_exe_fun <= 5'h1;
-    else if (_csignals_T_9)
-      exe_reg_exe_fun <= 5'h2;
-    else if (_csignals_T_11)
-      exe_reg_exe_fun <= 5'h3;
-    else if (_csignals_T_13)
-      exe_reg_exe_fun <= 5'h4;
-    else if (_csignals_T_15)
-      exe_reg_exe_fun <= 5'h5;
-    else if (_csignals_T_17)
-      exe_reg_exe_fun <= 5'h3;
-    else if (_csignals_T_19)
-      exe_reg_exe_fun <= 5'h4;
-    else if (_csignals_T_21)
-      exe_reg_exe_fun <= 5'h6;
-    else if (_csignals_T_23)
-      exe_reg_exe_fun <= 5'h7;
-    else if (_csignals_T_25)
-      exe_reg_exe_fun <= 5'h8;
-    else if (_csignals_T_27)
-      exe_reg_exe_fun <= 5'h9;
-    else if (_csignals_T_29)
-      exe_reg_exe_fun <= 5'hB;
-    else if (_csignals_T_31)
-      exe_reg_exe_fun <= 5'hC;
-    else if (_csignals_T_33)
-      exe_reg_exe_fun <= 5'h1;
-    else if (_csignals_T_35)
-      exe_reg_exe_fun <= 5'hE;
-    else
-      exe_reg_exe_fun <= {4'h0, _csignals_T_37};
-    exe_reg_mem_wen <= 2'h0;
-    if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
-        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
-        | _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
-      exe_reg_rf_wen <= 2'h1;
-      exe_reg_wb_sel <= 3'h1;
-    end
-    else if (_GEN_2) begin
-      exe_reg_rf_wen <= 2'h0;
-      exe_reg_wb_sel <= 3'h0;
-    end
-    else if (_csignals_T_33) begin
-      exe_reg_rf_wen <= 2'h1;
-      exe_reg_wb_sel <= 3'h3;
-    end
-    else if (_csignals_T_35) begin
+      exe_reg_rs2_data <= 32'h0;
+      exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= 2'h0;
       exe_reg_rf_wen <= 2'h0;
       exe_reg_wb_sel <= 3'h0;
+      exe_reg_imm_b_sext <= 32'h0;
+      mem_reg_pc <= 32'h0;
+      mem_reg_wb_addr <= 5'h0;
+      mem_reg_rs2_data <= 32'h0;
+      mem_reg_mem_wen <= 2'h0;
+      mem_reg_rf_wen <= 2'h0;
+      mem_reg_wb_sel <= 3'h0;
+      mem_reg_alu_out <= 32'h0;
+      wb_reg_wb_addr <= 5'h0;
+      wb_reg_rf_wen <= 2'h0;
+      wb_reg_wb_data <= 32'h0;
+      if_reg_pc <= 32'h400000;
     end
     else begin
-      exe_reg_rf_wen <= {1'h0, _csignals_T_37};
-      exe_reg_wb_sel <= {2'h0, _csignals_T_37};
+      automatic logic _GEN_5;
+      _GEN_5 = _csignals_T_27 | _csignals_T_29;
+      if (~stall_flg)
+        id_reg_pc <= if_reg_pc;
+      if (_id_inst_T)
+        id_reg_inst <= 32'h0;
+      else if (~stall_flg)
+        id_reg_inst <= io_imem_inst;
+      exe_reg_pc <= id_reg_pc;
+      exe_reg_wb_addr <= id_inst[15:11];
+      exe_reg_op1_data <= id_op1_data;
+      exe_reg_op2_data <= id_op2_data[31:0];
+      exe_reg_rs2_data <= id_rs2_data;
+      if (_csignals_T_5 | _csignals_T_7)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_9)
+        exe_reg_exe_fun <= 5'h2;
+      else if (_csignals_T_11)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_13)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_15)
+        exe_reg_exe_fun <= 5'h5;
+      else if (_csignals_T_17)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_19)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_21)
+        exe_reg_exe_fun <= 5'h9;
+      else if (_csignals_T_23)
+        exe_reg_exe_fun <= 5'hB;
+      else if (_csignals_T_25)
+        exe_reg_exe_fun <= 5'hC;
+      else
+        exe_reg_exe_fun <= {4'h0, _GEN_5};
+      exe_reg_mem_wen <= 2'h0;
+      if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+          | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h1;
+      end
+      else if (_GEN_1) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else begin
+        exe_reg_rf_wen <= {1'h0, _GEN_5};
+        if (_csignals_T_27)
+          exe_reg_wb_sel <= 3'h3;
+        else
+          exe_reg_wb_sel <= {2'h0, _csignals_T_29};
+      end
+      exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0};
+      mem_reg_pc <= exe_reg_pc;
+      mem_reg_wb_addr <= exe_reg_wb_addr;
+      mem_reg_rs2_data <= exe_reg_rs2_data;
+      mem_reg_mem_wen <= exe_reg_mem_wen;
+      mem_reg_rf_wen <= exe_reg_rf_wen;
+      mem_reg_wb_sel <= exe_reg_wb_sel;
+      mem_reg_alu_out <= _exe_alu_out_T_46;
+      wb_reg_wb_addr <= mem_reg_wb_addr;
+      wb_reg_rf_wen <= mem_reg_rf_wen;
+      wb_reg_wb_data <= mem_wb_data;
+      if (exe_br_flg)
+        if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
+      else if (exe_jmp_flg)
+        if_reg_pc <= _exe_alu_out_T_46;
+      else if (~stall_flg)
+        if_reg_pc <= if_reg_pc + 32'h4;
     end
-    exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
-    mem_reg_pc <= exe_reg_pc;
-    mem_reg_wb_addr <= exe_reg_wb_addr;
-    mem_reg_alu_out <= exe_alu_out;
-    mem_reg_rs2_data <= exe_reg_rs2_data;
-    mem_reg_rf_wen <= exe_reg_rf_wen;
-    mem_reg_wb_sel <= exe_reg_wb_sel;
-    mem_reg_mem_wen <= exe_reg_mem_wen;
-    wb_reg_wb_addr <= mem_reg_wb_addr;
-    wb_reg_rf_wen <= mem_reg_rf_wen;
-    wb_reg_wb_data <=
-      mem_reg_wb_sel == 3'h3
-        ? mem_reg_pc + 32'h4
-        : mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
-    if (reset)
-      if_reg_pc <= 32'h0;
-    else if (exe_br_flg)
-      if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
-    else if (exe_jmp_flg)
-      if_reg_pc <= exe_alu_out;
-    else if (~stall_flg)
-      if_reg_pc <= if_reg_pc + 32'h4;
   end // always @(posedge)
   regfile_32x32 regfile_ext (
-    .R0_addr (id_reg_inst[20:16]),
+    .R0_addr (5'h3),
     .R0_en   (1'h1),
     .R0_clk  (clock),
-    .R0_data (_regfile_ext_R0_data),
-    .R1_addr (id_reg_inst[25:21]),
+    .R0_data (io_gp),
+    .R1_addr (id_inst[20:16]),
     .R1_en   (1'h1),
     .R1_clk  (clock),
     .R1_data (_regfile_ext_R1_data),
+    .R2_addr (id_inst[25:21]),
+    .R2_en   (1'h1),
+    .R2_clk  (clock),
+    .R2_data (_regfile_ext_R2_data),
     .W0_addr (wb_reg_wb_addr),
     .W0_en   (_id_rs2_data_T_5),
     .W0_clk  (clock),
@@ -325,48 +331,84 @@ module Core(
   assign io_dmem_addr = mem_reg_alu_out;
   assign io_dmem_wen = mem_reg_mem_wen[0];
   assign io_dmem_wdata = mem_reg_rs2_data;
-  assign io_exit = id_reg_inst == 32'hC0000000;
+  assign io_exit = id_reg_inst == 32'h114514;
 endmodule
 
 // VCS coverage exclude_file
-module mem_512x32(
-  input  [8:0]  R0_addr,
+module mem_4096x8(
+  input  [11:0] R0_addr,
   input         R0_en,
                 R0_clk,
-  output [31:0] R0_data,
-  input  [8:0]  R1_addr,
+  output [7:0]  R0_data,
+  input  [11:0] R1_addr,
   input         R1_en,
                 R1_clk,
-  output [31:0] R1_data,
-  input  [8:0]  W0_addr,
+  output [7:0]  R1_data,
+  input  [11:0] R2_addr,
+  input         R2_en,
+                R2_clk,
+  output [7:0]  R2_data,
+  input  [11:0] R3_addr,
+  input         R3_en,
+                R3_clk,
+  output [7:0]  R3_data,
+  input  [11:0] R4_addr,
+  input         R4_en,
+                R4_clk,
+  output [7:0]  R4_data,
+  input  [11:0] R5_addr,
+  input         R5_en,
+                R5_clk,
+  output [7:0]  R5_data,
+  input  [11:0] R6_addr,
+  input         R6_en,
+                R6_clk,
+  output [7:0]  R6_data,
+  input  [11:0] R7_addr,
+  input         R7_en,
+                R7_clk,
+  output [7:0]  R7_data,
+  input  [11:0] W0_addr,
   input         W0_en,
                 W0_clk,
-  input  [31:0] W0_data
+  input  [7:0]  W0_data,
+  input  [11:0] W1_addr,
+  input         W1_en,
+                W1_clk,
+  input  [7:0]  W1_data,
+  input  [11:0] W2_addr,
+  input         W2_en,
+                W2_clk,
+  input  [7:0]  W2_data,
+  input  [11:0] W3_addr,
+  input         W3_en,
+                W3_clk,
+  input  [7:0]  W3_data
 );
 
-  reg [31:0] Memory[0:511];
-  reg        _R0_en_d0;
-  reg [8:0]  _R0_addr_d0;
-  always @(posedge R0_clk) begin
-    _R0_en_d0 <= R0_en;
-    _R0_addr_d0 <= R0_addr;
-  end // always @(posedge)
-  reg        _R1_en_d0;
-  reg [8:0]  _R1_addr_d0;
-  always @(posedge R1_clk) begin
-    _R1_en_d0 <= R1_en;
-    _R1_addr_d0 <= R1_addr;
-  end // always @(posedge)
+  reg [7:0] Memory[0:4095];
   always @(posedge W0_clk) begin
     if (W0_en & 1'h1)
       Memory[W0_addr] <= W0_data;
+    if (W1_en & 1'h1)
+      Memory[W1_addr] <= W1_data;
+    if (W2_en & 1'h1)
+      Memory[W2_addr] <= W2_data;
+    if (W3_en & 1'h1)
+      Memory[W3_addr] <= W3_data;
   end // always @(posedge)
   `ifdef ENABLE_INITIAL_MEM_
     initial
       $readmemh("src/hex/mem.hex", Memory);
   `endif // ENABLE_INITIAL_MEM_
-  assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
-  assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
+  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
+  assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
+  assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
+  assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
+  assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
+  assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
+  assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
 endmodule
 
 module Memory(
@@ -379,26 +421,78 @@ module Memory(
   input  [31:0] io_dmem_wdata
 );
 
-  mem_512x32 mem_ext (
-    .R0_addr (io_imem_addr[10:2]),
+  wire [7:0]  _mem_ext_R0_data;
+  wire [7:0]  _mem_ext_R1_data;
+  wire [7:0]  _mem_ext_R2_data;
+  wire [7:0]  _mem_ext_R3_data;
+  wire [7:0]  _mem_ext_R4_data;
+  wire [7:0]  _mem_ext_R5_data;
+  wire [7:0]  _mem_ext_R6_data;
+  wire [7:0]  _mem_ext_R7_data;
+  wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
+  wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
+  wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
+  mem_4096x8 mem_ext (
+    .R0_addr (io_imem_addr[11:0]),
     .R0_en   (1'h1),
     .R0_clk  (clock),
-    .R0_data (io_imem_inst),
-    .R1_addr (io_dmem_addr[10:2]),
+    .R0_data (_mem_ext_R0_data),
+    .R1_addr (io_imem_addr[11:0] + 12'h1),
     .R1_en   (1'h1),
     .R1_clk  (clock),
-    .R1_data (io_dmem_rdata),
-    .W0_addr (io_dmem_addr[10:2]),
+    .R1_data (_mem_ext_R1_data),
+    .R2_addr (io_imem_addr[11:0] + 12'h2),
+    .R2_en   (1'h1),
+    .R2_clk  (clock),
+    .R2_data (_mem_ext_R2_data),
+    .R3_addr (io_imem_addr[11:0] + 12'h3),
+    .R3_en   (1'h1),
+    .R3_clk  (clock),
+    .R3_data (_mem_ext_R3_data),
+    .R4_addr (io_dmem_addr[11:0]),
+    .R4_en   (1'h1),
+    .R4_clk  (clock),
+    .R4_data (_mem_ext_R4_data),
+    .R5_addr (_io_dmem_rdata_T_6),
+    .R5_en   (1'h1),
+    .R5_clk  (clock),
+    .R5_data (_mem_ext_R5_data),
+    .R6_addr (_io_dmem_rdata_T_3),
+    .R6_en   (1'h1),
+    .R6_clk  (clock),
+    .R6_data (_mem_ext_R6_data),
+    .R7_addr (_io_dmem_rdata_T),
+    .R7_en   (1'h1),
+    .R7_clk  (clock),
+    .R7_data (_mem_ext_R7_data),
+    .W0_addr (_io_dmem_rdata_T),
     .W0_en   (io_dmem_wen),
     .W0_clk  (clock),
-    .W0_data (io_dmem_wdata)
+    .W0_data (io_dmem_wdata[31:24]),
+    .W1_addr (_io_dmem_rdata_T_3),
+    .W1_en   (io_dmem_wen),
+    .W1_clk  (clock),
+    .W1_data (io_dmem_wdata[23:16]),
+    .W2_addr (_io_dmem_rdata_T_6),
+    .W2_en   (io_dmem_wen),
+    .W2_clk  (clock),
+    .W2_data (io_dmem_wdata[15:8]),
+    .W3_addr (io_dmem_addr[11:0]),
+    .W3_en   (io_dmem_wen),
+    .W3_clk  (clock),
+    .W3_data (io_dmem_wdata[7:0])
   );
+  assign io_imem_inst =
+    {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
+  assign io_dmem_rdata =
+    {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
 endmodule
 
 module TopOrigin(
-  input  clock,
-         reset,
-  output io_exit
+  input         clock,
+                reset,
+  output        io_exit,
+  output [31:0] io_gp
 );
 
   wire [31:0] _memory_io_imem_inst;
@@ -416,7 +510,8 @@ module TopOrigin(
     .io_dmem_rdata (_memory_io_dmem_rdata),
     .io_dmem_wen   (_core_io_dmem_wen),
     .io_dmem_wdata (_core_io_dmem_wdata),
-    .io_exit       (io_exit)
+    .io_exit       (io_exit),
+    .io_gp         (io_gp)
   );
   Memory memory (
     .clock         (clock),
diff --git a/src/hex/mem.hex b/src/hex/mem.hex
index 1898c61..56ca829 100755
--- a/src/hex/mem.hex
+++ b/src/hex/mem.hex
@@ -1,8 +1,36 @@
-00 01 08 20
-00 00 10 20
-65 00 12 20
-20 80 08 02
-01 00 08 21
-2A 50 12 01
-FC FF 40 15
-00 00 00 00
+01
+00
+08
+20
+00
+00
+10
+20
+65
+00
+12
+20
+20
+80
+08
+02
+01
+00
+08
+21
+2a
+50
+12
+01
+fc
+ff
+40
+15
+00
+00
+00
+00
+14
+45
+11
+00
\ No newline at end of file
diff --git a/src/main/scala/common/Consts.scala b/src/main/scala/common/Consts.scala
index 79ada35..2ab76c0 100755
--- a/src/main/scala/common/Consts.scala
+++ b/src/main/scala/common/Consts.scala
@@ -6,12 +6,12 @@ import chisel3.util._
 object Consts {
   // 数据宽度和地址
   val WORD_LEN = 32 // 指令和数据的宽度为32位
-  val START_ADDR = 0.U(WORD_LEN.W) // 起始地址，设为0
+  val START_ADDR = 0x00400000.U(WORD_LEN.W) // MIPS程序的起始地址通常为0x00400000
   val BUBBLE = 0x00000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP]
-  val UNIMP = "x_c0000000".U(WORD_LEN.W)
+  val UNIMP = 0x00114514.U(WORD_LEN.W) // 未实现指令 [NOP]
 
   // 寄存器地址长度
-  val ADDR_LEN = 5 // rs1、rs2和写回寄存器的地址宽度为5位
+  val ADDR_LEN = 5 // rs、rt和rd的地址宽度为5位
 
   // 执行功能定义
   val EXE_FUN_LEN = 5 // 执行功能的编码长度为5位
@@ -28,18 +28,22 @@ object Consts {
   val ALU_SLTU = 10.U(EXE_FUN_LEN.W) // 无符号比较小于操作
   val BR_BEQ = 11.U(EXE_FUN_LEN.W) // 分支相等
   val BR_BNE = 12.U(EXE_FUN_LEN.W) // 分支不等
-  val ALU_JAL = 13.U(EXE_FUN_LEN.W) // JAL跳转
-  val ALU_COPY1 = 14.U(EXE_FUN_LEN.W) // 复制操作
+  val BR_BLT = 13.U(EXE_FUN_LEN.W) // 有符号小于分支
+  val BR_BGE = 14.U(EXE_FUN_LEN.W) // 有符号大于等于分支
+  val BR_BLTU = 15.U(EXE_FUN_LEN.W) // 无符号小于分支
+  val BR_BGEU = 16.U(EXE_FUN_LEN.W) // 无符号大于等于分支
+  val ALU_JALR = 17.U(EXE_FUN_LEN.W) // JALR跳转（MIPS中没有JALR，但可以模拟）
+  val ALU_COPY1 = 18.U(EXE_FUN_LEN.W) // 复制操作
 
   // 操作数选择
   val OP1_LEN = 2 // 操作数1的选择宽度为2位
-  val OP1_RS1 = 0.U(OP1_LEN.W) // 选择rs1
-  val OP1_PC = 1.U(OP1_LEN.W) // 选择PC
-  val OP1_X = 2.U(OP1_LEN.W) // 未定义操作数1
+  val OP1_X = 0.U(OP1_LEN.W) // 未定义操作数1
+  val OP1_RS = 1.U(OP1_LEN.W) // 选择rs
+  val OP1_PC = 2.U(OP1_LEN.W) // 选择PC
 
   val OP2_LEN = 3 // 操作数2的选择宽度为3位
   val OP2_X = 0.U(OP2_LEN.W) // 未定义操作数2
-  val OP2_RS2 = 1.U(OP2_LEN.W) // 选择rs2
+  val OP2_RT = 1.U(OP2_LEN.W) // 选择rt
   val OP2_IMI = 2.U(OP2_LEN.W) // 立即数操作数2（immI）
   val OP2_IMS = 3.U(OP2_LEN.W) // 立即数操作数2（immS）
   val OP2_IMJ = 4.U(OP2_LEN.W) // 立即数操作数2（immJ）
@@ -62,12 +66,4 @@ object Consts {
   val WB_MEM = 2.U(WB_SEL_LEN.W) // 内存数据写回
   val WB_PC = 3.U(WB_SEL_LEN.W) // PC写回
 
-  // 内存宽度
-  val MW_LEN = 3 // 内存宽度控制信号宽度为3位
-  val MW_X = 0.U(MW_LEN.W) // 未定义
-  val MW_W = 1.U(MW_LEN.W) // 32位字访问
-  val MW_H = 2.U(MW_LEN.W) // 16位半字访问
-  val MW_B = 3.U(MW_LEN.W) // 8位字节访问
-  val MW_HU = 4.U(MW_LEN.W) // 16位无符号半字访问
-  val MW_BU = 5.U(MW_LEN.W) // 8位无符号字节访问
 }
diff --git a/src/main/scala/common/Instructions.scala b/src/main/scala/common/Instructions.scala
index b9e6521..2e1a83d 100755
--- a/src/main/scala/common/Instructions.scala
+++ b/src/main/scala/common/Instructions.scala
@@ -5,13 +5,13 @@ import chisel3.util._
 
 object Instructions {
   // * 加载 / 存储
-  val LW = BitPat("b100011????????????0000000000000000") // lw rt, offset(rs)
-  val SW = BitPat("b101011????????????0000000000000000") // sw rt, offset(rs)
+  val LW = BitPat("b100011????????????????????????????") // lw rt, offset(rs)
+  val SW = BitPat("b101011????????????????????????????") // sw rt, offset(rs)
 
   // * 算术运算
   val ADD = BitPat("b000000???????????????00000100000") // add rd, rs, rt
   val ADDI = BitPat(
-    "b001000????????????0000000000000000"
+    "b001000????????????????????????????"
   ) // addi rt, rs, immediate
   val SUB = BitPat("b000000???????????????00000100010") // sub rd, rs, rt
 
@@ -20,30 +20,31 @@ object Instructions {
   val OR = BitPat("b000000???????????????00000100101") // or rd, rs, rt
   val XOR = BitPat("b000000???????????????00000100110") // xor rd, rs, rt
   val ANDI = BitPat(
-    "b001100????????????0000000000000000"
+    "b001100????????????????????????????"
   ) // andi rt, rs, immediate
   val ORI = BitPat(
-    "b001101????????????0000000000000000"
+    "b001101????????????????????????????"
   ) // ori rt, rs, immediate
 
   // * 比较
   val SLT = BitPat("b000000???????????????00000101010") // slt rd, rs, rt
 
   // * 条件分支
-  val BEQ = BitPat("b000100????????????0000000000000000") // beq rs, rt, offset
-  val BNE = BitPat("b000101????????????0000000000000000") // bne rs, rt, offset
+  val BEQ = BitPat("b000100????????????????????????????") // beq rs, rt, offset
+  val BNE = BitPat("b000101????????????????????????????") // bne rs, rt, offset
 
   // * 移位
-  val SLL = BitPat("b00000000000??????????????000000") // sll rd, rt, shamt
-  val SRL = BitPat("b00000000000??????????????000010") // srl rd, rt, shamt
-  val SRA = BitPat("b00000000000??????????????000011") // sra rd, rt, shamt
+  val SLL = BitPat("b00000000000???????????????000000") // sll rd, rt, shamt
+  val SRL = BitPat("b00000000000???????????????000010") // srl rd, rt, shamt
+  val SRA = BitPat("b00000000000???????????????000011") // sra rd, rt, shamt
 
   // * 跳转
   val JR = BitPat("b000000????????????0000000000001000") // jr rs
-  val JAL = BitPat("b00001100000000000000000000000000") // jal target
+  val JAL = BitPat("b000011????????????????????????????") // jal target
 
   // * 立即数加载
-  val LUI = BitPat("b00111100000????????????0000000000") // lui rt, immediate
+  val LUI = BitPat("b00111100000???????????????????????") // lui rt, immediate
 
-  val NOP = BitPat("b000000000000000000000000000000000") // nop
+  // * NOP
+  val NOP = BitPat("b00000000000000000000000000000000") // nop (sll $0, $0, 0)
 }
diff --git a/src/main/scala/micore/Core.scala b/src/main/scala/micore/Core.scala
index f97a348..f424fff 100755
--- a/src/main/scala/micore/Core.scala
+++ b/src/main/scala/micore/Core.scala
@@ -7,48 +7,50 @@ import common.Instructions._
 
 class Core extends Module {
   val io = IO(new Bundle {
-    val imem = Flipped(new ImemPortIo)
-    val dmem = Flipped(new DmemPortIo)
+    val imem = Flipped(new ImemPortIo())
+    val dmem = Flipped(new DmemPortIo())
     val exit = Output(Bool())
+    val gp = Output(UInt(WORD_LEN.W))
   })
 
-  // Block RAM for data memory
-  val regfile = SyncReadMem(32, UInt(WORD_LEN.W))
+  val regfile = Mem(32, UInt(WORD_LEN.W))
 
   // ********* Pipeline Registers *********
-  val id_reg = Reg(new Bundle {
-    val pc = UInt(WORD_LEN.W)
-    val inst = UInt(WORD_LEN.W)
-  })
+  // IF/ID state
+  val id_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val id_reg_inst = RegInit(0.U(WORD_LEN.W))
 
-  val exe_reg = Reg(new Bundle {
-    val pc = UInt(WORD_LEN.W)
-    val wb_addr = UInt(ADDR_LEN.W)
-    val op1_data = UInt(WORD_LEN.W)
-    val op2_data = UInt(WORD_LEN.W)
-    val rs2_data = UInt(WORD_LEN.W)
-    val exe_fun = UInt(EXE_FUN_LEN.W)
-    val mem_wen = UInt(MEN_LEN.W)
-    val rf_wen = UInt(REN_LEN.W)
-    val wb_sel = UInt(WB_SEL_LEN.W)
-    val imm_b_sext = UInt(WORD_LEN.W)
-  })
+  // ID/EX state
+  val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
+  val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
+  val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
+  val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_z_uext = RegInit(0.U(WORD_LEN.W))
 
-  val mem_reg = Reg(new Bundle {
-    val pc = UInt(WORD_LEN.W)
-    val wb_addr = UInt(ADDR_LEN.W)
-    val alu_out = UInt(WORD_LEN.W)
-    val rs2_data = UInt(WORD_LEN.W)
-    val rf_wen = UInt(REN_LEN.W)
-    val wb_sel = UInt(WB_SEL_LEN.W)
-    val mem_wen = UInt(MEN_LEN.W)
-  })
+  // EX/MEM state
+  val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
+  val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
+  val mem_reg_imm_z_uext = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
 
-  val wb_reg = Reg(new Bundle {
-    val wb_addr = UInt(ADDR_LEN.W)
-    val rf_wen = UInt(REN_LEN.W)
-    val wb_data = UInt(WORD_LEN.W)
-  })
+  // MEM/WB state
+  val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
 
   // ********* Instruction Fetch (IF) Stage *********
   val if_reg_pc = RegInit(START_ADDR)
@@ -67,193 +69,232 @@ class Core extends Module {
     Seq(
       exe_br_flg -> exe_br_target,
       exe_jmp_flg -> exe_alu_out,
-      stall_flg -> if_reg_pc
+      stall_flg -> if_reg_pc // stall
     )
   )
   if_reg_pc := if_pc_next
 
   // ********* IF/ID Stage *********
-  id_reg.pc := Mux(stall_flg, id_reg.pc, if_reg_pc)
-  id_reg.inst := MuxCase(
+  id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc)
+  id_reg_inst := MuxCase(
     if_inst,
     Seq(
       (exe_br_flg || exe_jmp_flg) -> BUBBLE,
-      stall_flg -> id_reg.inst
+      stall_flg -> id_reg_inst
     )
   )
 
   // ********* Decode (ID) Stage *********
-  val id_rs1_addr = id_reg.inst(25, 21)
-  val id_rs2_addr = id_reg.inst(20, 16)
-  val id_wb_addr = id_reg.inst(15, 11)
+  val id_rs1_addr_b = id_reg_inst(25, 21) // MIPS rs字段
+  val id_rs2_addr_b = id_reg_inst(20, 16) // MIPS rt字段
 
-  // Data Hazard
+// 与EX数据冒险 -> stall
   val id_rs1_data_hazard =
-    (exe_reg.rf_wen === REN_S) && (id_rs1_addr =/= 0.U) && (id_rs1_addr === exe_reg.wb_addr)
+    (exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr)
   val id_rs2_data_hazard =
-    (exe_reg.rf_wen === REN_S) && (id_rs2_addr =/= 0.U) && (id_rs2_addr === exe_reg.wb_addr)
+    (exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr)
   stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
 
   val id_inst =
-    Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg.inst)
+    Mux((exe_br_flg || exe_jmp_flg || stall_flg), BUBBLE, id_reg_inst)
 
-  val id_rs1_data = Mux(
-    id_rs1_addr === 0.U,
-    0.U(WORD_LEN.W),
-    Mux(
-      (id_rs1_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
-      mem_reg.alu_out,
-      Mux(
-        (id_rs1_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
-        wb_reg.wb_data,
-        regfile(id_rs1_addr)
-      )
+  val id_rs1_addr = id_inst(25, 21) // MIPS rs字段
+  val id_rs2_addr = id_inst(20, 16) // MIPS rt字段
+  val id_wb_addr = id_inst(15, 11) // MIPS rt字段（写回地址）
+
+  val mem_wb_data = Wire(UInt(WORD_LEN.W))
+  val id_rs1_data = MuxCase(
+    regfile(id_rs1_addr),
+    Seq(
+      (id_rs1_addr === 0.U) -> 0.U(WORD_LEN.W),
+      ((id_rs1_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
+      ((id_rs1_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
     )
   )
-  val id_rs2_data = Mux(
-    id_rs2_addr === 0.U,
-    0.U(WORD_LEN.W),
-    Mux(
-      (id_rs2_addr === mem_reg.wb_addr) && (mem_reg.rf_wen === REN_S),
-      mem_reg.alu_out,
-      Mux(
-        (id_rs2_addr === wb_reg.wb_addr) && (wb_reg.rf_wen === REN_S),
-        wb_reg.wb_data,
-        regfile(id_rs2_addr)
-      )
+  val id_rs2_data = MuxCase(
+    regfile(id_rs2_addr),
+    Seq(
+      (id_rs2_addr === 0.U) -> 0.U(WORD_LEN.W),
+      ((id_rs2_addr === mem_reg_wb_addr) && (mem_reg_rf_wen === REN_S)) -> mem_wb_data, // 从MEM直通
+      ((id_rs2_addr === wb_reg_wb_addr) && (wb_reg_rf_wen === REN_S)) -> wb_reg_wb_data // 从WB直通
     )
   )
 
-  // 立即数扩展
-  val id_imm_i_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
-  val id_imm_b_sext = Cat(Fill(16, id_inst(15)), id_inst(15, 0))
+  val id_imm_i = id_inst(15, 0) // MIPS立即数字段
+  val id_imm_i_sext = Cat(Fill(16, id_imm_i(15)), id_imm_i)
+  val id_imm_s = Cat(id_inst(15, 11), id_inst(25, 21)) // 生成 10 位的立即数字段
+  val id_imm_s_sext = Cat(Fill(22, id_imm_s(9)), id_imm_s) // 符号扩展到 32 位
+  val id_imm_b = Cat(id_inst(15, 0), 0.U(2.W)) // MIPS分支指令的立即数字段
+  val id_imm_b_sext = Cat(Fill(14, id_imm_b(17)), id_imm_b)
+  val id_imm_j = Cat(id_inst(25, 0), 0.U(2.W)) // MIPS跳转指令的立即数字段
+  val id_imm_j_sext = Cat(Fill(6, id_imm_j(25)), id_imm_j, 0.U(2.W))
+  val id_imm_u = id_inst(15, 0) // MIPS lui指令的立即数字段
+  val id_imm_u_shifted = Cat(id_imm_u, Fill(16, 0.U))
+  val id_imm_z = id_inst(15, 11) // MIPS立即数字段
+  val id_imm_z_uext = Cat(Fill(27, 0.U), id_imm_z)
 
-  // 控制信号解码
   val csignals = ListLookup(
     id_inst,
-    List(ALU_X, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
+    List(ALU_X, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X),
     Array(
-      LW -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_MEM),
-      SW -> List(ALU_ADD, OP1_RS1, OP2_IMS, MEN_S, REN_X, WB_X),
-      ADD -> List(ALU_ADD, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      ADDI -> List(ALU_ADD, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-      SUB -> List(ALU_SUB, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      AND -> List(ALU_AND, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      OR -> List(ALU_OR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      XOR -> List(ALU_XOR, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      ANDI -> List(ALU_AND, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-      ORI -> List(ALU_OR, OP1_RS1, OP2_IMI, MEN_X, REN_S, WB_ALU),
-      SLL -> List(ALU_SLL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      SRL -> List(ALU_SRL, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      SRA -> List(ALU_SRA, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      SLT -> List(ALU_SLT, OP1_RS1, OP2_RS2, MEN_X, REN_S, WB_ALU),
-      BEQ -> List(BR_BEQ, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
-      BNE -> List(BR_BNE, OP1_RS1, OP2_RS2, MEN_X, REN_X, WB_X),
+      LW -> List(ALU_ADD, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_MEM),
+      SW -> List(ALU_ADD, OP1_RS, OP2_IMS, MEN_S, REN_X, WB_X),
+      ADD -> List(ALU_ADD, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      ADDI -> List(ALU_ADD, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      SUB -> List(ALU_SUB, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      AND -> List(ALU_AND, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      OR -> List(ALU_OR, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      XOR -> List(ALU_XOR, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      ANDI -> List(ALU_AND, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      ORI -> List(ALU_OR, OP1_RS, OP2_IMI, MEN_X, REN_S, WB_ALU),
+      SLT -> List(ALU_SLT, OP1_RS, OP2_RT, MEN_X, REN_S, WB_ALU),
+      BEQ -> List(BR_BEQ, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X),
+      BNE -> List(BR_BNE, OP1_RS, OP2_RT, MEN_X, REN_X, WB_X),
       JAL -> List(ALU_ADD, OP1_PC, OP2_IMJ, MEN_X, REN_S, WB_PC),
-      JR -> List(ALU_COPY1, OP1_RS1, OP2_X, MEN_X, REN_X, WB_X),
-      LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU),
-      NOP -> List(ALU_X, OP1_X, OP2_X, MEN_X, REN_X, WB_X)
+      LUI -> List(ALU_ADD, OP1_X, OP2_IMU, MEN_X, REN_S, WB_ALU)
     )
   )
 
   val id_exe_fun :: id_op1_sel :: id_op2_sel :: id_mem_wen :: id_rf_wen :: id_wb_sel :: Nil =
     csignals
 
-  val id_op1_data = Mux(
-    id_op1_sel === OP1_RS1,
-    id_rs1_data,
-    Mux(id_op1_sel === OP1_PC, id_reg.pc, 0.U(WORD_LEN.W))
-  )
-  val id_op2_data = MuxLookup(
-    id_op2_sel,
-    0.U(WORD_LEN.W)
-  )(
+  val id_op1_data = MuxCase(
+    0.U(WORD_LEN.W),
     Seq(
-      OP2_RS2 -> id_rs2_data,
-      OP2_IMI -> id_imm_i_sext,
-      OP2_IMS -> id_imm_i_sext,
-      OP2_IMJ -> Cat(Fill(4, id_inst(25)), id_inst(25, 0), 0.U(2.W)),
-      OP2_IMU -> Cat(id_inst(15, 0), Fill(16, 0.U))
+      (id_op1_sel === OP1_RS) -> id_rs1_data,
+      (id_op1_sel === OP1_PC) -> id_reg_pc
+      // (id_op1_sel === OP1_IMZ) -> id_imm_z_uext
+    )
+  )
+
+  val id_op2_data = MuxCase(
+    0.U(WORD_LEN.W),
+    Seq(
+      (id_op2_sel === OP2_RT) -> id_rs2_data,
+      (id_op2_sel === OP2_IMI) -> id_imm_i_sext,
+      (id_op2_sel === OP2_IMS) -> id_imm_s_sext,
+      (id_op2_sel === OP2_IMJ) -> id_imm_j_sext,
+      (id_op2_sel === OP2_IMU) -> id_imm_u_shifted
     )
   )
 
   // ********* Decode/Execute (ID/EX) Stage *********
-  exe_reg.pc := id_reg.pc
-  exe_reg.op1_data := id_op1_data
-  exe_reg.op2_data := id_op2_data
-  exe_reg.rs2_data := id_rs2_data
-  exe_reg.wb_addr := id_wb_addr
-  exe_reg.wb_sel := id_wb_sel
-  exe_reg.mem_wen := id_mem_wen
-  exe_reg.rf_wen := id_rf_wen
-  exe_reg.imm_b_sext := id_imm_b_sext
-  exe_reg.exe_fun := id_exe_fun
+  exe_reg_pc := id_reg_pc
+  exe_reg_op1_data := id_op1_data
+  exe_reg_op2_data := id_op2_data
+  exe_reg_rs2_data := id_rs2_data
+  exe_reg_wb_addr := id_wb_addr
+  exe_reg_wb_sel := id_wb_sel
+  exe_reg_mem_wen := id_mem_wen
+  exe_reg_rf_wen := id_rf_wen
+  exe_reg_imm_i_sext := id_imm_i_sext
+  exe_reg_imm_s_sext := id_imm_s_sext
+  exe_reg_imm_b_sext := id_imm_b_sext
+  exe_reg_imm_u_shifted := id_imm_u_shifted
+  exe_reg_imm_z_uext := id_imm_z_uext
+  exe_reg_exe_fun := id_exe_fun
 
   // ********* Execute (EX) Stage *********
-  exe_alu_out := MuxLookup(
-    exe_reg.exe_fun,
-    0.U(WORD_LEN.W)
-  )(
+  exe_alu_out := MuxCase(
+    0.U(WORD_LEN.W),
     Seq(
-      ALU_ADD -> (exe_reg.op1_data + exe_reg.op2_data),
-      ALU_SUB -> (exe_reg.op1_data - exe_reg.op2_data),
-      ALU_AND -> (exe_reg.op1_data & exe_reg.op2_data),
-      ALU_OR -> (exe_reg.op1_data | exe_reg.op2_data),
-      ALU_XOR -> (exe_reg.op1_data ^ exe_reg.op2_data),
-      ALU_SLL -> (exe_reg.op1_data << exe_reg.op2_data(4, 0))(31, 0),
-      ALU_SRL -> (exe_reg.op1_data >> exe_reg.op2_data(4, 0)).asUInt,
-      ALU_SRA -> (exe_reg.op1_data.asSInt >> exe_reg.op2_data(4, 0)).asUInt,
-      ALU_SLT -> (exe_reg.op1_data.asSInt < exe_reg.op2_data.asSInt).asUInt,
-      ALU_COPY1 -> exe_reg.op1_data
+      (exe_reg_exe_fun === ALU_ADD) -> (exe_reg_op1_data + exe_reg_op2_data),
+      (exe_reg_exe_fun === ALU_SUB) -> (exe_reg_op1_data - exe_reg_op2_data),
+      (exe_reg_exe_fun === ALU_AND) -> (exe_reg_op1_data & exe_reg_op2_data),
+      (exe_reg_exe_fun === ALU_OR) -> (exe_reg_op1_data | exe_reg_op2_data),
+      (exe_reg_exe_fun === ALU_XOR) -> (exe_reg_op1_data ^ exe_reg_op2_data),
+      (exe_reg_exe_fun === ALU_SLL) -> (exe_reg_op1_data << exe_reg_op2_data(
+        4,
+        0
+      )),
+      (exe_reg_exe_fun === ALU_SRL) -> (exe_reg_op1_data >> exe_reg_op2_data(
+        4,
+        0
+      )).asUInt,
+      (exe_reg_exe_fun === ALU_SRA) -> (exe_reg_op1_data.asSInt >> exe_reg_op2_data(
+        4,
+        0
+      )).asUInt,
+      (exe_reg_exe_fun === ALU_SLT) -> (exe_reg_op1_data.asSInt < exe_reg_op2_data.asSInt).asUInt,
+      (exe_reg_exe_fun === ALU_SLTU) -> (exe_reg_op1_data < exe_reg_op2_data).asUInt,
+      (exe_reg_exe_fun === ALU_JALR) -> ((exe_reg_op1_data + exe_reg_op2_data) & (~1
+        .U(WORD_LEN.W))),
+      (exe_reg_exe_fun === ALU_COPY1) -> exe_reg_op1_data
     )
   )
 
-  exe_br_flg := MuxLookup(
-    exe_reg.exe_fun,
-    false.B
-  )(
+  exe_br_flg := MuxCase(
+    false.B,
     Seq(
-      BR_BEQ -> (exe_reg.op1_data === exe_reg.op2_data),
-      BR_BNE -> (exe_reg.op1_data =/= exe_reg.op2_data)
+      (exe_reg_exe_fun === BR_BEQ) -> (exe_reg_op1_data === exe_reg_op2_data).asBool,
+      (exe_reg_exe_fun === BR_BNE) -> !(exe_reg_op1_data === exe_reg_op2_data).asBool
     )
   )
 
-  exe_br_target := exe_reg.pc + exe_reg.imm_b_sext
-  exe_jmp_flg := (exe_reg.wb_sel === WB_PC)
+  exe_br_target := exe_reg_pc + exe_reg_imm_b_sext
 
-  // ********* Execute/Memory (EX/MEM) Stage *********
-  mem_reg.pc := exe_reg.pc
-  mem_reg.wb_addr := exe_reg.wb_addr
-  mem_reg.alu_out := exe_alu_out
-  mem_reg.rs2_data := exe_reg.rs2_data
-  mem_reg.rf_wen := exe_reg.rf_wen
-  mem_reg.wb_sel := exe_reg.wb_sel
-  mem_reg.mem_wen := exe_reg.mem_wen
+  exe_jmp_flg := (exe_reg_wb_sel === WB_PC)
+
+  // ********** Execute/Memory (EX/MEM) Stage ***********
+  mem_reg_pc := exe_reg_pc
+  mem_reg_op1_data := exe_reg_op1_data
+  mem_reg_rs2_data := exe_reg_rs2_data
+  mem_reg_wb_addr := exe_reg_wb_addr
+  mem_reg_alu_out := exe_alu_out
+  mem_reg_rf_wen := exe_reg_rf_wen
+  mem_reg_wb_sel := exe_reg_wb_sel
+  mem_reg_imm_z_uext := exe_reg_imm_z_uext
+  mem_reg_mem_wen := exe_reg_mem_wen
 
   // ********* Memory (MEM) Stage *********
-  io.dmem.addr := mem_reg.alu_out
-  io.dmem.wen := mem_reg.mem_wen
-  io.dmem.wdata := mem_reg.rs2_data
+  io.dmem.addr := mem_reg_alu_out
+  io.dmem.wen := mem_reg_mem_wen
+  io.dmem.wdata := mem_reg_rs2_data
 
-  val mem_wb_data = MuxLookup(
-    mem_reg.wb_sel,
-    mem_reg.alu_out
-  )(
+  mem_wb_data := MuxCase(
+    mem_reg_alu_out,
     Seq(
-      WB_MEM -> io.dmem.rdata,
-      WB_PC -> (mem_reg.pc + 4.U(WORD_LEN.W))
+      (mem_reg_wb_sel === WB_MEM) -> io.dmem.rdata,
+      (mem_reg_wb_sel === WB_PC) -> (mem_reg_pc + 4.U(WORD_LEN.W))
     )
   )
 
-  // ********* Memory/Write Back (MEM/WB) Stage *********
-  wb_reg.wb_addr := mem_reg.wb_addr
-  wb_reg.rf_wen := mem_reg.rf_wen
-  wb_reg.wb_data := mem_wb_data
+  // ********** Memory/Write Back (MEM/WB) Stage ***********
+  wb_reg_wb_data := mem_wb_data
+  wb_reg_rf_wen := mem_reg_rf_wen
+  wb_reg_wb_addr := mem_reg_wb_addr
 
   // ********* Write Back (WB) Stage *********
-  when(wb_reg.rf_wen === REN_S) {
-    regfile(wb_reg.wb_addr) := wb_reg.wb_data
-  }
+  when(wb_reg_rf_wen === REN_S) { regfile(wb_reg_wb_addr) := wb_reg_wb_data }
 
-  io.exit := (id_reg.inst === UNIMP)
+  // ********* Debugging *********
+  io.gp := regfile(3)
+  io.exit := (id_reg_inst === UNIMP)
+  printf(p"---------------------\n")
+  // printf(p"if_reg_pc: 0x${Hexadecimal(if_reg_pc)}\n")
+  printf(p"id_reg_pc: 0x${Hexadecimal(id_reg_pc)}\n")
+  printf(p"id_reg_inst: 0x${Hexadecimal(id_reg_inst)}\n")
+  printf(p"id_inst: 0x${Hexadecimal(id_inst)}\n")
+  printf(p"id_rs1_addr: 0x${Hexadecimal(id_rs1_addr)}\n")
+  printf(p"id_rs2_addr: 0x${Hexadecimal(id_rs2_addr)}\n")
+  printf(p"id_wb_addr: 0x${Hexadecimal(id_wb_addr)}\n")
+  printf(p"id_exe_fun: 0x${Hexadecimal(id_exe_fun)}\n")
+  printf(p"id_op1_sel: 0x${Hexadecimal(id_op1_sel)}\n")
+  printf(p"id_op1_data: 0x${Hexadecimal(id_op1_data)}\n")
+  printf(p"id_op2_sel: 0x${Hexadecimal(id_op2_sel)}\n")
+  printf(p"id_op2_data: 0x${Hexadecimal(id_op2_data)}\n")
+  printf(p"id_mem_wen: 0x${Hexadecimal(id_mem_wen)}\n")
+  printf(p"id_rf_wen: 0x${Hexadecimal(id_rf_wen)}\n")
+  printf(p"id_wb_sel: 0x${Hexadecimal(id_wb_sel)}\n")
+  printf(p"id_rs1_data: 0x${Hexadecimal(id_rs1_data)}\n")
+  printf(p"id_rs2_data: 0x${Hexadecimal(id_rs2_data)}\n")
+  // printf(p"exe_reg_pc: 0x${Hexadecimal(exe_reg_pc)}\n")
+  // printf(p"exe_reg_op1_data: 0x${Hexadecimal(id_op1_data)}\n")
+  // printf(p"exe_reg_op2_data: 0x${Hexadecimal(id_op2_data)}\n")
+  printf(p"exe_alu_out: 0x${Hexadecimal(exe_alu_out)}\n")
+  printf(p"mem_reg_pc: 0x${Hexadecimal(mem_reg_pc)}\n")
+  printf(p"mem_reg_alu_out: 0x${Hexadecimal(mem_reg_alu_out)}\n")
+  printf(p"mem_wb_data: 0x${Hexadecimal(mem_wb_data)}\n")
+  printf(p"wb_reg_wb_data: 0${Hexadecimal(wb_reg_wb_data)}\n")
+  printf(p"---------------------\n")
 }
diff --git a/src/main/scala/micore/Memory.scala b/src/main/scala/micore/Memory.scala
index 0bc8045..43cecdc 100755
--- a/src/main/scala/micore/Memory.scala
+++ b/src/main/scala/micore/Memory.scala
@@ -2,14 +2,19 @@ package micore
 
 import chisel3._
 import chisel3.util._
-import chisel3.util.experimental.loadMemoryFromFileInline
+import chisel3.util.experimental.loadMemoryFromFile
 import common.Consts._
+import chisel3.util.experimental.loadMemoryFromFileInline
 
+/** 表示一个指令内存端口接口的类
+  */
 class ImemPortIo extends Bundle {
   val addr = Input(UInt(WORD_LEN.W))
   val inst = Output(UInt(WORD_LEN.W))
 }
 
+/** 表示一个数据内存端口接口的类
+  */
 class DmemPortIo extends Bundle {
   val addr = Input(UInt(WORD_LEN.W))
   val rdata = Output(UInt(WORD_LEN.W))
@@ -19,20 +24,37 @@ class DmemPortIo extends Bundle {
 
 class Memory extends Module {
   val io = IO(new Bundle {
-    val imem = new ImemPortIo
-    val dmem = new DmemPortIo
+    val imem = new ImemPortIo()
+    val dmem = new DmemPortIo()
   })
 
-  // val mem = Mem(8192, UInt(8.W))
-  val mem = SyncReadMem(512, UInt(WORD_LEN.W))
+  // 生成八位宽x4096(4KB)寄存器的存储器。
+  val mem = Mem(4096, UInt(8.W))
 
+  // 加载存储器的初始值。
   loadMemoryFromFileInline(mem, "src/hex/mem.hex")
 
-  io.imem.inst := mem.read(io.imem.addr >> 2) 
+  // 连接四个地址存储的八位数据形成一个32位的指令。
+  io.imem.inst := Cat(
+    mem(io.imem.addr + 3.U(WORD_LEN.W)),
+    mem(io.imem.addr + 2.U(WORD_LEN.W)),
+    mem(io.imem.addr + 1.U(WORD_LEN.W)),
+    mem(io.imem.addr)
+  )
 
-  io.dmem.rdata := mem.read(io.dmem.addr >> 2) 
+  // 连接四个地址存储的八位数据形成一个32位的数据。
+  io.dmem.rdata := Cat(
+    mem(io.dmem.addr + 3.U(WORD_LEN.W)),
+    mem(io.dmem.addr + 2.U(WORD_LEN.W)),
+    mem(io.dmem.addr + 1.U(WORD_LEN.W)),
+    mem(io.dmem.addr)
+  )
 
+  // 写数据到存储器。
   when(io.dmem.wen) {
-    mem.write(io.dmem.addr >> 2, io.dmem.wdata) 
+    mem(io.dmem.addr) := io.dmem.wdata(7, 0)
+    mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(15, 8)
+    mem(io.dmem.addr + 2.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)
+    mem(io.dmem.addr + 3.U(WORD_LEN.W)) := io.dmem.wdata(31, 24)
   }
 }
diff --git a/src/main/scala/micore/Top.scala b/src/main/scala/micore/Top.scala
index 941bdc8..70becd8 100755
--- a/src/main/scala/micore/Top.scala
+++ b/src/main/scala/micore/Top.scala
@@ -8,14 +8,14 @@ import common.Consts._
 class TopOrigin extends Module {
   val io = IO(new Bundle {
     val exit = Output(Bool())
+    val gp = Output(UInt(WORD_LEN.W))
   })
-  val core = Module(new Core)
-  val memory = Module(new Memory)
-
+  val core = Module(new Core())
+  val memory = Module(new Memory())
   core.io.imem <> memory.io.imem
   core.io.dmem <> memory.io.dmem
-
   io.exit := core.io.exit
+  io.gp := core.io.gp
 }
 
 /** Generate Verilog sources and save it in file
@@ -26,8 +26,7 @@ object TopOrigin extends App {
     firtoolOpts = Array(
       "--disable-all-randomization",
       "--strip-debug-info",
-      "--O=release",
-      "--mlir-timing"
+      "--O=release"
     )
   )
 }
diff --git a/src/test/scala/micore/MicoreSpec.scala b/src/test/scala/micore/MicoreSpec.scala
index dc05731..879f293 100755
--- a/src/test/scala/micore/MicoreSpec.scala
+++ b/src/test/scala/micore/MicoreSpec.scala
@@ -1,8 +1,9 @@
 package micore
 
 import chisel3._
-import org.scalatest.flatspec._
 import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
 
 class CTest extends AnyFlatSpec with ChiselScalatestTester {
   "Micore" should "run the C program" in {
diff --git a/target/scala-2.13/-name-_2.13-0.1.0.jar b/target/scala-2.13/-name-_2.13-0.1.0.jar
index c5de2f01d9ae07ebd66cd0c69033de0ceb21b804..8c2320e0c41d1c4b347d1f06174908ab2cfb8566 100755
GIT binary patch
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diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous
index 8692e93..422b9f2 100755
--- a/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$4.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$2.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$5.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$3.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
\ No newline at end of file
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$delayedInit$body.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/TopOrigin$.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class","/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/zinc/inc_compile_2.13.zip"]]
\ No newline at end of file
diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out
index 69ae457..debaacf 100755
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
@@ -1,6 +1,58 @@
 [debug] [zinc] IncrementalCompile -----------
 [debug] IncrementalCompile.incrementalCompile
-[debug] previous = Stamps for: 18 products, 5 sources, 2 libraries
+[debug] previous = Stamps for: 14 products, 5 sources, 2 libraries
 [debug] current source = Set(${BASE}/src/main/scala/micore/Core.scala, ${BASE}/src/main/scala/micore/Top.scala, ${BASE}/src/main/scala/common/Instructions.scala, ${BASE}/src/main/scala/micore/Memory.scala, ${BASE}/src/main/scala/common/Consts.scala)
-[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
-[debug] No changes
+[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala), unmodified = ...),Set(),Set(),API Changes: Set())
+[debug] 
+[debug] Initial source changes:
+[debug] 	removed: Set()
+[debug] 	added: Set()
+[debug] 	modified: Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala)
+[debug] Invalidated products: Set()
+[debug] External API changes: API Changes: Set()
+[debug] Modified binary dependencies: Set()
+[debug] Initial directly invalidated classes: Set(common.Consts, micore.Core)
+[debug] Sources indirectly invalidated by:
+[debug] 	product: Set()
+[debug] 	binary dep: Set()
+[debug] 	external source: Set()
+[debug] All initially invalidated classes: Set(common.Consts, micore.Core)
+[debug] All initially invalidated sources:Set(${BASE}/src/main/scala/common/Consts.scala, ${BASE}/src/main/scala/micore/Core.scala)
+[debug] Initial set of included nodes: common.Consts, micore.Core
+[debug] compilation cycle 1
+[info] compiling 2 Scala sources to /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes ...
+[debug] Returning already retrieved and compiled bridge: /home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala2-sbt-bridge/2.13.12/scala2-sbt-bridge-2.13.12.jar.
+[debug] [zinc] Running cached compiler 6e7cf61b for Scala compiler version 2.13.12
+[debug] [zinc] The Scala compiler is invoked with:
+[debug] 	-language:reflectiveCalls
+[debug] 	-deprecation
+[debug] 	-feature
+[debug] 	-Xcheckinit
+[debug] 	-Ymacro-annotations
+[debug] 	-Xplugin:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel-plugin_2.13.12/6.2.0/chisel-plugin_2.13.12-6.2.0.jar
+[debug] 	-bootclasspath
+[debug] 	/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.13.12/scala-library-2.13.12.jar
+[debug] 	-classpath
+[debug] 	/run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/chisel_2.13/6.2.0/chisel_2.13-6.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.13.12/scala-reflect-2.13.12.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.13/4.1.0/scopt_2.13-4.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.13/0.4.2/moultingyaml_2.13-0.4.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.13/4.0.6/json4s-native_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.10.0/commons-text-1.10.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/data-class_2.13/0.2.6/data-class_2.13-0.2.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/os-lib_2.13/0.9.2/os-lib_2.13-0.9.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parallel-collections_2.13/1.0.4/scala-parallel-collections_2.13-1.0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle_2.13/3.1.0/upickle_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/chipsalliance/firtool-resolver_2.13/1.3.0/firtool-resolver_2.13-1.3.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.13/2.22.0/nscala-time_2.13-2.22.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.13/4.0.6/json4s-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native-core_2.13/4.0.6/json4s-native-core_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.12.0/commons-lang3-3.12.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/geny_2.13/1.0.0/geny_2.13-1.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/ujson_2.13/3.1.0/ujson_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upack_2.13/3.1.0/upack_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-implicits_2.13/3.1.0/upickle-implicits_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/dev/dirs/directories/26/directories-26.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/scribe_2.13/3.13.0/scribe_2.13-3.13.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier_2.13/2.1.8/coursier_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.13/4.0.6/json4s-ast_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.13/4.0.6/json4s-scalap_2.13-4.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/upickle-core_2.13/3.1.0/upickle-core_2.13-3.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/perfolation_2.13/1.2.9/perfolation_2.13-1.2.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.13/0.3.1/sourcecode_2.13-0.3.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-collection-compat_2.13/2.11.0/scala-collection-compat_2.13-2.11.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/outr/moduload_2.13/1.1.7/moduload_2.13-1.1.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.13/2.13.5.2/jsoniter-scala-core_2.13-2.13.5.2.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-core_2.13/2.1.8/coursier-core_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-cache_2.13/2.1.8/coursier-cache_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-proxy-setup/2.1.8/coursier-proxy-setup-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/concurrent-reference-hash-map/1.1.0/concurrent-reference-hash-map-1.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.13/2.2.0/scala-xml_2.13-2.2.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/coursier-util_2.13/2.1.8/coursier-util_2.13-2.1.8.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/jniutils/windows-jni-utils/0.3.3/windows-jni-utils-0.3.3.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-archiver/4.9.0/plexus-archiver-4.9.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-container-default/2.1.1/plexus-container-default-2.1.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/virtuslab/scala-cli/config_2.13/0.2.1/config_2.13-0.2.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/alexarchambault/windows-ansi/windows-ansi/0.0.5/windows-ansi-0.0.5.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/javax/inject/javax.inject/1/javax.inject-1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-utils/4.0.0/plexus-utils-4.0.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-io/3.4.1/plexus-io-3.4.1.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/commons-io/commons-io/2.15.0/commons-io-2.15.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-compress/1.24.0/commons-compress-1.24.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.36/slf4j-api-1.7.36.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/iq80/snappy/snappy/0.4/snappy-0.4.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/tukaani/xz/1.9/xz-1.9.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/luben/zstd-jni/1.5.5-10/zstd-jni-1.5.5-10.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/codehaus/plexus/plexus-classworlds/2.6.0/plexus-classworlds-2.6.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/xbean/xbean-reflect/3.7/xbean-reflect-3.7.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.18/jansi-1.18.jar
+[debug] Invalidating (transitively) by inheritance from common.Consts...
+[debug] Initial set of included nodes: common.Consts
+[debug] Invalidated by transitive inheritance dependency: Set(common.Consts)
+[debug] None of the modified names appears in source file of micore.TopOrigin. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of micore.ImemPortIo. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of micore.Core. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of micore.Memory. This dependency is not being considered for invalidation.
+[debug] None of the modified names appears in source file of micore.DmemPortIo. This dependency is not being considered for invalidation.
+[debug] Change NamesChange(common.Consts,ModifiedNames(changes = UsedName(OP1_IMZ,[Default]))) invalidates 1 classes due to The common.Consts has the following regular definitions changed:
+[debug] 	UsedName(OP1_IMZ,[Default]).
+[debug]   > by transitive inheritance: Set(common.Consts)
+[debug]   > 
+[debug]   > 
+[debug]         
+[debug] New invalidations:
+[debug] Initial set of included nodes: 
+[debug] Previously invalidated, but (transitively) depend on new invalidations:
+[debug] Final step, transitive dependencies:
+[debug] 	Set()
+[debug] No classes were invalidated.
+[debug] Scala compilation took 2.955256556 s
+[debug] done compiling
diff --git a/target/streams/compile/incOptions/_global/streams/out b/target/streams/compile/incOptions/_global/streams/out
index 9479f4e..a11cadf 100755
--- a/target/streams/compile/incOptions/_global/streams/out
+++ b/target/streams/compile/incOptions/_global/streams/out
@@ -1,2 +1,17 @@
 [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
+[debug] About to delete class files:
+[debug] 	Consts$.class
+[debug] 	Consts.class
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
+[debug] We backup class files:
+[debug] 	Consts$.class
+[debug] 	Consts.class
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
+[debug] Registering generated classes:
+[debug] 	Consts.class
+[debug] 	Consts$.class
+[debug] 	Core$$anon$1.class
+[debug] 	Core.class
 [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs
index c77af77..d9a0ca3 100755
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@@ -1 +1 @@
--153958634
\ No newline at end of file
+-627113868
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out
index 594010b..766e80b 100755
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@@ -14,14 +14,6 @@
 [debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore
 [debug] 	micore/Core$$anon$1.class
 [debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
-[debug] 	micore/Core$$anon$2.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$2.class
-[debug] 	micore/Core$$anon$3.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$3.class
-[debug] 	micore/Core$$anon$4.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$4.class
-[debug] 	micore/Core$$anon$5.class
-[debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$5.class
 [debug] 	micore/Core.class
 [debug] 	  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class
 [debug] 	micore/DmemPortIo.class
diff --git a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
index 1f38fae..49b023a 100755
--- a/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
+++ b/test_run_dir/Micore_should_run_the_C_program/TopOrigin.lo.fir
@@ -10,176 +10,227 @@ circuit TopOrigin :
     output io_dmem_wen : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
     output io_dmem_wdata : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
     output io_exit : UInt<1> @[src/main/scala/micore/Core.scala 9:14]
+    output io_gp : UInt<32> @[src/main/scala/micore/Core.scala 9:14]
 
-    mem regfile : @[src/main/scala/micore/Core.scala 16:28]
+    mem regfile : @[src/main/scala/micore/Core.scala 16:20]
       data-type => UInt<32>
       depth => 32
-      read-latency => 1
+      read-latency => 0
       write-latency => 1
       reader => id_rs1_data_MPORT
       reader => id_rs2_data_MPORT
+      reader => io_gp_MPORT
       writer => MPORT
       read-under-write => undefined
     reg id_reg_pc : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 19:19]
+      reset => (UInt<1>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 20:26]
     reg id_reg_inst : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 19:19]
+      reset => (UInt<1>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 21:28]
     reg exe_reg_pc : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 24:27]
     reg exe_reg_wb_addr : UInt<5>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 25:32]
     reg exe_reg_op1_data : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 26:33]
     reg exe_reg_op2_data : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_op2_data) @[src/main/scala/micore/Core.scala 27:33]
     reg exe_reg_rs2_data : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 28:33]
     reg exe_reg_exe_fun : UInt<5>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 29:32]
     reg exe_reg_mem_wen : UInt<2>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 30:32]
     reg exe_reg_rf_wen : UInt<2>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 31:31]
     reg exe_reg_wb_sel : UInt<3>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 32:31]
+    reg exe_reg_imm_i_sext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_i_sext) @[src/main/scala/micore/Core.scala 33:35]
+    reg exe_reg_imm_s_sext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_s_sext) @[src/main/scala/micore/Core.scala 34:35]
     reg exe_reg_imm_b_sext : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 24:20]
+      reset => (UInt<1>("h0"), exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 35:35]
+    reg exe_reg_imm_u_shifted : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_u_shifted) @[src/main/scala/micore/Core.scala 36:38]
+    reg exe_reg_imm_z_uext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 37:35]
     reg mem_reg_pc : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 37:20]
+      reset => (UInt<1>("h0"), mem_reg_pc) @[src/main/scala/micore/Core.scala 40:27]
     reg mem_reg_wb_addr : UInt<5>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 37:20]
-    reg mem_reg_alu_out : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 37:20]
+      reset => (UInt<1>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 41:32]
+    reg mem_reg_op1_data : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_op1_data) @[src/main/scala/micore/Core.scala 42:33]
     reg mem_reg_rs2_data : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 37:20]
-    reg mem_reg_rf_wen : UInt<2>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 37:20]
-    reg mem_reg_wb_sel : UInt<3>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 37:20]
+      reset => (UInt<1>("h0"), mem_reg_rs2_data) @[src/main/scala/micore/Core.scala 43:33]
     reg mem_reg_mem_wen : UInt<2>, clock with :
-      reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 37:20]
+      reset => (UInt<1>("h0"), mem_reg_mem_wen) @[src/main/scala/micore/Core.scala 44:32]
+    reg mem_reg_rf_wen : UInt<2>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 45:31]
+    reg mem_reg_wb_sel : UInt<3>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 46:31]
+    reg mem_reg_imm_z_uext : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 47:35]
+    reg mem_reg_alu_out : UInt<32>, clock with :
+      reset => (UInt<1>("h0"), mem_reg_alu_out) @[src/main/scala/micore/Core.scala 48:32]
     reg wb_reg_wb_addr : UInt<5>, clock with :
-      reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 47:19]
+      reset => (UInt<1>("h0"), wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 51:31]
     reg wb_reg_rf_wen : UInt<2>, clock with :
-      reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 47:19]
+      reset => (UInt<1>("h0"), wb_reg_rf_wen) @[src/main/scala/micore/Core.scala 52:30]
     reg wb_reg_wb_data : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 47:19]
+      reset => (UInt<1>("h0"), wb_reg_wb_data) @[src/main/scala/micore/Core.scala 53:31]
     reg if_reg_pc : UInt<32>, clock with :
-      reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 54:26]
-    node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 64:31]
-    node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 64:31]
-    node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 92:21]
-    node id_rs1_addr = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 86:32]
-    node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 92:48]
-    node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 92:32]
-    node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 92:73]
-    node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 92:57]
-    node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 94:21]
-    node id_rs2_addr = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 87:32]
-    node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 94:48]
-    node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 94:32]
-    node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 94:73]
-    node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 94:57]
-    node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 95:36]
-    node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 58:23 95:13]
+      reset => (UInt<1>("h0"), if_reg_pc) @[src/main/scala/micore/Core.scala 56:26]
+    node _if_pc_plus4_T = add(if_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 66:31]
+    node if_pc_plus4 = tail(_if_pc_plus4_T, 1) @[src/main/scala/micore/Core.scala 66:31]
+    node _id_rs1_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 93:21]
+    node id_rs1_addr_b = bits(id_reg_inst, 25, 21) @[src/main/scala/micore/Core.scala 88:34]
+    node _id_rs1_data_hazard_T_1 = neq(id_rs1_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 93:50]
+    node _id_rs1_data_hazard_T_2 = and(_id_rs1_data_hazard_T, _id_rs1_data_hazard_T_1) @[src/main/scala/micore/Core.scala 93:32]
+    node _id_rs1_data_hazard_T_3 = eq(id_rs1_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 93:77]
+    node id_rs1_data_hazard = and(_id_rs1_data_hazard_T_2, _id_rs1_data_hazard_T_3) @[src/main/scala/micore/Core.scala 93:59]
+    node _id_rs2_data_hazard_T = eq(exe_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 95:21]
+    node id_rs2_addr_b = bits(id_reg_inst, 20, 16) @[src/main/scala/micore/Core.scala 89:34]
+    node _id_rs2_data_hazard_T_1 = neq(id_rs2_addr_b, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 95:50]
+    node _id_rs2_data_hazard_T_2 = and(_id_rs2_data_hazard_T, _id_rs2_data_hazard_T_1) @[src/main/scala/micore/Core.scala 95:32]
+    node _id_rs2_data_hazard_T_3 = eq(id_rs2_addr_b, exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 95:77]
+    node id_rs2_data_hazard = and(_id_rs2_data_hazard_T_2, _id_rs2_data_hazard_T_3) @[src/main/scala/micore/Core.scala 95:59]
+    node _stall_flg_T = or(id_rs1_data_hazard, id_rs2_data_hazard) @[src/main/scala/micore/Core.scala 96:36]
+    node stall_flg = _stall_flg_T @[src/main/scala/micore/Core.scala 60:23 96:13]
     node _if_pc_next_T = mux(stall_flg, if_reg_pc, if_pc_plus4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
-    node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 222:34]
-    node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 222:15 61:25]
-    node _exe_alu_out_T_37 = eq(UInt<5>("he"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_35 = eq(UInt<5>("h9"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_16 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 206:36]
-    node _exe_alu_out_T_17 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 206:62]
-    node _exe_alu_out_T_18 = lt(_exe_alu_out_T_16, _exe_alu_out_T_17) @[src/main/scala/micore/Core.scala 206:43]
-    node _exe_alu_out_T_33 = eq(UInt<5>("h8"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_12 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 205:36]
-    node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 205:62]
-    node _exe_alu_out_T_14 = dshr(_exe_alu_out_T_12, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 205:43]
-    node _exe_alu_out_T_15 = asUInt(_exe_alu_out_T_14) @[src/main/scala/micore/Core.scala 205:70]
-    node _exe_alu_out_T_31 = eq(UInt<5>("h7"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_10 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 204:55]
-    node _exe_alu_out_T_11 = dshr(exe_reg_op1_data, _exe_alu_out_T_10) @[src/main/scala/micore/Core.scala 204:36]
-    node _exe_alu_out_T_29 = eq(UInt<5>("h6"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_7 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 203:55]
-    node _exe_alu_out_T_8 = dshl(exe_reg_op1_data, _exe_alu_out_T_7) @[src/main/scala/micore/Core.scala 203:36]
-    node _exe_alu_out_T_9 = bits(_exe_alu_out_T_8, 31, 0) @[src/main/scala/micore/Core.scala 203:62]
-    node _exe_alu_out_T_27 = eq(UInt<5>("h5"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_6 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:36]
-    node _exe_alu_out_T_25 = eq(UInt<5>("h4"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_5 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:35]
-    node _exe_alu_out_T_23 = eq(UInt<5>("h3"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_4 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 200:36]
-    node _exe_alu_out_T_21 = eq(UInt<5>("h2"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_2 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 199:36]
-    node _exe_alu_out_T_3 = tail(_exe_alu_out_T_2, 1) @[src/main/scala/micore/Core.scala 199:36]
-    node _exe_alu_out_T_19 = eq(UInt<5>("h1"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 198:36]
-    node _exe_alu_out_T_1 = tail(_exe_alu_out_T, 1) @[src/main/scala/micore/Core.scala 198:36]
-    node _exe_alu_out_T_20 = mux(_exe_alu_out_T_19, _exe_alu_out_T_1, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_22 = mux(_exe_alu_out_T_21, _exe_alu_out_T_3, _exe_alu_out_T_20) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_24 = mux(_exe_alu_out_T_23, _exe_alu_out_T_4, _exe_alu_out_T_22) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_26 = mux(_exe_alu_out_T_25, _exe_alu_out_T_5, _exe_alu_out_T_24) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_28 = mux(_exe_alu_out_T_27, _exe_alu_out_T_6, _exe_alu_out_T_26) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_30 = mux(_exe_alu_out_T_29, _exe_alu_out_T_9, _exe_alu_out_T_28) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_32 = mux(_exe_alu_out_T_31, _exe_alu_out_T_11, _exe_alu_out_T_30) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_34 = mux(_exe_alu_out_T_33, _exe_alu_out_T_15, _exe_alu_out_T_32) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_36 = mux(_exe_alu_out_T_35, _exe_alu_out_T_18, _exe_alu_out_T_34) @[src/main/scala/micore/Core.scala 196:4]
-    node _exe_alu_out_T_38 = mux(_exe_alu_out_T_37, exe_reg_op1_data, _exe_alu_out_T_36) @[src/main/scala/micore/Core.scala 196:4]
-    node exe_alu_out = _exe_alu_out_T_38 @[src/main/scala/micore/Core.scala 193:15 62:25]
+    node _exe_jmp_flg_T = eq(exe_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 236:34]
+    node exe_jmp_flg = _exe_jmp_flg_T @[src/main/scala/micore/Core.scala 236:15 63:25]
+    node _exe_alu_out_T = eq(exe_reg_exe_fun, UInt<5>("h1")) @[src/main/scala/micore/Core.scala 201:24]
+    node _exe_alu_out_T_1 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 201:58]
+    node _exe_alu_out_T_2 = tail(_exe_alu_out_T_1, 1) @[src/main/scala/micore/Core.scala 201:58]
+    node _exe_alu_out_T_3 = eq(exe_reg_exe_fun, UInt<5>("h2")) @[src/main/scala/micore/Core.scala 202:24]
+    node _exe_alu_out_T_4 = sub(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 202:58]
+    node _exe_alu_out_T_5 = tail(_exe_alu_out_T_4, 1) @[src/main/scala/micore/Core.scala 202:58]
+    node _exe_alu_out_T_6 = eq(exe_reg_exe_fun, UInt<5>("h3")) @[src/main/scala/micore/Core.scala 203:24]
+    node _exe_alu_out_T_7 = and(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 203:58]
+    node _exe_alu_out_T_8 = eq(exe_reg_exe_fun, UInt<5>("h4")) @[src/main/scala/micore/Core.scala 204:24]
+    node _exe_alu_out_T_9 = or(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 204:57]
+    node _exe_alu_out_T_10 = eq(exe_reg_exe_fun, UInt<5>("h5")) @[src/main/scala/micore/Core.scala 205:24]
+    node _exe_alu_out_T_11 = xor(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 205:58]
+    node _exe_alu_out_T_12 = eq(exe_reg_exe_fun, UInt<5>("h6")) @[src/main/scala/micore/Core.scala 206:24]
+    node _exe_alu_out_T_13 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 206:77]
+    node _exe_alu_out_T_14 = dshl(exe_reg_op1_data, _exe_alu_out_T_13) @[src/main/scala/micore/Core.scala 206:58]
+    node _exe_alu_out_T_15 = eq(exe_reg_exe_fun, UInt<5>("h7")) @[src/main/scala/micore/Core.scala 210:24]
+    node _exe_alu_out_T_16 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 210:77]
+    node _exe_alu_out_T_17 = dshr(exe_reg_op1_data, _exe_alu_out_T_16) @[src/main/scala/micore/Core.scala 210:58]
+    node _exe_alu_out_T_18 = eq(exe_reg_exe_fun, UInt<5>("h8")) @[src/main/scala/micore/Core.scala 214:24]
+    node _exe_alu_out_T_19 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 214:58]
+    node _exe_alu_out_T_20 = bits(exe_reg_op2_data, 4, 0) @[src/main/scala/micore/Core.scala 214:84]
+    node _exe_alu_out_T_21 = dshr(_exe_alu_out_T_19, _exe_alu_out_T_20) @[src/main/scala/micore/Core.scala 214:65]
+    node _exe_alu_out_T_22 = asUInt(_exe_alu_out_T_21) @[src/main/scala/micore/Core.scala 217:10]
+    node _exe_alu_out_T_23 = eq(exe_reg_exe_fun, UInt<5>("h9")) @[src/main/scala/micore/Core.scala 218:24]
+    node _exe_alu_out_T_24 = asSInt(exe_reg_op1_data) @[src/main/scala/micore/Core.scala 218:58]
+    node _exe_alu_out_T_25 = asSInt(exe_reg_op2_data) @[src/main/scala/micore/Core.scala 218:84]
+    node _exe_alu_out_T_26 = lt(_exe_alu_out_T_24, _exe_alu_out_T_25) @[src/main/scala/micore/Core.scala 218:65]
+    node _exe_alu_out_T_27 = eq(exe_reg_exe_fun, UInt<5>("ha")) @[src/main/scala/micore/Core.scala 219:24]
+    node _exe_alu_out_T_28 = lt(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 219:59]
+    node _exe_alu_out_T_29 = eq(exe_reg_exe_fun, UInt<5>("h11")) @[src/main/scala/micore/Core.scala 220:24]
+    node _exe_alu_out_T_30 = add(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 220:60]
+    node _exe_alu_out_T_31 = tail(_exe_alu_out_T_30, 1) @[src/main/scala/micore/Core.scala 220:60]
+    node _exe_alu_out_T_32 = not(UInt<32>("h1")) @[src/main/scala/micore/Core.scala 220:83]
+    node _exe_alu_out_T_33 = and(_exe_alu_out_T_31, _exe_alu_out_T_32) @[src/main/scala/micore/Core.scala 220:80]
+    node _exe_alu_out_T_34 = eq(exe_reg_exe_fun, UInt<5>("h12")) @[src/main/scala/micore/Core.scala 222:24]
+    node _exe_alu_out_T_35 = mux(_exe_alu_out_T_34, exe_reg_op1_data, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_36 = mux(_exe_alu_out_T_29, _exe_alu_out_T_33, _exe_alu_out_T_35) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_37 = mux(_exe_alu_out_T_27, _exe_alu_out_T_28, _exe_alu_out_T_36) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_38 = mux(_exe_alu_out_T_23, _exe_alu_out_T_26, _exe_alu_out_T_37) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_39 = mux(_exe_alu_out_T_18, _exe_alu_out_T_22, _exe_alu_out_T_38) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_40 = mux(_exe_alu_out_T_15, _exe_alu_out_T_17, _exe_alu_out_T_39) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_41 = mux(_exe_alu_out_T_12, _exe_alu_out_T_14, _exe_alu_out_T_40) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_42 = mux(_exe_alu_out_T_10, _exe_alu_out_T_11, _exe_alu_out_T_41) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_43 = mux(_exe_alu_out_T_8, _exe_alu_out_T_9, _exe_alu_out_T_42) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_44 = mux(_exe_alu_out_T_6, _exe_alu_out_T_7, _exe_alu_out_T_43) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_45 = mux(_exe_alu_out_T_3, _exe_alu_out_T_5, _exe_alu_out_T_44) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_alu_out_T_46 = mux(_exe_alu_out_T, _exe_alu_out_T_2, _exe_alu_out_T_45) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node exe_alu_out = bits(_exe_alu_out_T_46, 31, 0) @[src/main/scala/micore/Core.scala 198:15 64:25]
     node _if_pc_next_T_1 = mux(exe_jmp_flg, exe_alu_out, _if_pc_next_T) @[src/main/scala/chisel3/util/Mux.scala 126:16]
-    node _exe_br_flg_T_4 = eq(UInt<5>("hc"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4]
-    node _exe_br_flg_T_1 = neq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 217:35]
-    node _exe_br_flg_T_2 = eq(UInt<5>("hb"), exe_reg_exe_fun) @[src/main/scala/micore/Core.scala 214:4]
-    node _exe_br_flg_T = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 216:35]
-    node _exe_br_flg_T_3 = mux(_exe_br_flg_T_2, _exe_br_flg_T, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 214:4]
-    node _exe_br_flg_T_5 = mux(_exe_br_flg_T_4, _exe_br_flg_T_1, _exe_br_flg_T_3) @[src/main/scala/micore/Core.scala 214:4]
-    node exe_br_flg = _exe_br_flg_T_5 @[src/main/scala/micore/Core.scala 211:14 59:24]
-    node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 221:31]
-    node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 221:31]
-    node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 221:17 60:27]
+    node _exe_br_flg_T = eq(exe_reg_exe_fun, UInt<5>("hb")) @[src/main/scala/micore/Core.scala 229:24]
+    node _exe_br_flg_T_1 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 229:57]
+    node _exe_br_flg_T_2 = eq(exe_reg_exe_fun, UInt<5>("hc")) @[src/main/scala/micore/Core.scala 230:24]
+    node _exe_br_flg_T_3 = eq(exe_reg_op1_data, exe_reg_op2_data) @[src/main/scala/micore/Core.scala 230:58]
+    node _exe_br_flg_T_4 = eq(_exe_br_flg_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 230:39]
+    node _exe_br_flg_T_5 = mux(_exe_br_flg_T_2, _exe_br_flg_T_4, UInt<1>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _exe_br_flg_T_6 = mux(_exe_br_flg_T, _exe_br_flg_T_1, _exe_br_flg_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node exe_br_flg = _exe_br_flg_T_6 @[src/main/scala/micore/Core.scala 226:14 61:24]
+    node _exe_br_target_T = add(exe_reg_pc, exe_reg_imm_b_sext) @[src/main/scala/micore/Core.scala 234:31]
+    node _exe_br_target_T_1 = tail(_exe_br_target_T, 1) @[src/main/scala/micore/Core.scala 234:31]
+    node exe_br_target = _exe_br_target_T_1 @[src/main/scala/micore/Core.scala 234:17 62:27]
     node if_pc_next = mux(exe_br_flg, exe_br_target, _if_pc_next_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
-    node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 76:19]
-    node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 80:19]
+    node _id_reg_pc_T = mux(stall_flg, id_reg_pc, if_reg_pc) @[src/main/scala/micore/Core.scala 78:19]
+    node _id_reg_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 82:19]
     node _id_reg_inst_T_1 = mux(stall_flg, id_reg_inst, io_imem_inst) @[src/main/scala/chisel3/util/Mux.scala 126:16]
     node _id_reg_inst_T_2 = mux(_id_reg_inst_T, UInt<32>("h0"), _id_reg_inst_T_1) @[src/main/scala/chisel3/util/Mux.scala 126:16]
-    node id_wb_addr = bits(id_reg_inst, 15, 11) @[src/main/scala/micore/Core.scala 88:31]
-    node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 98:21]
-    node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 98:36]
-    node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 98:8]
-    node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 101:17]
-    node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 104:20]
-    node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 104:60]
-    node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 104:41]
-    node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 107:22]
-    node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 107:60]
-    node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 107:42]
-    node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/micore/Core.scala 106:10]
-    node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_reg_alu_out, _id_rs1_data_T_7) @[src/main/scala/micore/Core.scala 103:8]
-    node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/micore/Core.scala 100:24]
-    node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 114:17]
-    node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 117:20]
-    node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 117:60]
-    node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 117:41]
-    node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 120:22]
-    node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 120:60]
-    node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 120:42]
-    node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/micore/Core.scala 119:10]
-    node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_reg_alu_out, _id_rs2_data_T_7) @[src/main/scala/micore/Core.scala 116:8]
-    node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/micore/Core.scala 113:24]
-    node _id_imm_i_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 128:43]
-    node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 128:31]
-    node _id_imm_i_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 128:57]
-    node id_imm_i_sext = cat(_id_imm_i_sext_T_1, _id_imm_i_sext_T_2) @[src/main/scala/micore/Core.scala 128:26]
-    node _id_imm_b_sext_T = bits(id_inst, 15, 15) @[src/main/scala/micore/Core.scala 129:43]
-    node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 129:31]
-    node _id_imm_b_sext_T_2 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 129:57]
-    node id_imm_b_sext = cat(_id_imm_b_sext_T_1, _id_imm_b_sext_T_2) @[src/main/scala/micore/Core.scala 129:26]
-    node _csignals_T = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _id_inst_T = or(exe_br_flg, exe_jmp_flg) @[src/main/scala/micore/Core.scala 99:21]
+    node _id_inst_T_1 = or(_id_inst_T, stall_flg) @[src/main/scala/micore/Core.scala 99:36]
+    node id_inst = mux(_id_inst_T_1, UInt<32>("h0"), id_reg_inst) @[src/main/scala/micore/Core.scala 99:8]
+    node id_rs1_addr = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 101:28]
+    node id_rs2_addr = bits(id_inst, 20, 16) @[src/main/scala/micore/Core.scala 102:28]
+    node id_wb_addr = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 103:27]
+    node _id_rs1_data_T = eq(id_rs1_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 109:20]
+    node _id_rs1_data_T_1 = eq(id_rs1_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 110:21]
+    node _id_rs1_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 110:61]
+    node _id_rs1_data_T_3 = and(_id_rs1_data_T_1, _id_rs1_data_T_2) @[src/main/scala/micore/Core.scala 110:42]
+    node _id_rs1_data_T_4 = eq(id_rs1_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 111:21]
+    node _id_rs1_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 111:59]
+    node _id_rs1_data_T_6 = and(_id_rs1_data_T_4, _id_rs1_data_T_5) @[src/main/scala/micore/Core.scala 111:41]
+    node _id_rs1_data_T_7 = mux(_id_rs1_data_T_6, wb_reg_wb_data, regfile.id_rs1_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _mem_wb_data_T = eq(mem_reg_wb_sel, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 257:23]
+    node _mem_wb_data_T_1 = eq(mem_reg_wb_sel, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 258:23]
+    node _mem_wb_data_T_2 = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 258:49]
+    node _mem_wb_data_T_3 = tail(_mem_wb_data_T_2, 1) @[src/main/scala/micore/Core.scala 258:49]
+    node _mem_wb_data_T_4 = mux(_mem_wb_data_T_1, _mem_wb_data_T_3, mem_reg_alu_out) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _mem_wb_data_T_5 = mux(_mem_wb_data_T, io_dmem_rdata, _mem_wb_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node mem_wb_data = _mem_wb_data_T_5 @[src/main/scala/micore/Core.scala 105:25 254:15]
+    node _id_rs1_data_T_8 = mux(_id_rs1_data_T_3, mem_wb_data, _id_rs1_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_rs1_data = mux(_id_rs1_data_T, UInt<32>("h0"), _id_rs1_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rs2_data_T = eq(id_rs2_addr, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 117:20]
+    node _id_rs2_data_T_1 = eq(id_rs2_addr, mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 118:21]
+    node _id_rs2_data_T_2 = eq(mem_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 118:61]
+    node _id_rs2_data_T_3 = and(_id_rs2_data_T_1, _id_rs2_data_T_2) @[src/main/scala/micore/Core.scala 118:42]
+    node _id_rs2_data_T_4 = eq(id_rs2_addr, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 119:21]
+    node _id_rs2_data_T_5 = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 119:59]
+    node _id_rs2_data_T_6 = and(_id_rs2_data_T_4, _id_rs2_data_T_5) @[src/main/scala/micore/Core.scala 119:41]
+    node _id_rs2_data_T_7 = mux(_id_rs2_data_T_6, wb_reg_wb_data, regfile.id_rs2_data_MPORT.data) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_rs2_data_T_8 = mux(_id_rs2_data_T_3, mem_wb_data, _id_rs2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_rs2_data = mux(_id_rs2_data_T, UInt<32>("h0"), _id_rs2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_imm_i = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 123:25]
+    node _id_imm_i_sext_T = bits(id_imm_i, 15, 15) @[src/main/scala/micore/Core.scala 124:44]
+    node _id_imm_i_sext_T_1 = mux(_id_imm_i_sext_T, UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 124:31]
+    node id_imm_i_sext = cat(_id_imm_i_sext_T_1, id_imm_i) @[src/main/scala/micore/Core.scala 124:26]
+    node _id_imm_s_T = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 125:29]
+    node _id_imm_s_T_1 = bits(id_inst, 25, 21) @[src/main/scala/micore/Core.scala 125:46]
+    node id_imm_s = cat(_id_imm_s_T, _id_imm_s_T_1) @[src/main/scala/micore/Core.scala 125:21]
+    node _id_imm_s_sext_T = bits(id_imm_s, 9, 9) @[src/main/scala/micore/Core.scala 126:44]
+    node _id_imm_s_sext_T_1 = mux(_id_imm_s_sext_T, UInt<22>("h3fffff"), UInt<22>("h0")) @[src/main/scala/micore/Core.scala 126:31]
+    node id_imm_s_sext = cat(_id_imm_s_sext_T_1, id_imm_s) @[src/main/scala/micore/Core.scala 126:26]
+    node _id_imm_b_T = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 127:29]
+    node id_imm_b = cat(_id_imm_b_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 127:21]
+    node _id_imm_b_sext_T = bits(id_imm_b, 17, 17) @[src/main/scala/micore/Core.scala 128:44]
+    node _id_imm_b_sext_T_1 = mux(_id_imm_b_sext_T, UInt<14>("h3fff"), UInt<14>("h0")) @[src/main/scala/micore/Core.scala 128:31]
+    node id_imm_b_sext = cat(_id_imm_b_sext_T_1, id_imm_b) @[src/main/scala/micore/Core.scala 128:26]
+    node _id_imm_j_T = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 129:29]
+    node id_imm_j = cat(_id_imm_j_T, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 129:21]
+    node _id_imm_j_sext_T = bits(id_imm_j, 25, 25) @[src/main/scala/micore/Core.scala 130:43]
+    node _id_imm_j_sext_T_1 = mux(_id_imm_j_sext_T, UInt<6>("h3f"), UInt<6>("h0")) @[src/main/scala/micore/Core.scala 130:31]
+    node id_imm_j_sext_hi = cat(_id_imm_j_sext_T_1, id_imm_j) @[src/main/scala/micore/Core.scala 130:26]
+    node id_imm_j_sext = cat(id_imm_j_sext_hi, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 130:26]
+    node id_imm_u = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 131:25]
+    node _id_imm_u_shifted_T = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 132:44]
+    node id_imm_u_shifted = cat(id_imm_u, _id_imm_u_shifted_T) @[src/main/scala/micore/Core.scala 132:29]
+    node id_imm_z = bits(id_inst, 15, 11) @[src/main/scala/micore/Core.scala 133:25]
+    node _id_imm_z_uext_T = mux(UInt<1>("h0"), UInt<27>("h7ffffff"), UInt<27>("h0")) @[src/main/scala/micore/Core.scala 134:31]
+    node id_imm_z_uext = cat(_id_imm_z_uext_T, id_imm_z) @[src/main/scala/micore/Core.scala 134:26]
+    node _csignals_T = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_1 = eq(UInt<34>("h230000000"), _csignals_T) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_2 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_2 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_3 = eq(UInt<34>("h2b0000000"), _csignals_T_2) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_4 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_5 = eq(UInt<6>("h20"), _csignals_T_4) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_6 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_6 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_7 = eq(UInt<32>("h80000000"), _csignals_T_6) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_8 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_9 = eq(UInt<6>("h22"), _csignals_T_8) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
@@ -189,285 +240,388 @@ circuit TopOrigin :
     node _csignals_T_13 = eq(UInt<6>("h25"), _csignals_T_12) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_14 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_15 = eq(UInt<6>("h26"), _csignals_T_14) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_16 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_16 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_17 = eq(UInt<32>("hc0000000"), _csignals_T_16) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_18 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_18 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
     node _csignals_T_19 = eq(UInt<32>("hd0000000"), _csignals_T_18) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_20 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_21 = eq(UInt<1>("h0"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_22 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_23 = eq(UInt<2>("h2"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_24 = and(id_inst, UInt<31>("h7ff0003f")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_25 = eq(UInt<2>("h3"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_26 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_27 = eq(UInt<6>("h2a"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_28 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_29 = eq(UInt<31>("h40000000"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_30 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_31 = eq(UInt<31>("h50000000"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_32 = and(id_inst, UInt<32>("hffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_33 = eq(UInt<28>("hc000000"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_34 = and(id_inst, UInt<34>("h3f000ffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_35 = eq(UInt<4>("h8"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_36 = and(id_inst, UInt<33>("h1ffc003ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_37 = eq(UInt<31>("h78000000"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_38 = and(id_inst, UInt<33>("h1ffffffff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_39 = eq(UInt<1>("h0"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
-    node _csignals_T_40 = mux(_csignals_T_39, UInt<5>("h0"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_41 = mux(_csignals_T_37, UInt<5>("h1"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_42 = mux(_csignals_T_35, UInt<5>("he"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_43 = mux(_csignals_T_33, UInt<5>("h1"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_44 = mux(_csignals_T_31, UInt<5>("hc"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_45 = mux(_csignals_T_29, UInt<5>("hb"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_46 = mux(_csignals_T_27, UInt<5>("h9"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_47 = mux(_csignals_T_25, UInt<5>("h8"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_48 = mux(_csignals_T_23, UInt<5>("h7"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_49 = mux(_csignals_T_21, UInt<5>("h6"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_50 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_51 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_52 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_53 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_54 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_55 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_56 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_57 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_58 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_59 = mux(_csignals_T_39, UInt<2>("h2"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_60 = mux(_csignals_T_37, UInt<2>("h2"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_61 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_62 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_63 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_64 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_65 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_66 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_67 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_68 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_69 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_70 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_71 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_72 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_73 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_74 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_75 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_76 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_77 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_1 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_78 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_79 = mux(_csignals_T_37, UInt<3>("h5"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_80 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_81 = mux(_csignals_T_33, UInt<3>("h4"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_82 = mux(_csignals_T_31, UInt<3>("h1"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_83 = mux(_csignals_T_29, UInt<3>("h1"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_84 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_85 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_86 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_87 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_88 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_89 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_90 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_91 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_92 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_93 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_94 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_95 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_96 = mux(_csignals_T_3, UInt<3>("h3"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_97 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_98 = mux(_csignals_T_37, UInt<2>("h0"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_99 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_100 = mux(_csignals_T_33, UInt<2>("h0"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_101 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_102 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_103 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_104 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_105 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_106 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_107 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_108 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_109 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_110 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_111 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_112 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_113 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_114 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_115 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_114) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_115) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_116 = mux(_csignals_T_39, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_117 = mux(_csignals_T_37, UInt<2>("h1"), _csignals_T_116) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_118 = mux(_csignals_T_35, UInt<2>("h0"), _csignals_T_117) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_119 = mux(_csignals_T_33, UInt<2>("h1"), _csignals_T_118) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_120 = mux(_csignals_T_31, UInt<2>("h0"), _csignals_T_119) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_121 = mux(_csignals_T_29, UInt<2>("h0"), _csignals_T_120) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_122 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_121) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_123 = mux(_csignals_T_25, UInt<2>("h1"), _csignals_T_122) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_124 = mux(_csignals_T_23, UInt<2>("h1"), _csignals_T_123) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_125 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_124) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_126 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_125) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_127 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_126) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_128 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_127) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_129 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_128) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_130 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_129) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_131 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_130) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_132 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_131) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_133 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_132) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_134 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_133) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_134) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_135 = mux(_csignals_T_39, UInt<3>("h0"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_136 = mux(_csignals_T_37, UInt<3>("h1"), _csignals_T_135) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_137 = mux(_csignals_T_35, UInt<3>("h0"), _csignals_T_136) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_138 = mux(_csignals_T_33, UInt<3>("h3"), _csignals_T_137) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_139 = mux(_csignals_T_31, UInt<3>("h0"), _csignals_T_138) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_140 = mux(_csignals_T_29, UInt<3>("h0"), _csignals_T_139) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_141 = mux(_csignals_T_27, UInt<3>("h1"), _csignals_T_140) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_142 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_141) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_143 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_142) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_144 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_143) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_145 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_144) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_146 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_145) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_147 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_146) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_148 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_147) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_149 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_148) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_150 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_149) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_151 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_150) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_152 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_151) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _csignals_T_153 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_152) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_153) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
-    node _id_op1_data_T = eq(csignals_1, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 163:16]
-    node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 165:20]
-    node _id_op1_data_T_2 = mux(_id_op1_data_T_1, id_reg_pc, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 165:8]
-    node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_2) @[src/main/scala/micore/Core.scala 162:24]
-    node _id_op2_data_T = bits(id_inst, 25, 25) @[src/main/scala/micore/Core.scala 175:37]
-    node _id_op2_data_T_1 = mux(_id_op2_data_T, UInt<4>("hf"), UInt<4>("h0")) @[src/main/scala/micore/Core.scala 175:26]
-    node _id_op2_data_T_2 = bits(id_inst, 25, 0) @[src/main/scala/micore/Core.scala 175:51]
-    node id_op2_data_hi = cat(_id_op2_data_T_1, _id_op2_data_T_2) @[src/main/scala/micore/Core.scala 175:21]
-    node _id_op2_data_T_3 = cat(id_op2_data_hi, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 175:21]
-    node _id_op2_data_T_4 = bits(id_inst, 15, 0) @[src/main/scala/micore/Core.scala 176:29]
-    node _id_op2_data_T_5 = mux(UInt<1>("h0"), UInt<16>("hffff"), UInt<16>("h0")) @[src/main/scala/micore/Core.scala 176:42]
-    node _id_op2_data_T_6 = cat(_id_op2_data_T_4, _id_op2_data_T_5) @[src/main/scala/micore/Core.scala 176:21]
-    node _id_op2_data_T_7 = eq(UInt<3>("h1"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_8 = mux(_id_op2_data_T_7, id_rs2_data, UInt<32>("h0")) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_9 = eq(UInt<3>("h2"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_10 = mux(_id_op2_data_T_9, id_imm_i_sext, _id_op2_data_T_8) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_11 = eq(UInt<3>("h3"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_12 = mux(_id_op2_data_T_11, id_imm_i_sext, _id_op2_data_T_10) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_13 = eq(UInt<3>("h4"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_14 = mux(_id_op2_data_T_13, _id_op2_data_T_3, _id_op2_data_T_12) @[src/main/scala/micore/Core.scala 170:4]
-    node _id_op2_data_T_15 = eq(UInt<3>("h5"), csignals_2) @[src/main/scala/micore/Core.scala 170:4]
-    node id_op2_data = mux(_id_op2_data_T_15, _id_op2_data_T_6, _id_op2_data_T_14) @[src/main/scala/micore/Core.scala 170:4]
-    node _mem_wb_data_T = add(mem_reg_pc, UInt<32>("h4")) @[src/main/scala/micore/Core.scala 244:28]
-    node _mem_wb_data_T_1 = tail(_mem_wb_data_T, 1) @[src/main/scala/micore/Core.scala 244:28]
-    node _mem_wb_data_T_2 = eq(UInt<3>("h2"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4]
-    node _mem_wb_data_T_3 = mux(_mem_wb_data_T_2, io_dmem_rdata, mem_reg_alu_out) @[src/main/scala/micore/Core.scala 241:4]
-    node _mem_wb_data_T_4 = eq(UInt<3>("h3"), mem_reg_wb_sel) @[src/main/scala/micore/Core.scala 241:4]
-    node mem_wb_data = mux(_mem_wb_data_T_4, _mem_wb_data_T_1, _mem_wb_data_T_3) @[src/main/scala/micore/Core.scala 241:4]
-    node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 254:22]
-    node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 254:33 255:12]
-    node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 254:33 255:12]
-    node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 254:33 255:12 16:28]
-    node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 254:33 255:29]
-    node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 254:33 255:29]
-    node _io_exit_T = eq(id_reg_inst, UInt<32>("hc0000000")) @[src/main/scala/micore/Core.scala 258:27]
-    io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 55:16]
-    io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 234:16]
-    io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 235:15]
-    io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 236:17]
-    io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 258:11]
-    regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 109:16]
-    regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 86:32]
-    regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 109:16]
-    regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 122:16]
-    regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 87:32]
-    regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 122:16]
+    node _csignals_T_20 = and(id_inst, UInt<32>("hfc0007ff")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_21 = eq(UInt<6>("h2a"), _csignals_T_20) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_22 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_23 = eq(UInt<31>("h40000000"), _csignals_T_22) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_24 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_25 = eq(UInt<31>("h50000000"), _csignals_T_24) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_26 = and(id_inst, UInt<34>("h3f0000000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_27 = eq(UInt<30>("h30000000"), _csignals_T_26) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_28 = and(id_inst, UInt<34>("h3ff800000")) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_29 = eq(UInt<32>("hf0000000"), _csignals_T_28) @[src/main/scala/chisel3/util/Lookup.scala 31:38]
+    node _csignals_T_30 = mux(_csignals_T_29, UInt<5>("h1"), UInt<5>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_31 = mux(_csignals_T_27, UInt<5>("h1"), _csignals_T_30) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_32 = mux(_csignals_T_25, UInt<5>("hc"), _csignals_T_31) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_33 = mux(_csignals_T_23, UInt<5>("hb"), _csignals_T_32) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_34 = mux(_csignals_T_21, UInt<5>("h9"), _csignals_T_33) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_35 = mux(_csignals_T_19, UInt<5>("h4"), _csignals_T_34) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_36 = mux(_csignals_T_17, UInt<5>("h3"), _csignals_T_35) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_37 = mux(_csignals_T_15, UInt<5>("h5"), _csignals_T_36) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_38 = mux(_csignals_T_13, UInt<5>("h4"), _csignals_T_37) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_39 = mux(_csignals_T_11, UInt<5>("h3"), _csignals_T_38) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_40 = mux(_csignals_T_9, UInt<5>("h2"), _csignals_T_39) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_41 = mux(_csignals_T_7, UInt<5>("h1"), _csignals_T_40) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_42 = mux(_csignals_T_5, UInt<5>("h1"), _csignals_T_41) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_43 = mux(_csignals_T_3, UInt<5>("h1"), _csignals_T_42) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_0 = mux(_csignals_T_1, UInt<5>("h1"), _csignals_T_43) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_44 = mux(_csignals_T_29, UInt<2>("h2"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_45 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_44) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_46 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_45) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_47 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_46) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_48 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_47) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_49 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_48) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_50 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_49) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_51 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_50) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_52 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_51) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_53 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_52) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_54 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_53) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_55 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_54) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_56 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_55) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_57 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_56) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_1 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_57) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_58 = mux(_csignals_T_29, UInt<3>("h5"), UInt<3>("h1")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_59 = mux(_csignals_T_27, UInt<3>("h4"), _csignals_T_58) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_60 = mux(_csignals_T_25, UInt<3>("h1"), _csignals_T_59) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_61 = mux(_csignals_T_23, UInt<3>("h1"), _csignals_T_60) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_62 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_61) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_63 = mux(_csignals_T_19, UInt<3>("h2"), _csignals_T_62) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_64 = mux(_csignals_T_17, UInt<3>("h2"), _csignals_T_63) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_65 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_64) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_66 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_65) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_67 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_66) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_68 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_67) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_69 = mux(_csignals_T_7, UInt<3>("h2"), _csignals_T_68) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_70 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_69) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_71 = mux(_csignals_T_3, UInt<3>("h3"), _csignals_T_70) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_2 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_71) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_72 = mux(_csignals_T_29, UInt<2>("h0"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_73 = mux(_csignals_T_27, UInt<2>("h0"), _csignals_T_72) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_74 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_73) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_75 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_74) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_76 = mux(_csignals_T_21, UInt<2>("h0"), _csignals_T_75) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_77 = mux(_csignals_T_19, UInt<2>("h0"), _csignals_T_76) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_78 = mux(_csignals_T_17, UInt<2>("h0"), _csignals_T_77) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_79 = mux(_csignals_T_15, UInt<2>("h0"), _csignals_T_78) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_80 = mux(_csignals_T_13, UInt<2>("h0"), _csignals_T_79) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_81 = mux(_csignals_T_11, UInt<2>("h0"), _csignals_T_80) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_82 = mux(_csignals_T_9, UInt<2>("h0"), _csignals_T_81) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_83 = mux(_csignals_T_7, UInt<2>("h0"), _csignals_T_82) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_84 = mux(_csignals_T_5, UInt<2>("h0"), _csignals_T_83) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_85 = mux(_csignals_T_3, UInt<2>("h1"), _csignals_T_84) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_3 = mux(_csignals_T_1, UInt<2>("h0"), _csignals_T_85) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_86 = mux(_csignals_T_29, UInt<2>("h1"), UInt<2>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_87 = mux(_csignals_T_27, UInt<2>("h1"), _csignals_T_86) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_88 = mux(_csignals_T_25, UInt<2>("h0"), _csignals_T_87) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_89 = mux(_csignals_T_23, UInt<2>("h0"), _csignals_T_88) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_90 = mux(_csignals_T_21, UInt<2>("h1"), _csignals_T_89) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_91 = mux(_csignals_T_19, UInt<2>("h1"), _csignals_T_90) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_92 = mux(_csignals_T_17, UInt<2>("h1"), _csignals_T_91) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_93 = mux(_csignals_T_15, UInt<2>("h1"), _csignals_T_92) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_94 = mux(_csignals_T_13, UInt<2>("h1"), _csignals_T_93) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_95 = mux(_csignals_T_11, UInt<2>("h1"), _csignals_T_94) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_96 = mux(_csignals_T_9, UInt<2>("h1"), _csignals_T_95) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_97 = mux(_csignals_T_7, UInt<2>("h1"), _csignals_T_96) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_98 = mux(_csignals_T_5, UInt<2>("h1"), _csignals_T_97) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_99 = mux(_csignals_T_3, UInt<2>("h0"), _csignals_T_98) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_4 = mux(_csignals_T_1, UInt<2>("h1"), _csignals_T_99) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_100 = mux(_csignals_T_29, UInt<3>("h1"), UInt<3>("h0")) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_101 = mux(_csignals_T_27, UInt<3>("h3"), _csignals_T_100) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_102 = mux(_csignals_T_25, UInt<3>("h0"), _csignals_T_101) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_103 = mux(_csignals_T_23, UInt<3>("h0"), _csignals_T_102) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_104 = mux(_csignals_T_21, UInt<3>("h1"), _csignals_T_103) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_105 = mux(_csignals_T_19, UInt<3>("h1"), _csignals_T_104) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_106 = mux(_csignals_T_17, UInt<3>("h1"), _csignals_T_105) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_107 = mux(_csignals_T_15, UInt<3>("h1"), _csignals_T_106) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_108 = mux(_csignals_T_13, UInt<3>("h1"), _csignals_T_107) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_109 = mux(_csignals_T_11, UInt<3>("h1"), _csignals_T_108) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_110 = mux(_csignals_T_9, UInt<3>("h1"), _csignals_T_109) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_111 = mux(_csignals_T_7, UInt<3>("h1"), _csignals_T_110) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_112 = mux(_csignals_T_5, UInt<3>("h1"), _csignals_T_111) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _csignals_T_113 = mux(_csignals_T_3, UInt<3>("h0"), _csignals_T_112) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node csignals_5 = mux(_csignals_T_1, UInt<3>("h2"), _csignals_T_113) @[src/main/scala/chisel3/util/Lookup.scala 34:39]
+    node _id_op1_data_T = eq(csignals_1, UInt<2>("h0")) @[src/main/scala/micore/Core.scala 164:19]
+    node _id_op1_data_T_1 = eq(csignals_1, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 165:19]
+    node _id_op1_data_T_2 = eq(csignals_1, UInt<2>("h3")) @[src/main/scala/micore/Core.scala 166:19]
+    node _id_op1_data_T_3 = mux(_id_op1_data_T_2, id_imm_z_uext, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op1_data_T_4 = mux(_id_op1_data_T_1, id_reg_pc, _id_op1_data_T_3) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_op1_data = mux(_id_op1_data_T, id_rs1_data, _id_op1_data_T_4) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T = eq(csignals_2, UInt<3>("h1")) @[src/main/scala/micore/Core.scala 173:19]
+    node _id_op2_data_T_1 = eq(csignals_2, UInt<3>("h2")) @[src/main/scala/micore/Core.scala 174:19]
+    node _id_op2_data_T_2 = eq(csignals_2, UInt<3>("h3")) @[src/main/scala/micore/Core.scala 175:19]
+    node _id_op2_data_T_3 = eq(csignals_2, UInt<3>("h4")) @[src/main/scala/micore/Core.scala 176:19]
+    node _id_op2_data_T_4 = eq(csignals_2, UInt<3>("h5")) @[src/main/scala/micore/Core.scala 177:19]
+    node _id_op2_data_T_5 = mux(_id_op2_data_T_4, id_imm_u_shifted, UInt<32>("h0")) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T_6 = mux(_id_op2_data_T_3, id_imm_j_sext, _id_op2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T_7 = mux(_id_op2_data_T_2, id_imm_s_sext, _id_op2_data_T_6) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _id_op2_data_T_8 = mux(_id_op2_data_T_1, id_imm_i_sext, _id_op2_data_T_7) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node id_op2_data = mux(_id_op2_data_T, id_rs2_data, _id_op2_data_T_8) @[src/main/scala/chisel3/util/Mux.scala 126:16]
+    node _T = eq(wb_reg_rf_wen, UInt<2>("h1")) @[src/main/scala/micore/Core.scala 268:22]
+    node _GEN_0 = validif(_T, wb_reg_wb_addr) @[src/main/scala/micore/Core.scala 268:{33,42}]
+    node _GEN_1 = validif(_T, clock) @[src/main/scala/micore/Core.scala 268:{33,42}]
+    node _GEN_2 = mux(_T, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Core.scala 16:20 268:{33,42}]
+    node _GEN_3 = validif(_T, UInt<1>("h1")) @[src/main/scala/micore/Core.scala 268:{33,59}]
+    node _GEN_4 = validif(_T, wb_reg_wb_data) @[src/main/scala/micore/Core.scala 268:{33,59}]
+    node _io_exit_T = eq(id_reg_inst, UInt<32>("h114514")) @[src/main/scala/micore/Core.scala 272:27]
+    node _T_1 = asUInt(reset) @[src/main/scala/micore/Core.scala 273:9]
+    node _T_2 = eq(_T_1, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 273:9]
+    node _T_3 = asUInt(reset) @[src/main/scala/micore/Core.scala 275:9]
+    node _T_4 = eq(_T_3, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 275:9]
+    node _T_5 = asUInt(reset) @[src/main/scala/micore/Core.scala 276:9]
+    node _T_6 = eq(_T_5, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 276:9]
+    node _T_7 = asUInt(reset) @[src/main/scala/micore/Core.scala 277:9]
+    node _T_8 = eq(_T_7, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 277:9]
+    node _T_9 = asUInt(reset) @[src/main/scala/micore/Core.scala 278:9]
+    node _T_10 = eq(_T_9, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 278:9]
+    node _T_11 = asUInt(reset) @[src/main/scala/micore/Core.scala 279:9]
+    node _T_12 = eq(_T_11, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 279:9]
+    node _T_13 = asUInt(reset) @[src/main/scala/micore/Core.scala 280:9]
+    node _T_14 = eq(_T_13, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 280:9]
+    node _T_15 = asUInt(reset) @[src/main/scala/micore/Core.scala 281:9]
+    node _T_16 = eq(_T_15, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 281:9]
+    node _T_17 = asUInt(reset) @[src/main/scala/micore/Core.scala 282:9]
+    node _T_18 = eq(_T_17, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 282:9]
+    node _T_19 = asUInt(reset) @[src/main/scala/micore/Core.scala 283:9]
+    node _T_20 = eq(_T_19, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 283:9]
+    node _T_21 = asUInt(reset) @[src/main/scala/micore/Core.scala 284:9]
+    node _T_22 = eq(_T_21, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 284:9]
+    node _T_23 = asUInt(reset) @[src/main/scala/micore/Core.scala 285:9]
+    node _T_24 = eq(_T_23, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 285:9]
+    node _T_25 = asUInt(reset) @[src/main/scala/micore/Core.scala 286:9]
+    node _T_26 = eq(_T_25, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 286:9]
+    node _T_27 = asUInt(reset) @[src/main/scala/micore/Core.scala 287:9]
+    node _T_28 = eq(_T_27, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 287:9]
+    node _T_29 = asUInt(reset) @[src/main/scala/micore/Core.scala 288:9]
+    node _T_30 = eq(_T_29, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 288:9]
+    node _T_31 = asUInt(reset) @[src/main/scala/micore/Core.scala 289:9]
+    node _T_32 = eq(_T_31, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 289:9]
+    node _T_33 = asUInt(reset) @[src/main/scala/micore/Core.scala 290:9]
+    node _T_34 = eq(_T_33, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 290:9]
+    node _T_35 = asUInt(reset) @[src/main/scala/micore/Core.scala 294:9]
+    node _T_36 = eq(_T_35, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 294:9]
+    node _T_37 = asUInt(reset) @[src/main/scala/micore/Core.scala 295:9]
+    node _T_38 = eq(_T_37, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 295:9]
+    node _T_39 = asUInt(reset) @[src/main/scala/micore/Core.scala 296:9]
+    node _T_40 = eq(_T_39, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 296:9]
+    node _T_41 = asUInt(reset) @[src/main/scala/micore/Core.scala 297:9]
+    node _T_42 = eq(_T_41, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 297:9]
+    node _T_43 = asUInt(reset) @[src/main/scala/micore/Core.scala 298:9]
+    node _T_44 = eq(_T_43, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 298:9]
+    node _T_45 = asUInt(reset) @[src/main/scala/micore/Core.scala 299:9]
+    node _T_46 = eq(_T_45, UInt<1>("h0")) @[src/main/scala/micore/Core.scala 299:9]
+    io_imem_addr <= if_reg_pc @[src/main/scala/micore/Core.scala 57:16]
+    io_dmem_addr <= mem_reg_alu_out @[src/main/scala/micore/Core.scala 250:16]
+    io_dmem_wen <= bits(mem_reg_mem_wen, 0, 0) @[src/main/scala/micore/Core.scala 251:15]
+    io_dmem_wdata <= mem_reg_rs2_data @[src/main/scala/micore/Core.scala 252:17]
+    io_exit <= _io_exit_T @[src/main/scala/micore/Core.scala 272:11]
+    io_gp <= regfile.io_gp_MPORT.data @[src/main/scala/micore/Core.scala 271:9]
+    regfile.id_rs1_data_MPORT.addr <= id_rs1_addr @[src/main/scala/micore/Core.scala 107:12]
+    regfile.id_rs1_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 107:12]
+    regfile.id_rs1_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 107:12]
+    regfile.id_rs2_data_MPORT.addr <= id_rs2_addr @[src/main/scala/micore/Core.scala 115:12]
+    regfile.id_rs2_data_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 115:12]
+    regfile.id_rs2_data_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 115:12]
+    regfile.io_gp_MPORT.addr <= UInt<5>("h3") @[src/main/scala/micore/Core.scala 271:19]
+    regfile.io_gp_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Core.scala 271:19]
+    regfile.io_gp_MPORT.clk <= clock @[src/main/scala/micore/Core.scala 271:19]
     regfile.MPORT.addr <= _GEN_0
     regfile.MPORT.en <= _GEN_2
     regfile.MPORT.clk <= _GEN_1
     regfile.MPORT.data <= _GEN_4
     regfile.MPORT.mask <= _GEN_3
-    id_reg_pc <= _id_reg_pc_T @[src/main/scala/micore/Core.scala 76:13]
-    id_reg_inst <= _id_reg_inst_T_2 @[src/main/scala/micore/Core.scala 77:15]
-    exe_reg_pc <= id_reg_pc @[src/main/scala/micore/Core.scala 181:14]
-    exe_reg_wb_addr <= id_wb_addr @[src/main/scala/micore/Core.scala 185:19]
-    exe_reg_op1_data <= id_op1_data @[src/main/scala/micore/Core.scala 182:20]
-    exe_reg_op2_data <= id_op2_data @[src/main/scala/micore/Core.scala 183:20]
-    exe_reg_rs2_data <= id_rs2_data @[src/main/scala/micore/Core.scala 184:20]
-    exe_reg_exe_fun <= csignals_0 @[src/main/scala/micore/Core.scala 190:19]
-    exe_reg_mem_wen <= csignals_3 @[src/main/scala/micore/Core.scala 187:19]
-    exe_reg_rf_wen <= csignals_4 @[src/main/scala/micore/Core.scala 188:18]
-    exe_reg_wb_sel <= csignals_5 @[src/main/scala/micore/Core.scala 186:18]
-    exe_reg_imm_b_sext <= id_imm_b_sext @[src/main/scala/micore/Core.scala 189:22]
-    mem_reg_pc <= exe_reg_pc @[src/main/scala/micore/Core.scala 225:14]
-    mem_reg_wb_addr <= exe_reg_wb_addr @[src/main/scala/micore/Core.scala 226:19]
-    mem_reg_alu_out <= exe_alu_out @[src/main/scala/micore/Core.scala 227:19]
-    mem_reg_rs2_data <= exe_reg_rs2_data @[src/main/scala/micore/Core.scala 228:20]
-    mem_reg_rf_wen <= exe_reg_rf_wen @[src/main/scala/micore/Core.scala 229:18]
-    mem_reg_wb_sel <= exe_reg_wb_sel @[src/main/scala/micore/Core.scala 230:18]
-    mem_reg_mem_wen <= exe_reg_mem_wen @[src/main/scala/micore/Core.scala 231:19]
-    wb_reg_wb_addr <= mem_reg_wb_addr @[src/main/scala/micore/Core.scala 249:18]
-    wb_reg_rf_wen <= mem_reg_rf_wen @[src/main/scala/micore/Core.scala 250:17]
-    wb_reg_wb_data <= mem_wb_data @[src/main/scala/micore/Core.scala 251:18]
-    if_reg_pc <= mux(reset, UInt<32>("h0"), if_pc_next) @[src/main/scala/micore/Core.scala 54:{26,26} 73:13]
+    id_reg_pc <= mux(reset, UInt<32>("h0"), _id_reg_pc_T) @[src/main/scala/micore/Core.scala 20:{26,26} 78:13]
+    id_reg_inst <= mux(reset, UInt<32>("h0"), _id_reg_inst_T_2) @[src/main/scala/micore/Core.scala 21:{28,28} 79:15]
+    exe_reg_pc <= mux(reset, UInt<32>("h0"), id_reg_pc) @[src/main/scala/micore/Core.scala 182:14 24:{27,27}]
+    exe_reg_wb_addr <= mux(reset, UInt<5>("h0"), id_wb_addr) @[src/main/scala/micore/Core.scala 186:19 25:{32,32}]
+    exe_reg_op1_data <= mux(reset, UInt<32>("h0"), id_op1_data) @[src/main/scala/micore/Core.scala 183:20 26:{33,33}]
+    exe_reg_op2_data <= bits(mux(reset, UInt<32>("h0"), id_op2_data), 31, 0) @[src/main/scala/micore/Core.scala 184:20 27:{33,33}]
+    exe_reg_rs2_data <= mux(reset, UInt<32>("h0"), id_rs2_data) @[src/main/scala/micore/Core.scala 185:20 28:{33,33}]
+    exe_reg_exe_fun <= mux(reset, UInt<5>("h0"), csignals_0) @[src/main/scala/micore/Core.scala 195:19 29:{32,32}]
+    exe_reg_mem_wen <= mux(reset, UInt<2>("h0"), csignals_3) @[src/main/scala/micore/Core.scala 188:19 30:{32,32}]
+    exe_reg_rf_wen <= mux(reset, UInt<2>("h0"), csignals_4) @[src/main/scala/micore/Core.scala 189:18 31:{31,31}]
+    exe_reg_wb_sel <= mux(reset, UInt<3>("h0"), csignals_5) @[src/main/scala/micore/Core.scala 187:18 32:{31,31}]
+    exe_reg_imm_i_sext <= mux(reset, UInt<32>("h0"), id_imm_i_sext) @[src/main/scala/micore/Core.scala 190:22 33:{35,35}]
+    exe_reg_imm_s_sext <= mux(reset, UInt<32>("h0"), id_imm_s_sext) @[src/main/scala/micore/Core.scala 191:22 34:{35,35}]
+    exe_reg_imm_b_sext <= mux(reset, UInt<32>("h0"), id_imm_b_sext) @[src/main/scala/micore/Core.scala 192:22 35:{35,35}]
+    exe_reg_imm_u_shifted <= mux(reset, UInt<32>("h0"), id_imm_u_shifted) @[src/main/scala/micore/Core.scala 193:25 36:{38,38}]
+    exe_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), id_imm_z_uext) @[src/main/scala/micore/Core.scala 194:22 37:{35,35}]
+    mem_reg_pc <= mux(reset, UInt<32>("h0"), exe_reg_pc) @[src/main/scala/micore/Core.scala 239:14 40:{27,27}]
+    mem_reg_wb_addr <= mux(reset, UInt<5>("h0"), exe_reg_wb_addr) @[src/main/scala/micore/Core.scala 242:19 41:{32,32}]
+    mem_reg_op1_data <= mux(reset, UInt<32>("h0"), exe_reg_op1_data) @[src/main/scala/micore/Core.scala 240:20 42:{33,33}]
+    mem_reg_rs2_data <= mux(reset, UInt<32>("h0"), exe_reg_rs2_data) @[src/main/scala/micore/Core.scala 241:20 43:{33,33}]
+    mem_reg_mem_wen <= mux(reset, UInt<2>("h0"), exe_reg_mem_wen) @[src/main/scala/micore/Core.scala 247:19 44:{32,32}]
+    mem_reg_rf_wen <= mux(reset, UInt<2>("h0"), exe_reg_rf_wen) @[src/main/scala/micore/Core.scala 244:18 45:{31,31}]
+    mem_reg_wb_sel <= mux(reset, UInt<3>("h0"), exe_reg_wb_sel) @[src/main/scala/micore/Core.scala 245:18 46:{31,31}]
+    mem_reg_imm_z_uext <= mux(reset, UInt<32>("h0"), exe_reg_imm_z_uext) @[src/main/scala/micore/Core.scala 246:22 47:{35,35}]
+    mem_reg_alu_out <= mux(reset, UInt<32>("h0"), exe_alu_out) @[src/main/scala/micore/Core.scala 243:19 48:{32,32}]
+    wb_reg_wb_addr <= mux(reset, UInt<5>("h0"), mem_reg_wb_addr) @[src/main/scala/micore/Core.scala 265:18 51:{31,31}]
+    wb_reg_rf_wen <= mux(reset, UInt<2>("h0"), mem_reg_rf_wen) @[src/main/scala/micore/Core.scala 264:17 52:{30,30}]
+    wb_reg_wb_data <= mux(reset, UInt<32>("h0"), mem_wb_data) @[src/main/scala/micore/Core.scala 263:18 53:{31,31}]
+    if_reg_pc <= mux(reset, UInt<32>("h400000"), if_pc_next) @[src/main/scala/micore/Core.scala 56:{26,26} 75:13]
+    printf(clock, and(and(UInt<1>("h1"), _T_2), UInt<1>("h1")), "---------------------\n") : printf @[src/main/scala/micore/Core.scala 273:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_4), UInt<1>("h1")), "id_reg_pc: 0x%x\n", id_reg_pc) : printf_1 @[src/main/scala/micore/Core.scala 275:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_6), UInt<1>("h1")), "id_reg_inst: 0x%x\n", id_reg_inst) : printf_2 @[src/main/scala/micore/Core.scala 276:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_8), UInt<1>("h1")), "id_inst: 0x%x\n", id_inst) : printf_3 @[src/main/scala/micore/Core.scala 277:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_10), UInt<1>("h1")), "id_rs1_addr: 0x%x\n", id_rs1_addr) : printf_4 @[src/main/scala/micore/Core.scala 278:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_12), UInt<1>("h1")), "id_rs2_addr: 0x%x\n", id_rs2_addr) : printf_5 @[src/main/scala/micore/Core.scala 279:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_14), UInt<1>("h1")), "id_wb_addr: 0x%x\n", id_wb_addr) : printf_6 @[src/main/scala/micore/Core.scala 280:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_16), UInt<1>("h1")), "id_exe_fun: 0x%x\n", csignals_0) : printf_7 @[src/main/scala/micore/Core.scala 281:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_18), UInt<1>("h1")), "id_op1_sel: 0x%x\n", csignals_1) : printf_8 @[src/main/scala/micore/Core.scala 282:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_20), UInt<1>("h1")), "id_op1_data: 0x%x\n", id_op1_data) : printf_9 @[src/main/scala/micore/Core.scala 283:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_22), UInt<1>("h1")), "id_op2_sel: 0x%x\n", csignals_2) : printf_10 @[src/main/scala/micore/Core.scala 284:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_24), UInt<1>("h1")), "id_op2_data: 0x%x\n", id_op2_data) : printf_11 @[src/main/scala/micore/Core.scala 285:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_26), UInt<1>("h1")), "id_mem_wen: 0x%x\n", csignals_3) : printf_12 @[src/main/scala/micore/Core.scala 286:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_28), UInt<1>("h1")), "id_rf_wen: 0x%x\n", csignals_4) : printf_13 @[src/main/scala/micore/Core.scala 287:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_30), UInt<1>("h1")), "id_wb_sel: 0x%x\n", csignals_5) : printf_14 @[src/main/scala/micore/Core.scala 288:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_32), UInt<1>("h1")), "id_rs1_data: 0x%x\n", id_rs1_data) : printf_15 @[src/main/scala/micore/Core.scala 289:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_34), UInt<1>("h1")), "id_rs2_data: 0x%x\n", id_rs2_data) : printf_16 @[src/main/scala/micore/Core.scala 290:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_36), UInt<1>("h1")), "exe_alu_out: 0x%x\n", exe_alu_out) : printf_17 @[src/main/scala/micore/Core.scala 294:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_38), UInt<1>("h1")), "mem_reg_pc: 0x%x\n", mem_reg_pc) : printf_18 @[src/main/scala/micore/Core.scala 295:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_40), UInt<1>("h1")), "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out) : printf_19 @[src/main/scala/micore/Core.scala 296:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_42), UInt<1>("h1")), "mem_wb_data: 0x%x\n", mem_wb_data) : printf_20 @[src/main/scala/micore/Core.scala 297:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_44), UInt<1>("h1")), "wb_reg_wb_data: 0%x\n", wb_reg_wb_data) : printf_21 @[src/main/scala/micore/Core.scala 298:9]
+    printf(clock, and(and(UInt<1>("h1"), _T_46), UInt<1>("h1")), "---------------------\n") : printf_22 @[src/main/scala/micore/Core.scala 299:9]
 
-  module Memory : @[src/main/scala/micore/Memory.scala 20:7]
-    input clock : Clock @[src/main/scala/micore/Memory.scala 20:7]
-    input reset : UInt<1> @[src/main/scala/micore/Memory.scala 20:7]
-    input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
-    output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
-    input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
-    output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
-    input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 21:14]
-    input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 21:14]
+  module Memory : @[src/main/scala/micore/Memory.scala 25:7]
+    input clock : Clock @[src/main/scala/micore/Memory.scala 25:7]
+    input reset : UInt<1> @[src/main/scala/micore/Memory.scala 25:7]
+    input io_imem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 26:14]
+    output io_imem_inst : UInt<32> @[src/main/scala/micore/Memory.scala 26:14]
+    input io_dmem_addr : UInt<32> @[src/main/scala/micore/Memory.scala 26:14]
+    output io_dmem_rdata : UInt<32> @[src/main/scala/micore/Memory.scala 26:14]
+    input io_dmem_wen : UInt<1> @[src/main/scala/micore/Memory.scala 26:14]
+    input io_dmem_wdata : UInt<32> @[src/main/scala/micore/Memory.scala 26:14]
 
-    mem mem : @[src/main/scala/micore/Memory.scala 27:24]
-      data-type => UInt<32>
-      depth => 512
-      read-latency => 1
+    mem mem : @[src/main/scala/micore/Memory.scala 32:16]
+      data-type => UInt<8>
+      depth => 4096
+      read-latency => 0
       write-latency => 1
       reader => io_imem_inst_MPORT
+      reader => io_imem_inst_MPORT_1
+      reader => io_imem_inst_MPORT_2
+      reader => io_imem_inst_MPORT_3
       reader => io_dmem_rdata_MPORT
+      reader => io_dmem_rdata_MPORT_1
+      reader => io_dmem_rdata_MPORT_2
+      reader => io_dmem_rdata_MPORT_3
       writer => MPORT
+      writer => MPORT_1
+      writer => MPORT_2
+      writer => MPORT_3
       read-under-write => undefined
-    node _io_imem_inst_T = shr(io_imem_addr, 2) @[src/main/scala/micore/Memory.scala 31:41]
-    node _GEN_0 = validif(UInt<1>("h1"), _io_imem_inst_T) @[src/main/scala/micore/Memory.scala 31:{27,27}]
-    node _io_imem_inst_WIRE = _GEN_0 @[src/main/scala/micore/Memory.scala 31:27]
-    node _io_imem_inst_T_1 = bits(_io_imem_inst_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 31:27]
-    node _GEN_1 = mux(UInt<1>("h1"), UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 27:24 31:{27,27}]
-    node _GEN_2 = validif(UInt<1>("h1"), _io_imem_inst_T_1) @[src/main/scala/micore/Memory.scala 31:{27,27}]
-    node _GEN_3 = validif(UInt<1>("h1"), clock) @[src/main/scala/micore/Memory.scala 31:{27,27}]
-    node _io_dmem_rdata_T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 33:42]
-    node _GEN_4 = validif(UInt<1>("h1"), _io_dmem_rdata_T) @[src/main/scala/micore/Memory.scala 33:{28,28}]
-    node _io_dmem_rdata_WIRE = _GEN_4 @[src/main/scala/micore/Memory.scala 33:28]
-    node _io_dmem_rdata_T_1 = bits(_io_dmem_rdata_WIRE, 8, 0) @[src/main/scala/micore/Memory.scala 33:28]
-    node _GEN_5 = validif(UInt<1>("h1"), _io_dmem_rdata_T_1) @[src/main/scala/micore/Memory.scala 33:{28,28}]
-    node _T = shr(io_dmem_addr, 2) @[src/main/scala/micore/Memory.scala 36:28]
-    node _T_1 = bits(_T, 8, 0) @[src/main/scala/micore/Memory.scala 36:14]
-    node _GEN_6 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 35:21 36:14]
-    node _GEN_7 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 35:21 36:14]
-    node _GEN_8 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 35:21 36:14 27:24]
-    node _GEN_9 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 35:21 36:14]
-    node _GEN_10 = validif(io_dmem_wen, io_dmem_wdata) @[src/main/scala/micore/Memory.scala 35:21 36:14]
-    io_imem_inst <= mem.io_imem_inst_MPORT.data @[src/main/scala/micore/Memory.scala 31:16]
-    io_dmem_rdata <= mem.io_dmem_rdata_MPORT.data @[src/main/scala/micore/Memory.scala 33:17]
-    mem.io_imem_inst_MPORT.addr <= _GEN_2
-    mem.io_imem_inst_MPORT.en <= _GEN_1
-    mem.io_imem_inst_MPORT.clk <= _GEN_3
-    mem.io_dmem_rdata_MPORT.addr <= _GEN_5
-    mem.io_dmem_rdata_MPORT.en <= _GEN_1
-    mem.io_dmem_rdata_MPORT.clk <= _GEN_3
-    mem.MPORT.addr <= _GEN_6
-    mem.MPORT.en <= _GEN_8
-    mem.MPORT.clk <= _GEN_7
-    mem.MPORT.data <= _GEN_10
-    mem.MPORT.mask <= _GEN_9
+    node _io_imem_inst_T = add(io_imem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 39:22]
+    node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[src/main/scala/micore/Memory.scala 39:22]
+    node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 39:8]
+    node _io_imem_inst_T_3 = add(io_imem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 40:22]
+    node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[src/main/scala/micore/Memory.scala 40:22]
+    node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 40:8]
+    node _io_imem_inst_T_6 = add(io_imem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 41:22]
+    node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[src/main/scala/micore/Memory.scala 41:22]
+    node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 41:8]
+    node _io_imem_inst_T_9 = bits(io_imem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 42:8]
+    node io_imem_inst_lo = cat(mem.io_imem_inst_MPORT_2.data, mem.io_imem_inst_MPORT_3.data) @[src/main/scala/micore/Memory.scala 38:22]
+    node io_imem_inst_hi = cat(mem.io_imem_inst_MPORT.data, mem.io_imem_inst_MPORT_1.data) @[src/main/scala/micore/Memory.scala 38:22]
+    node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[src/main/scala/micore/Memory.scala 38:22]
+    node _io_dmem_rdata_T = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 47:22]
+    node _io_dmem_rdata_T_1 = tail(_io_dmem_rdata_T, 1) @[src/main/scala/micore/Memory.scala 47:22]
+    node _io_dmem_rdata_T_2 = bits(_io_dmem_rdata_T_1, 11, 0) @[src/main/scala/micore/Memory.scala 47:8]
+    node _io_dmem_rdata_T_3 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 48:22]
+    node _io_dmem_rdata_T_4 = tail(_io_dmem_rdata_T_3, 1) @[src/main/scala/micore/Memory.scala 48:22]
+    node _io_dmem_rdata_T_5 = bits(_io_dmem_rdata_T_4, 11, 0) @[src/main/scala/micore/Memory.scala 48:8]
+    node _io_dmem_rdata_T_6 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 49:22]
+    node _io_dmem_rdata_T_7 = tail(_io_dmem_rdata_T_6, 1) @[src/main/scala/micore/Memory.scala 49:22]
+    node _io_dmem_rdata_T_8 = bits(_io_dmem_rdata_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 49:8]
+    node _io_dmem_rdata_T_9 = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 50:8]
+    node io_dmem_rdata_lo = cat(mem.io_dmem_rdata_MPORT_2.data, mem.io_dmem_rdata_MPORT_3.data) @[src/main/scala/micore/Memory.scala 46:23]
+    node io_dmem_rdata_hi = cat(mem.io_dmem_rdata_MPORT.data, mem.io_dmem_rdata_MPORT_1.data) @[src/main/scala/micore/Memory.scala 46:23]
+    node _io_dmem_rdata_T_10 = cat(io_dmem_rdata_hi, io_dmem_rdata_lo) @[src/main/scala/micore/Memory.scala 46:23]
+    node _T = bits(io_dmem_addr, 11, 0) @[src/main/scala/micore/Memory.scala 55:8]
+    node _T_1 = bits(io_dmem_wdata, 7, 0) @[src/main/scala/micore/Memory.scala 55:39]
+    node _T_2 = add(io_dmem_addr, UInt<32>("h1")) @[src/main/scala/micore/Memory.scala 56:22]
+    node _T_3 = tail(_T_2, 1) @[src/main/scala/micore/Memory.scala 56:22]
+    node _T_4 = bits(_T_3, 11, 0) @[src/main/scala/micore/Memory.scala 56:8]
+    node _T_5 = bits(io_dmem_wdata, 15, 8) @[src/main/scala/micore/Memory.scala 56:57]
+    node _T_6 = add(io_dmem_addr, UInt<32>("h2")) @[src/main/scala/micore/Memory.scala 57:22]
+    node _T_7 = tail(_T_6, 1) @[src/main/scala/micore/Memory.scala 57:22]
+    node _T_8 = bits(_T_7, 11, 0) @[src/main/scala/micore/Memory.scala 57:8]
+    node _T_9 = bits(io_dmem_wdata, 23, 16) @[src/main/scala/micore/Memory.scala 57:57]
+    node _T_10 = add(io_dmem_addr, UInt<32>("h3")) @[src/main/scala/micore/Memory.scala 58:22]
+    node _T_11 = tail(_T_10, 1) @[src/main/scala/micore/Memory.scala 58:22]
+    node _T_12 = bits(_T_11, 11, 0) @[src/main/scala/micore/Memory.scala 58:8]
+    node _T_13 = bits(io_dmem_wdata, 31, 24) @[src/main/scala/micore/Memory.scala 58:57]
+    node _GEN_0 = validif(io_dmem_wen, _T) @[src/main/scala/micore/Memory.scala 54:21 55:8]
+    node _GEN_1 = validif(io_dmem_wen, clock) @[src/main/scala/micore/Memory.scala 54:21 55:8]
+    node _GEN_2 = mux(io_dmem_wen, UInt<1>("h1"), UInt<1>("h0")) @[src/main/scala/micore/Memory.scala 32:16 54:21 55:8]
+    node _GEN_3 = validif(io_dmem_wen, UInt<1>("h1")) @[src/main/scala/micore/Memory.scala 54:21 55:23]
+    node _GEN_4 = validif(io_dmem_wen, _T_1) @[src/main/scala/micore/Memory.scala 54:21 55:23]
+    node _GEN_5 = validif(io_dmem_wen, _T_4) @[src/main/scala/micore/Memory.scala 54:21 56:8]
+    node _GEN_6 = validif(io_dmem_wen, _T_5) @[src/main/scala/micore/Memory.scala 54:21 56:41]
+    node _GEN_7 = validif(io_dmem_wen, _T_8) @[src/main/scala/micore/Memory.scala 54:21 57:8]
+    node _GEN_8 = validif(io_dmem_wen, _T_9) @[src/main/scala/micore/Memory.scala 54:21 57:41]
+    node _GEN_9 = validif(io_dmem_wen, _T_12) @[src/main/scala/micore/Memory.scala 54:21 58:8]
+    node _GEN_10 = validif(io_dmem_wen, _T_13) @[src/main/scala/micore/Memory.scala 54:21 58:41]
+    io_imem_inst <= _io_imem_inst_T_10 @[src/main/scala/micore/Memory.scala 38:16]
+    io_dmem_rdata <= _io_dmem_rdata_T_10 @[src/main/scala/micore/Memory.scala 46:17]
+    mem.io_imem_inst_MPORT.addr <= _io_imem_inst_T_2 @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_imem_inst_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_imem_inst_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 39:8]
+    mem.io_imem_inst_MPORT_1.addr <= _io_imem_inst_T_5 @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_imem_inst_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_imem_inst_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 40:8]
+    mem.io_imem_inst_MPORT_2.addr <= _io_imem_inst_T_8 @[src/main/scala/micore/Memory.scala 41:8]
+    mem.io_imem_inst_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 41:8]
+    mem.io_imem_inst_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 41:8]
+    mem.io_imem_inst_MPORT_3.addr <= _io_imem_inst_T_9 @[src/main/scala/micore/Memory.scala 42:8]
+    mem.io_imem_inst_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 42:8]
+    mem.io_imem_inst_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 42:8]
+    mem.io_dmem_rdata_MPORT.addr <= _io_dmem_rdata_T_2 @[src/main/scala/micore/Memory.scala 47:8]
+    mem.io_dmem_rdata_MPORT.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 47:8]
+    mem.io_dmem_rdata_MPORT.clk <= clock @[src/main/scala/micore/Memory.scala 47:8]
+    mem.io_dmem_rdata_MPORT_1.addr <= _io_dmem_rdata_T_5 @[src/main/scala/micore/Memory.scala 48:8]
+    mem.io_dmem_rdata_MPORT_1.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 48:8]
+    mem.io_dmem_rdata_MPORT_1.clk <= clock @[src/main/scala/micore/Memory.scala 48:8]
+    mem.io_dmem_rdata_MPORT_2.addr <= _io_dmem_rdata_T_8 @[src/main/scala/micore/Memory.scala 49:8]
+    mem.io_dmem_rdata_MPORT_2.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 49:8]
+    mem.io_dmem_rdata_MPORT_2.clk <= clock @[src/main/scala/micore/Memory.scala 49:8]
+    mem.io_dmem_rdata_MPORT_3.addr <= _io_dmem_rdata_T_9 @[src/main/scala/micore/Memory.scala 50:8]
+    mem.io_dmem_rdata_MPORT_3.en <= UInt<1>("h1") @[src/main/scala/micore/Memory.scala 50:8]
+    mem.io_dmem_rdata_MPORT_3.clk <= clock @[src/main/scala/micore/Memory.scala 50:8]
+    mem.MPORT.addr <= _GEN_0
+    mem.MPORT.en <= _GEN_2
+    mem.MPORT.clk <= _GEN_1
+    mem.MPORT.data <= _GEN_4
+    mem.MPORT.mask <= _GEN_3
+    mem.MPORT_1.addr <= _GEN_5
+    mem.MPORT_1.en <= _GEN_2
+    mem.MPORT_1.clk <= _GEN_1
+    mem.MPORT_1.data <= _GEN_6
+    mem.MPORT_1.mask <= _GEN_3
+    mem.MPORT_2.addr <= _GEN_7
+    mem.MPORT_2.en <= _GEN_2
+    mem.MPORT_2.clk <= _GEN_1
+    mem.MPORT_2.data <= _GEN_8
+    mem.MPORT_2.mask <= _GEN_3
+    mem.MPORT_3.addr <= _GEN_9
+    mem.MPORT_3.en <= _GEN_2
+    mem.MPORT_3.clk <= _GEN_1
+    mem.MPORT_3.data <= _GEN_10
+    mem.MPORT_3.mask <= _GEN_3
 
   module TopOrigin : @[src/main/scala/micore/Top.scala 8:7]
     input clock : Clock @[src/main/scala/micore/Top.scala 8:7]
     input reset : UInt<1> @[src/main/scala/micore/Top.scala 8:7]
     output io_exit : UInt<1> @[src/main/scala/micore/Top.scala 9:14]
+    output io_gp : UInt<32> @[src/main/scala/micore/Top.scala 9:14]
 
-    inst core of Core @[src/main/scala/micore/Top.scala 12:20]
-    inst memory of Memory @[src/main/scala/micore/Top.scala 13:22]
-    io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 18:11]
+    inst core of Core @[src/main/scala/micore/Top.scala 13:20]
+    inst memory of Memory @[src/main/scala/micore/Top.scala 14:22]
+    io_exit <= core.io_exit @[src/main/scala/micore/Top.scala 17:11]
+    io_gp <= core.io_gp @[src/main/scala/micore/Top.scala 18:9]
     core.clock <= clock
     core.reset <= reset
     core.io_imem_inst <= memory.io_imem_inst @[src/main/scala/micore/Top.scala 15:16]