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Add mem.hex and Fix some bugs

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CGH0S7
2024-12-27 13:53:58 +08:00
parent 7f695e27ac
commit ec0fd8812f
53 changed files with 680 additions and 91 deletions
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// Generated by CIRCT firtool-1.62.0
// VCS coverage exclude_file
module regfile_32x32(
input [4:0] R0_addr,
input R0_en,
R0_clk,
output [31:0] R0_data,
input [4:0] R1_addr,
input R1_en,
R1_clk,
output [31:0] R1_data,
input [4:0] W0_addr,
input W0_en,
W0_clk,
input [31:0] W0_data
);
reg [31:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
endmodule
module Core(
input clock,
reset,
output [31:0] io_imem_addr,
input [31:0] io_imem_inst,
output [31:0] io_dmem_addr,
input [31:0] io_dmem_rdata,
output io_dmem_wen,
output [31:0] io_dmem_wdata,
output io_exit
);
wire exe_jmp_flg;
wire exe_br_flg;
wire [31:0] _regfile_ext_R0_data;
wire [31:0] _regfile_ext_R1_data;
reg [31:0] id_reg_pc;
reg [31:0] id_reg_inst;
reg [31:0] exe_reg_pc;
reg [4:0] exe_reg_wb_addr;
reg [31:0] exe_reg_op1_data;
reg [31:0] exe_reg_op2_data;
reg [31:0] exe_reg_rs2_data;
reg [4:0] exe_reg_exe_fun;
reg [1:0] exe_reg_mem_wen;
reg [1:0] exe_reg_rf_wen;
reg [2:0] exe_reg_wb_sel;
reg [31:0] exe_reg_imm_b_sext;
reg [31:0] mem_reg_pc;
reg [4:0] mem_reg_wb_addr;
reg [31:0] mem_reg_rs2_data;
reg [1:0] mem_reg_mem_wen;
reg [1:0] mem_reg_rf_wen;
reg [2:0] mem_reg_wb_sel;
reg [31:0] mem_reg_alu_out;
reg [4:0] wb_reg_wb_addr;
reg [1:0] wb_reg_rf_wen;
reg [31:0] wb_reg_wb_data;
reg [31:0] if_reg_pc;
wire _id_inst_T = exe_br_flg | exe_jmp_flg;
wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
wire stall_flg =
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
assign exe_br_flg =
exe_reg_exe_fun == 5'hB
? exe_reg_op1_data == exe_reg_op2_data
: exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
wire [31:0] mem_wb_data =
mem_reg_wb_sel == 3'h2
? io_dmem_rdata
: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
always @(posedge clock) begin
if (reset) begin
id_reg_pc <= 32'h0;
id_reg_inst <= 32'h0;
exe_reg_pc <= 32'h0;
exe_reg_wb_addr <= 5'h0;
exe_reg_op1_data <= 32'h0;
exe_reg_op2_data <= 32'h0;
exe_reg_rs2_data <= 32'h0;
exe_reg_exe_fun <= 5'h0;
exe_reg_mem_wen <= 2'h0;
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
exe_reg_imm_b_sext <= 32'h0;
mem_reg_pc <= 32'h0;
mem_reg_wb_addr <= 5'h0;
mem_reg_rs2_data <= 32'h0;
mem_reg_mem_wen <= 2'h0;
mem_reg_rf_wen <= 2'h0;
mem_reg_wb_sel <= 3'h0;
mem_reg_alu_out <= 32'h0;
wb_reg_wb_addr <= 5'h0;
wb_reg_rf_wen <= 2'h0;
wb_reg_wb_data <= 32'h0;
if_reg_pc <= 32'h0;
end
else begin
automatic logic _id_rs2_data_T_2;
automatic logic [31:0] id_rs2_data;
automatic logic [16:0] _GEN = {id_inst[31:26], id_inst[10:0]};
automatic logic _csignals_T_5 = _GEN == 17'h20;
automatic logic [19:0] _GEN_0 = {id_inst[31:28], id_inst[15:0]};
automatic logic _csignals_T_7 = _GEN_0 == 20'h80000;
automatic logic _csignals_T_9;
automatic logic _csignals_T_11;
automatic logic _csignals_T_13;
automatic logic _csignals_T_15;
automatic logic _csignals_T_17;
automatic logic _csignals_T_19;
automatic logic [16:0] _GEN_1 = {id_inst[30:20], id_inst[5:0]};
automatic logic _csignals_T_21;
automatic logic _csignals_T_23;
automatic logic _csignals_T_25;
automatic logic _csignals_T_27;
automatic logic _csignals_T_29;
automatic logic _csignals_T_31;
automatic logic _csignals_T_33;
automatic logic _csignals_T_35;
automatic logic _csignals_T_37;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic [1:0] csignals_1;
automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
automatic logic [62:0] _exe_alu_out_T_14 =
{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
automatic logic [31:0] exe_alu_out;
automatic logic [7:0][31:0] _GEN_5;
_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
id_rs2_data =
id_inst[20:16] == 5'h0
? 32'h0
: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
? mem_wb_data
: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
? wb_reg_wb_data
: _regfile_ext_R0_data;
_csignals_T_9 = _GEN == 17'h22;
_csignals_T_11 = _GEN == 17'h24;
_csignals_T_13 = _GEN == 17'h25;
_csignals_T_15 = _GEN == 17'h26;
_csignals_T_17 = _GEN_0 == 20'hC0000;
_csignals_T_19 = _GEN_0 == 20'hD0000;
_csignals_T_21 = _GEN_1 == 17'h0;
_csignals_T_23 = _GEN_1 == 17'h2;
_csignals_T_25 = _GEN_1 == 17'h3;
_csignals_T_27 = _GEN == 17'h2A;
_csignals_T_29 = _GEN_0 == 20'h40000;
_csignals_T_31 = _GEN_0 == 20'h50000;
_csignals_T_33 = id_inst == 32'hC000000;
_csignals_T_35 = _GEN_0 == 20'h8;
_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
_GEN_2 = _csignals_T_29 | _csignals_T_31;
_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
? 2'h0
: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
exe_alu_out =
exe_reg_exe_fun == 5'h1
? exe_reg_op1_data + exe_reg_op2_data
: exe_reg_exe_fun == 5'h2
? exe_reg_op1_data - exe_reg_op2_data
: exe_reg_exe_fun == 5'h3
? exe_reg_op1_data & exe_reg_op2_data
: exe_reg_exe_fun == 5'h4
? exe_reg_op1_data | exe_reg_op2_data
: exe_reg_exe_fun == 5'h5
? exe_reg_op1_data ^ exe_reg_op2_data
: exe_reg_exe_fun == 5'h6
? _exe_alu_out_T_14[31:0]
: exe_reg_exe_fun == 5'h7
? exe_reg_op1_data >> _GEN_4
: exe_reg_exe_fun == 5'h8
? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
: exe_reg_exe_fun == 5'h9
? {31'h0,
$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
: exe_reg_exe_fun == 5'hE
? exe_reg_op1_data
: 32'h0;
if (~stall_flg)
id_reg_pc <= if_reg_pc;
if (_id_inst_T)
id_reg_inst <= 32'h0;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_inst[15:11];
if (csignals_1 == 2'h0) begin
if (id_inst[25:21] == 5'h0)
exe_reg_op1_data <= 32'h0;
else if (id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2)
exe_reg_op1_data <= mem_wb_data;
else if (id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5)
exe_reg_op1_data <= wb_reg_wb_data;
else
exe_reg_op1_data <= _regfile_ext_R1_data;
end
else if (csignals_1 == 2'h1)
exe_reg_op1_data <= id_reg_pc;
else
exe_reg_op1_data <= 32'h0;
_GEN_5 =
{{32'h0},
{32'h0},
{{id_inst[15:0], 16'h0}},
{{{4{id_inst[25]}}, id_inst[25:0], 2'h0}},
{{{16{id_inst[15]}}, id_inst[15:0]}},
{{{16{id_inst[15]}}, id_inst[15:0]}},
{id_rs2_data},
{32'h0}};
exe_reg_op2_data <=
_GEN_5[_csignals_T_5
? 3'h1
: _csignals_T_7
? 3'h2
: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
? 3'h1
: _csignals_T_17 | _csignals_T_19
? 3'h2
: _GEN_3
? 3'h1
: _csignals_T_33
? 3'h4
: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1}];
exe_reg_rs2_data <= id_rs2_data;
if (_csignals_T_5 | _csignals_T_7)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h6;
else if (_csignals_T_23)
exe_reg_exe_fun <= 5'h7;
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'h8;
else if (_csignals_T_27)
exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_29)
exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_31)
exe_reg_exe_fun <= 5'hC;
else if (_csignals_T_33)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_35)
exe_reg_exe_fun <= 5'hE;
else
exe_reg_exe_fun <= {4'h0, _csignals_T_37};
exe_reg_mem_wen <= 2'h0;
if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_2) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else if (_csignals_T_33) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h3;
end
else if (_csignals_T_35) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <= {1'h0, _csignals_T_37};
exe_reg_wb_sel <= {2'h0, _csignals_T_37};
end
exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_rs2_data <= exe_reg_rs2_data;
mem_reg_mem_wen <= exe_reg_mem_wen;
mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_alu_out <= exe_alu_out;
wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= mem_wb_data;
if (exe_br_flg)
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
else if (exe_jmp_flg)
if_reg_pc <= exe_alu_out;
else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4;
end
end // always @(posedge)
regfile_32x32 regfile_ext (
.R0_addr (id_inst[20:16]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.R1_addr (id_inst[25:21]),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_regfile_ext_R1_data),
.W0_addr (wb_reg_wb_addr),
.W0_en (_id_rs2_data_T_5),
.W0_clk (clock),
.W0_data (wb_reg_wb_data)
);
assign io_imem_addr = if_reg_pc;
assign io_dmem_addr = mem_reg_alu_out;
assign io_dmem_wen = mem_reg_mem_wen[0];
assign io_dmem_wdata = mem_reg_rs2_data;
assign io_exit = id_reg_inst == 32'hC0000000;
endmodule
// VCS coverage exclude_file
module mem_8192x8(
input [12:0] R0_addr,
input R0_en,
R0_clk,
output [7:0] R0_data,
input [12:0] R1_addr,
input R1_en,
R1_clk,
output [7:0] R1_data,
input [12:0] R2_addr,
input R2_en,
R2_clk,
output [7:0] R2_data,
input [12:0] R3_addr,
input R3_en,
R3_clk,
output [7:0] R3_data,
input [12:0] R4_addr,
input R4_en,
R4_clk,
output [7:0] R4_data,
input [12:0] R5_addr,
input R5_en,
R5_clk,
output [7:0] R5_data,
input [12:0] R6_addr,
input R6_en,
R6_clk,
output [7:0] R6_data,
input [12:0] R7_addr,
input R7_en,
R7_clk,
output [7:0] R7_data,
input [12:0] W0_addr,
input W0_en,
W0_clk,
input [7:0] W0_data,
input [12:0] W1_addr,
input W1_en,
W1_clk,
input [7:0] W1_data,
input [12:0] W2_addr,
input W2_en,
W2_clk,
input [7:0] W2_data,
input [12:0] W3_addr,
input W3_en,
W3_clk,
input [7:0] W3_data
);
reg [7:0] Memory[0:8191];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
if (W2_en & 1'h1)
Memory[W2_addr] <= W2_data;
if (W3_en & 1'h1)
Memory[W3_addr] <= W3_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
initial
$readmemh("src/hex/mem.hex", Memory);
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule
module Memory(
input clock,
input [31:0] io_imem_addr,
output [31:0] io_imem_inst,
input [31:0] io_dmem_addr,
output [31:0] io_dmem_rdata,
input io_dmem_wen,
input [31:0] io_dmem_wdata
);
wire [7:0] _mem_ext_R0_data;
wire [7:0] _mem_ext_R1_data;
wire [7:0] _mem_ext_R2_data;
wire [7:0] _mem_ext_R3_data;
wire [7:0] _mem_ext_R4_data;
wire [7:0] _mem_ext_R5_data;
wire [7:0] _mem_ext_R6_data;
wire [7:0] _mem_ext_R7_data;
wire [12:0] _io_dmem_rdata_T_1 = io_dmem_addr[12:0] + 13'h1;
wire [12:0] _io_dmem_rdata_T_4 = io_dmem_addr[12:0] + 13'h2;
wire [12:0] _io_dmem_rdata_T_7 = io_dmem_addr[12:0] + 13'h3;
mem_8192x8 mem_ext (
.R0_addr (io_imem_addr[12:0] + 13'h3),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_mem_ext_R0_data),
.R1_addr (io_imem_addr[12:0] + 13'h2),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_mem_ext_R1_data),
.R2_addr (io_imem_addr[12:0] + 13'h1),
.R2_en (1'h1),
.R2_clk (clock),
.R2_data (_mem_ext_R2_data),
.R3_addr (io_imem_addr[12:0]),
.R3_en (1'h1),
.R3_clk (clock),
.R3_data (_mem_ext_R3_data),
.R4_addr (_io_dmem_rdata_T_7),
.R4_en (1'h1),
.R4_clk (clock),
.R4_data (_mem_ext_R4_data),
.R5_addr (_io_dmem_rdata_T_4),
.R5_en (1'h1),
.R5_clk (clock),
.R5_data (_mem_ext_R5_data),
.R6_addr (_io_dmem_rdata_T_1),
.R6_en (1'h1),
.R6_clk (clock),
.R6_data (_mem_ext_R6_data),
.R7_addr (io_dmem_addr[12:0]),
.R7_en (1'h1),
.R7_clk (clock),
.R7_data (_mem_ext_R7_data),
.W0_addr (_io_dmem_rdata_T_7),
.W0_en (io_dmem_wen),
.W0_clk (clock),
.W0_data (io_dmem_wdata[7:0]),
.W1_addr (_io_dmem_rdata_T_4),
.W1_en (io_dmem_wen),
.W1_clk (clock),
.W1_data (io_dmem_wdata[15:8]),
.W2_addr (_io_dmem_rdata_T_1),
.W2_en (io_dmem_wen),
.W2_clk (clock),
.W2_data (io_dmem_wdata[23:16]),
.W3_addr (io_dmem_addr[12:0]),
.W3_en (io_dmem_wen),
.W3_clk (clock),
.W3_data (io_dmem_wdata[31:24])
);
assign io_imem_inst =
{_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
assign io_dmem_rdata =
{_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule
module Top(
input clock,
reset,
output io_exit
);
wire [31:0] _memory_io_imem_inst;
wire [31:0] _memory_io_dmem_rdata;
wire [31:0] _core_io_imem_addr;
wire [31:0] _core_io_dmem_addr;
wire _core_io_dmem_wen;
wire [31:0] _core_io_dmem_wdata;
Core core (
.clock (clock),
.reset (reset),
.io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata),
.io_exit (io_exit)
);
Memory memory (
.clock (clock),
.io_imem_addr (_core_io_imem_addr),
.io_imem_inst (_memory_io_imem_inst),
.io_dmem_addr (_core_io_dmem_addr),
.io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata)
);
endmodule

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/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

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[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

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/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

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/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

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sbt.internal.DslEntry

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sbt.internal.DslEntry

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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]] ["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

2
project/project/target/streams/compile/bloopGenerate/_global/streams/out
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[debug] [micore-build-build] Classpath dependencies List() [debug] [micore-build-build] Classpath dependencies List()
[debug] [micore-build-build] Dependencies from configurations List() [debug] [micore-build-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/project/ddca/micore/project/project/.bloop/micore-build-build.json' [debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'
[success] Generated .bloop/micore-build-build.json [success] Generated .bloop/micore-build-build.json

2
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/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes

6
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[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak

2
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/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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sbt.internal.DslEntry

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2
project/target/streams/compile/_global/_global/compileOutputs/previous
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2
project/target/streams/compile/bloopGenerate/_global/streams/out
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[debug] [micore-build] Classpath dependencies List() [debug] [micore-build] Classpath dependencies List()
[debug] [micore-build] Dependencies from configurations List() [debug] [micore-build] Dependencies from configurations List()
[debug] Bloop wrote the configuration of project 'micore-build' to '/home/gh0s7/project/ddca/micore/project/.bloop/micore-build.json' [debug] Bloop wrote the configuration of project 'micore-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/.bloop/micore-build.json'
[success] Generated .bloop/micore-build.json [success] Generated .bloop/micore-build.json

2
project/target/streams/compile/exportedProducts/_global/streams/export
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@ -1 +1 @@
/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes

6
project/target/streams/compile/incOptions/_global/streams/out
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[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak

2
project/target/streams/runtime/dependencyClasspath/_global/streams/export
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/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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/home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/sbt-bloop_2.12_1.0/2.0.6/sbt-bloop_2.12_1.0-2.0.6.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/ch/epfl/scala/bloop-config_2.12/2.1.0/bloop-config_2.12-2.1.0.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/plokhotnyuk/jsoniter-scala/jsoniter-scala-core_2.12/2.30.14/jsoniter-scala-core_2.12-2.30.14.jar:/home/gh0s7/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/unroll-annotation_2.12/0.1.12/unroll-annotation_2.12-0.1.12.jar:/home/gh0s7/.sbt/boot/scala-2.12.18/lib/scala-library.jar

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@ -0,0 +1,32 @@
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2
src/main/scala/common/Consts.scala
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@ -8,7 +8,7 @@ object Consts {
val WORD_LEN = 32 // 指令和数据的宽度为32位 val WORD_LEN = 32 // 指令和数据的宽度为32位
val START_ADDR = 0.U(WORD_LEN.W) // 起始地址，设为0 val START_ADDR = 0.U(WORD_LEN.W) // 起始地址，设为0
val BUBBLE = 0x00000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP] val BUBBLE = 0x00000000.U(WORD_LEN.W) // 用于冒泡的指令 [NOP]
val UNIMP = "x_c0000000".U(WORD_LEN.W) // 未实现指令 [SLL $0, $0, 0] val UNIMP = "x_c0000000".U(WORD_LEN.W)
// 寄存器地址长度 // 寄存器地址长度
val ADDR_LEN = 5 // rs1、rs2和写回寄存器的地址宽度为5位 val ADDR_LEN = 5 // rs1、rs2和写回寄存器的地址宽度为5位

7
src/main/scala/micore/Memory.scala
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@ -34,6 +34,13 @@ class Memory extends Module {
mem(io.imem.addr + 3.U(WORD_LEN.W)) mem(io.imem.addr + 3.U(WORD_LEN.W))
) )
io.dmem.rdata := Cat(
mem(io.dmem.addr),
mem(io.dmem.addr + 1.U(WORD_LEN.W)),
mem(io.dmem.addr + 2.U(WORD_LEN.W)),
mem(io.dmem.addr + 3.U(WORD_LEN.W))
)
when(io.dmem.wen) { when(io.dmem.wen) {
mem(io.dmem.addr) := io.dmem.wdata(31, 24) mem(io.dmem.addr) := io.dmem.wdata(31, 24)
mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(23, 16) mem(io.dmem.addr + 1.U(WORD_LEN.W)) := io.dmem.wdata(23, 16)

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target/scala-2.13/-name-_2.13-0.1.0.jar
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@ -1 +1 @@
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["gcd.GCD"] ["micore.Top"]

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@ -1,15 +1,17 @@
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class
[debug]  DmemPortIo.class
[debug]  Memory.class
[debug] We backup class files: [debug] We backup class files:
[debug]  Memory$$anon$1.class
[debug]  ImemPortIo.class
[debug]  DmemPortIo.class
[debug]  Memory.class
[debug] Registering generated classes: [debug] Registering generated classes:
[debug]  GCD$.class [debug]  DmemPortIo.class
[debug]  GcdOutputBundle.class [debug]  Memory$$anon$1.class
[debug]  GCD$$anon$1.class [debug]  ImemPortIo.class
[debug]  GCD.class [debug]  Memory.class
[debug]  GCD$delayedInit$body.class [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes.bak
[debug]  GcdInputBundle.class
[debug]  DecoupledGcd.class
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/target/scala-2.13/classes.bak

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-469312488 -686303872

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@ -1,19 +1,35 @@
[debug] Packaging /home/gh0s7/project/ddca/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ... [debug] Packaging /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/-name-_2.13-0.1.0.jar ...
[debug] Input file mappings: [debug] Input file mappings:
[debug]  gcd [debug]  common
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common
[debug]  gcd/GcdInputBundle.class [debug]  common/Consts$.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdInputBundle.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts$.class
[debug]  gcd/GcdOutputBundle.class [debug]  common/Consts.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GcdOutputBundle.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Consts.class
[debug]  gcd/DecoupledGcd.class [debug]  common/Instructions$.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/DecoupledGcd.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions$.class
[debug]  gcd/GCD.class [debug]  common/Instructions.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/common/Instructions.class
[debug]  gcd/GCD$.class [debug]  micore
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore
[debug]  gcd/GCD$$anon$1.class [debug]  micore/Core$$anon$1.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$$anon$1.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core$$anon$1.class
[debug]  gcd/GCD$delayedInit$body.class [debug]  micore/Core.class
[debug]  /home/gh0s7/project/ddca/micore/target/scala-2.13/classes/gcd/GCD$delayedInit$body.class [debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Core.class
[debug]  micore/DmemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/DmemPortIo.class
[debug]  micore/ImemPortIo.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/ImemPortIo.class
[debug]  micore/Memory$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory$$anon$1.class
[debug]  micore/Memory.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Memory.class
[debug]  micore/Top$$anon$1.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$$anon$1.class
[debug]  micore/Top$.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$.class
[debug]  micore/Top$delayedInit$body.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top$delayedInit$body.class
[debug]  micore/Top.class
[debug]  /run/media/gh0s7/Data/project/ddca2024/micore/target/scala-2.13/classes/micore/Top.class
[debug] Done packaging. [debug] Done packaging.

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