`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:28:52
// Design Name:
// Module Name: Regfile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module regfile_32x32(
  input  [4:0]  R0_addr,
  input         R0_en,
                R0_clk,
  output [31:0] R0_data,
  input  [4:0]  R1_addr,
  input         R1_en,
                R1_clk,
  output [31:0] R1_data,
  input  [4:0]  W0_addr,
  input         W0_en,
                W0_clk,
  output [3:0]  io_anodes,
  output [6:0]  io_segments,
  input  [31:0] W0_data
);

  reg [31:0] Memory[0:31];
  always @(posedge W0_clk) begin
    if (W0_en & 1'h1)
      Memory[W0_addr] <= W0_data;
  end // always @(posedge)
  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
  wire [31:0] reg16_value = Memory[16];
  DynamicDisplay display (
                       .clock        (W0_clk),
                       .reset        (1'b0),
                       .reg_result   (reg16_value),
                       .io_anodes    (io_anodes),
                       .io_segments  (io_segments)
                   );
endmodule