`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:36:13
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module Top_tb;

    reg clock;
    reg reset;
    
    wire        io_exit;

    wire [31:0] if_reg_pc;
    wire [31:0] id_reg_pc;
    wire [31:0] _memory_io_imem_inst;
    wire [31:0] id_inst;
    wire [31:0] id_reg_inst;
    wire [31:0] exe_reg_op1_data;
    wire [31:0] exe_reg_op2_data;
    wire [31:0] exe_alu_out;
    wire [3:0]  exe_reg_exe_fun;
    wire        exe_br_flg;
    wire        stall_flg;
    wire [31:0] mem_reg_alu_out;
    wire [31:0] reg_r8;
    wire [31:0] reg_r10;
    wire [31:0] reg_r16;
    wire [31:0] reg_r18;

    Top uut (
        .clock       (clock),
        .reset       (reset),
        .io_exit     (io_exit)
    );

    assign if_reg_pc = uut.core.if_reg_pc;
    assign id_reg_pc = uut.core.id_reg_pc;
    assign _memory_io_imem_inst = uut.core._memory_io_imem_inst;
    assign id_inst = uut.core.id_inst;
    assign id_reg_inst = uut.core.id_reg_inst;
    assign exe_reg_op1_data = uut.core.exe_reg_op1_data;
    assign exe_reg_op2_data = uut.core.exe_reg_op2_data;
    assign exe_alu_out = uut.core.exe_alu_out;
    assign exe_reg_exe_fun = uut.core.exe_reg_exe_fun;
    assign exe_br_flg = uut.core.exe_br_flg;
    assign stall_flg = uut.core.stall_flg;
    assign mem_reg_alu_out = uut.core.mem_reg_alu_out;
    assign reg_r8 = uut.core.regfile_ext.Memory[8];
    assign reg_r10 = uut.core.regfile_ext.Memory[10];
    assign reg_r16 = uut.core.regfile_ext.Memory[16];
    assign reg_r18 = uut.core.regfile_ext.Memory[18];

    initial begin
        clock = 0;
        forever #5 clock = ~clock; // 10ns 
    end

    initial begin
        reset = 1;
        #20;
        reset = 0;

        #1000;
        $finish;
    end

    always @(posedge clock) begin
        if (!reset) begin
            $display("Cycle: %0d", $time / 10);
            $display("if_reg_pc: %h", if_reg_pc);
            $display("id_reg_pc: %h", id_reg_pc);
            $display("if_inst: %h", _memory_io_imem_inst);
            $display("id_inst: %h", id_inst);
            $display("id_reg_inst: %h", id_reg_inst);
            $display("exe_reg_op1_data: %h", exe_reg_op1_data);
            $display("exe_reg_op2_data: %h", exe_reg_op2_data);
            $display("exe_reg_exe_fun: %h", exe_reg_exe_fun);
            $display("exe_alu_out: %h", exe_alu_out);
            $display("exe_br_flg: %h", exe_br_flg);
            $display("stall_flg: %h", stall_flg);
            $display("mem_reg_alu_out: %h", mem_reg_alu_out);
            $display("Registers:");
            $display("R%0d: %h", 8, reg_r8);
            $display("R%0d: %h", 10, reg_r10);
            $display("R%0d: %h", 16, reg_r16);
            $display("R%0d: %h", 18, reg_r18);
            $display("-----------------------------");
        end
    end

endmodule