`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:36:13
// Design Name:
// Module Name: testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module tb_Top();

    reg clock;
    reg reset;

    wire io_exit;
    wire [3:0] io_anodes;
    wire [6:0] io_segments;

    Top uut (
            .clock(clock),
            .reset(reset),
            .io_exit(io_exit),
            .io_anodes(io_anodes),
            .io_segments(io_segments)
        );

    initial begin
        clock = 0;
        forever
            #5 clock = ~clock; // 10ns周期，50MHz时钟
    end

    initial begin
        reset = 1;
        #20;
        reset = 0;

        #1000;

        $display("Simulation finished.");
        $finish;
    end

    always @(posedge clock) begin
        if (!reset) begin
            // 打印当前PC值和指令
            if (uut.core.io_imem_inst !== 32'hx) begin
                $display("Time: %0t | PC: %h | Instruction: %h", $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
            end

            // 打印ALU输入操作数和计算结果
            if (uut.core.exe_alu_out !== 32'hx) begin
                $display("Time: %0t | ALU Op1: %h | ALU Op2: %h | ALU Result: %h | ALU Fun: %h",
                         $time, uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data,
                         uut.core.exe_alu_out, uut.core.exe_reg_exe_fun);
            end

            // 打印寄存器文件读写操作
            if (uut.core.regfile_ext.W0_en && uut.core.regfile_ext.W0_addr !== 5'hx) begin
                $display("Time: %0t | RegFile Write | Addr: %h | Data: %h",
                         $time, uut.core.regfile_ext.W0_addr, uut.core.regfile_ext.W0_data);
            end
            if (uut.core.regfile_ext.R0_en && uut.core.regfile_ext.R0_addr !== 5'hx) begin
                $display("Time: %0t | RegFile Read R0 | Addr: %h | Data: %h",
                         $time, uut.core.regfile_ext.R0_addr, uut.core.regfile_ext.R0_data);
            end
            if (uut.core.regfile_ext.R1_en && uut.core.regfile_ext.R1_addr !== 5'hx) begin
                $display("Time: %0t | RegFile Read R1 | Addr: %h | Data: %h",
                         $time, uut.core.regfile_ext.R1_addr, uut.core.regfile_ext.R1_data);
            end

            // 打印内存读写操作
            if (uut.memory.io_dmem_wen) begin
                $display("Time: %0t | Memory Write | Addr: %h | Data: %h",
                         $time, uut.memory.io_dmem_addr, uut.memory.io_dmem_wdata);
            end
            if (uut.memory.io_dmem_rdata !== 32'hx) begin
                $display("Time: %0t | Memory Read | Addr: %h | Data: %h",
                         $time, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
            end

            // 打印流水线各阶段的状态
            $display("Time: %0t | IF Stage | PC: %h | Instruction: %h",
                     $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
            $display("Time: %0t | ID Stage | PC: %h | Instruction: %h | Op1: %h | Op2: %h",
                     $time, uut.core.id_reg_pc, uut.core.id_reg_inst,
                     uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data);
            $display("Time: %0t | EXE Stage | PC: %h | ALU Result: %h",
                     $time, uut.core.exe_reg_pc, uut.core.exe_alu_out);
            $display("Time: %0t | MEM Stage | PC: %h | Mem Addr: %h | Mem Data: %h",
                     $time, uut.core.mem_reg_pc, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
            $display("Time: %0t | WB Stage | PC: %h | WB Addr: %h | WB Data: %h",
                     $time, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_data);
        end
    end

    initial begin
        $dumpfile("waveform.vcd");
        $dumpvars(0, tb_Top); // 记录所有信号
    end

endmodule