// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for prints and assertions.

// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
  `ifdef PRINTF_COND
    `define PRINTF_COND_ (`PRINTF_COND)
  `else  // PRINTF_COND
    `define PRINTF_COND_ 1
  `endif // PRINTF_COND
`endif // not def PRINTF_COND_

// VCS coverage exclude_file
module regfile_32x32(
  input  [4:0]  R0_addr,
  input         R0_en,
                R0_clk,
  output [31:0] R0_data,
  input  [4:0]  R1_addr,
  input         R1_en,
                R1_clk,
  output [31:0] R1_data,
  input  [4:0]  W0_addr,
  input         W0_en,
                W0_clk,
  input  [31:0] W0_data
);

  reg [31:0] Memory[0:31];
  always @(posedge W0_clk) begin
    if (W0_en & 1'h1)
      Memory[W0_addr] <= W0_data;
  end // always @(posedge)
  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
endmodule

module Core(
  input         clock,
                reset,
  output [31:0] io_imem_addr,
  input  [31:0] io_imem_inst,
  output [31:0] io_dmem_addr,
  input  [31:0] io_dmem_rdata,
  output        io_dmem_wen,
  output [31:0] io_dmem_wdata,
  output        io_exit
);

  wire [31:0] _regfile_ext_R0_data;
  wire [31:0] _regfile_ext_R1_data;
  reg  [31:0] pc_reg;
  wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
  wire [11:0] _GEN = {io_imem_inst[31:26], io_imem_inst[5:0]};
  wire        jmp_flg = io_imem_inst[31:26] == 6'h3 | _GEN == 12'h8;
  wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R0_data : 32'h0;
  wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R1_data : 32'h0;
  wire        _csignals_T_1 = io_imem_inst[31:26] == 6'h23;
  wire        _csignals_T_3 = io_imem_inst[31:26] == 6'h2B;
  wire        _csignals_T_5 = _GEN == 12'h20;
  wire        _csignals_T_7 = io_imem_inst[31:26] == 6'h8;
  wire        _csignals_T_9 = _GEN == 12'h22;
  wire        _csignals_T_11 = _GEN == 12'h24;
  wire        _csignals_T_13 = _GEN == 12'h25;
  wire        _csignals_T_15 = _GEN == 12'h26;
  wire        _csignals_T_17 = io_imem_inst[31:26] == 6'hC;
  wire        _csignals_T_19 = io_imem_inst[31:26] == 6'hD;
  wire        _csignals_T_21 = _GEN == 12'h2A;
  wire        _csignals_T_23 = io_imem_inst[31:26] == 6'h4;
  wire        _csignals_T_25 = io_imem_inst[31:26] == 6'h5;
  wire [16:0] _GEN_0 = {io_imem_inst[31:21], io_imem_inst[5:0]};
  wire        _csignals_T_27 = _GEN_0 == 17'h0;
  wire        _csignals_T_29 = _GEN_0 == 17'h2;
  wire        _csignals_T_31 = _GEN_0 == 17'h3;
  wire        _csignals_T_33 = io_imem_inst[31:26] == 6'h3;
  wire        _csignals_T_35 = _GEN == 12'h8;
  wire [4:0]  csignals_0 =
    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7
      ? 5'h1
      : _csignals_T_9
          ? 5'h2
          : _csignals_T_11
              ? 5'h3
              : _csignals_T_13
                  ? 5'h4
                  : _csignals_T_15
                      ? 5'h5
                      : _csignals_T_17
                          ? 5'h3
                          : _csignals_T_19
                              ? 5'h4
                              : _csignals_T_21
                                  ? 5'h9
                                  : _csignals_T_23
                                      ? 5'hB
                                      : _csignals_T_25
                                          ? 5'hC
                                          : _csignals_T_27
                                              ? 5'h6
                                              : _csignals_T_29
                                                  ? 5'h7
                                                  : _csignals_T_31
                                                      ? 5'h8
                                                      : _csignals_T_33
                                                          ? 5'h1
                                                          : _csignals_T_35 ? 5'hD : 5'h0;
  wire        _GEN_1 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
  wire        _GEN_2 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_1;
  wire [1:0]  csignals_1 =
    _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
    | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19
    | _GEN_2 | ~_csignals_T_33
      ? 2'h1
      : 2'h2;
  wire [2:0]  csignals_2 =
    _csignals_T_1 | _csignals_T_3
      ? 3'h2
      : _csignals_T_5
          ? 3'h1
          : _csignals_T_7
              ? 3'h2
              : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
                  ? 3'h1
                  : _csignals_T_17 | _csignals_T_19
                      ? 3'h2
                      : _GEN_2 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
  wire        _GEN_3 = _csignals_T_23 | _csignals_T_25;
  wire        _GEN_4 =
    _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
    | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
  wire [1:0]  csignals_4 =
    _csignals_T_1
      ? 2'h1
      : _csignals_T_3
          ? 2'h0
          : _GEN_4
              ? 2'h1
              : _GEN_3
                  ? 2'h0
                  : {1'h0,
                     _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
  wire [2:0]  csignals_5 =
    _csignals_T_1
      ? 3'h2
      : _csignals_T_3
          ? 3'h0
          : _GEN_4 ? 3'h1 : _GEN_3 ? 3'h0 : _GEN_1 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0;
  wire        _op1_data_T = csignals_1 == 2'h1;
  wire        _op1_data_T_1 = csignals_1 == 2'h2;
  wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
  wire [31:0] op2_data =
    csignals_2 == 3'h1
      ? rt_data
      : csignals_2 == 3'h2
          ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
          : csignals_2 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
  wire        _alu_out_T = csignals_0 == 5'h1;
  wire [31:0] _alu_out_T_1 = op1_data + op2_data;
  wire        _alu_out_T_3 = csignals_0 == 5'h2;
  wire [31:0] _alu_out_T_4 = op1_data - op2_data;
  wire        _alu_out_T_6 = csignals_0 == 5'h3;
  wire [31:0] _alu_out_T_7 = op1_data & op2_data;
  wire        _alu_out_T_8 = csignals_0 == 5'h4;
  wire [31:0] _alu_out_T_9 = op1_data | op2_data;
  wire        _alu_out_T_10 = csignals_0 == 5'h5;
  wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
  wire        _alu_out_T_12 = csignals_0 == 5'h6;
  wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
  wire        _alu_out_T_16 = csignals_0 == 5'h7;
  wire [31:0] _GEN_5 = {27'h0, op2_data[4:0]};
  wire [31:0] _alu_out_T_18 = op1_data >> _GEN_5;
  wire        _alu_out_T_19 = csignals_0 == 5'h8;
  wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_5);
  wire        _alu_out_T_24 = csignals_0 == 5'h9;
  wire        _alu_out_T_28 = csignals_0 == 5'hD;
  wire [31:0] _GEN_6 = {31'h0, $signed(op1_data) < $signed(op2_data)};
  wire [31:0] alu_out =
    _alu_out_T
      ? _alu_out_T_1
      : _alu_out_T_3
          ? _alu_out_T_4
          : _alu_out_T_6
              ? _alu_out_T_7
              : _alu_out_T_8
                  ? _alu_out_T_9
                  : _alu_out_T_10
                      ? _alu_out_T_11
                      : _alu_out_T_12
                          ? _alu_out_T_14[31:0]
                          : _alu_out_T_16
                              ? _alu_out_T_18
                              : _alu_out_T_19
                                  ? _alu_out_T_22
                                  : _alu_out_T_24
                                      ? _GEN_6
                                      : _alu_out_T_28 ? op1_data : 32'h0;
  wire        _br_flg_T_3 = op1_data == op2_data;
  wire        br_flg =
    csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
  wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
  wire [31:0] wb_data =
    csignals_5 == 3'h2 ? io_dmem_rdata : csignals_5 == 3'h3 ? _pc_plus4_T : alu_out;
  wire [4:0]  wb_addr =
    csignals_5 == 3'h1 & io_imem_inst[31:26] == 6'h0
      ? io_imem_inst[15:11]
      : io_imem_inst[31:26] == 6'h3 ? 5'h1F : io_imem_inst[20:16];
  `ifndef SYNTHESIS
    always @(posedge clock) begin
      if ((`PRINTF_COND_) & ~reset) begin
        $fwrite(32'h80000002, "---------------\n");
        $fwrite(32'h80000002, "io.imem.inst: 0x%x\n", io_imem_inst);
        $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%b \n", pc_reg, io_imem_inst);
        $fwrite(32'h80000002, "pc_next: 0x%x\n",
                br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
        $fwrite(32'h80000002, "exe_fun: 0x%x\n", csignals_0);
        $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
        $fwrite(32'h80000002, "rt_addr: 0x%x\n", io_imem_inst[20:16]);
        $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
        $fwrite(32'h80000002, "reg: 0x%x\n", _regfile_ext_R1_data);
        $fwrite(32'h80000002, "rf_wen: 0x%x\n", csignals_4);
        $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
        $fwrite(32'h80000002, "rt_data: 0x%x\n", rt_data);
        $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
        $fwrite(32'h80000002, "---------------\n");
      end
    end // always @(posedge)
  `endif // not def SYNTHESIS
  always @(posedge clock) begin
    if (reset)
      pc_reg <= 32'h0;
    else if (br_flg)
      pc_reg <= br_target;
    else if (jmp_flg) begin
      if (_alu_out_T)
        pc_reg <= _alu_out_T_1;
      else if (_alu_out_T_3)
        pc_reg <= _alu_out_T_4;
      else if (_alu_out_T_6)
        pc_reg <= _alu_out_T_7;
      else if (_alu_out_T_8)
        pc_reg <= _alu_out_T_9;
      else if (_alu_out_T_10)
        pc_reg <= _alu_out_T_11;
      else if (_alu_out_T_12)
        pc_reg <= _alu_out_T_14[31:0];
      else if (_alu_out_T_16)
        pc_reg <= _alu_out_T_18;
      else if (_alu_out_T_19)
        pc_reg <= _alu_out_T_22;
      else if (_alu_out_T_24)
        pc_reg <= _GEN_6;
      else if (_alu_out_T_28) begin
        if (_op1_data_T)
          pc_reg <= rs_data;
        else if (~_op1_data_T_1)
          pc_reg <= 32'h0;
      end
      else
        pc_reg <= 32'h0;
    end
    else
      pc_reg <= _pc_plus4_T;
  end // always @(posedge)
  regfile_32x32 regfile_ext (
    .R0_addr (io_imem_inst[25:21]),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (_regfile_ext_R0_data),
    .R1_addr (io_imem_inst[20:16]),
    .R1_en   (1'h1),
    .R1_clk  (clock),
    .R1_data (_regfile_ext_R1_data),
    .W0_addr (wb_addr),
    .W0_en   (csignals_4 == 2'h1 & (|wb_addr)),
    .W0_clk  (clock),
    .W0_data (wb_data)
  );
  assign io_imem_addr = pc_reg;
  assign io_dmem_addr = alu_out;
  assign io_dmem_wen = ~_csignals_T_1 & _csignals_T_3;
  assign io_dmem_wdata = rt_data;
  assign io_exit = io_imem_inst == 32'h114514;
endmodule

// VCS coverage exclude_file
module mem_4096x8(
  input  [11:0] R0_addr,
  input         R0_en,
                R0_clk,
  output [7:0]  R0_data,
  input  [11:0] R1_addr,
  input         R1_en,
                R1_clk,
  output [7:0]  R1_data,
  input  [11:0] R2_addr,
  input         R2_en,
                R2_clk,
  output [7:0]  R2_data,
  input  [11:0] R3_addr,
  input         R3_en,
                R3_clk,
  output [7:0]  R3_data,
  input  [11:0] R4_addr,
  input         R4_en,
                R4_clk,
  output [7:0]  R4_data,
  input  [11:0] R5_addr,
  input         R5_en,
                R5_clk,
  output [7:0]  R5_data,
  input  [11:0] R6_addr,
  input         R6_en,
                R6_clk,
  output [7:0]  R6_data,
  input  [11:0] R7_addr,
  input         R7_en,
                R7_clk,
  output [7:0]  R7_data,
  input  [11:0] W0_addr,
  input         W0_en,
                W0_clk,
  input  [7:0]  W0_data,
  input  [11:0] W1_addr,
  input         W1_en,
                W1_clk,
  input  [7:0]  W1_data,
  input  [11:0] W2_addr,
  input         W2_en,
                W2_clk,
  input  [7:0]  W2_data,
  input  [11:0] W3_addr,
  input         W3_en,
                W3_clk,
  input  [7:0]  W3_data
);

  reg [7:0] Memory[0:4095];
  always @(posedge W0_clk) begin
    if (W0_en & 1'h1)
      Memory[W0_addr] <= W0_data;
    if (W1_en & 1'h1)
      Memory[W1_addr] <= W1_data;
    if (W2_en & 1'h1)
      Memory[W2_addr] <= W2_data;
    if (W3_en & 1'h1)
      Memory[W3_addr] <= W3_data;
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_MEM_
    initial
      $readmemh("src/hex/mem.hex", Memory);
  `endif // ENABLE_INITIAL_MEM_
  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
  assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
  assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
  assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
  assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
  assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
  assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
  assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
endmodule

module Memory(
  input         clock,
  input  [31:0] io_imem_addr,
  output [31:0] io_imem_inst,
  input  [31:0] io_dmem_addr,
  output [31:0] io_dmem_rdata,
  input         io_dmem_wen,
  input  [31:0] io_dmem_wdata
);

  wire [7:0]  _mem_ext_R0_data;
  wire [7:0]  _mem_ext_R1_data;
  wire [7:0]  _mem_ext_R2_data;
  wire [7:0]  _mem_ext_R3_data;
  wire [7:0]  _mem_ext_R4_data;
  wire [7:0]  _mem_ext_R5_data;
  wire [7:0]  _mem_ext_R6_data;
  wire [7:0]  _mem_ext_R7_data;
  wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
  wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
  wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
  mem_4096x8 mem_ext (
    .R0_addr (io_imem_addr[11:0]),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (_mem_ext_R0_data),
    .R1_addr (io_imem_addr[11:0] + 12'h1),
    .R1_en   (1'h1),
    .R1_clk  (clock),
    .R1_data (_mem_ext_R1_data),
    .R2_addr (io_imem_addr[11:0] + 12'h2),
    .R2_en   (1'h1),
    .R2_clk  (clock),
    .R2_data (_mem_ext_R2_data),
    .R3_addr (io_imem_addr[11:0] + 12'h3),
    .R3_en   (1'h1),
    .R3_clk  (clock),
    .R3_data (_mem_ext_R3_data),
    .R4_addr (io_dmem_addr[11:0]),
    .R4_en   (1'h1),
    .R4_clk  (clock),
    .R4_data (_mem_ext_R4_data),
    .R5_addr (_io_dmem_rdata_T_6),
    .R5_en   (1'h1),
    .R5_clk  (clock),
    .R5_data (_mem_ext_R5_data),
    .R6_addr (_io_dmem_rdata_T_3),
    .R6_en   (1'h1),
    .R6_clk  (clock),
    .R6_data (_mem_ext_R6_data),
    .R7_addr (_io_dmem_rdata_T),
    .R7_en   (1'h1),
    .R7_clk  (clock),
    .R7_data (_mem_ext_R7_data),
    .W0_addr (_io_dmem_rdata_T),
    .W0_en   (io_dmem_wen),
    .W0_clk  (clock),
    .W0_data (io_dmem_wdata[31:24]),
    .W1_addr (_io_dmem_rdata_T_3),
    .W1_en   (io_dmem_wen),
    .W1_clk  (clock),
    .W1_data (io_dmem_wdata[23:16]),
    .W2_addr (_io_dmem_rdata_T_6),
    .W2_en   (io_dmem_wen),
    .W2_clk  (clock),
    .W2_data (io_dmem_wdata[15:8]),
    .W3_addr (io_dmem_addr[11:0]),
    .W3_en   (io_dmem_wen),
    .W3_clk  (clock),
    .W3_data (io_dmem_wdata[7:0])
  );
  assign io_imem_inst =
    {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
  assign io_dmem_rdata =
    {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
endmodule

module TopOrigin(
  input  clock,
         reset,
  output io_exit
);

  wire [31:0] _memory_io_imem_inst;
  wire [31:0] _memory_io_dmem_rdata;
  wire [31:0] _core_io_imem_addr;
  wire [31:0] _core_io_dmem_addr;
  wire        _core_io_dmem_wen;
  wire [31:0] _core_io_dmem_wdata;
  Core core (
    .clock         (clock),
    .reset         (reset),
    .io_imem_addr  (_core_io_imem_addr),
    .io_imem_inst  (_memory_io_imem_inst),
    .io_dmem_addr  (_core_io_dmem_addr),
    .io_dmem_rdata (_memory_io_dmem_rdata),
    .io_dmem_wen   (_core_io_dmem_wen),
    .io_dmem_wdata (_core_io_dmem_wdata),
    .io_exit       (io_exit)
  );
  Memory memory (
    .clock         (clock),
    .io_imem_addr  (_core_io_imem_addr),
    .io_imem_inst  (_memory_io_imem_inst),
    .io_dmem_addr  (_core_io_dmem_addr),
    .io_dmem_rdata (_memory_io_dmem_rdata),
    .io_dmem_wen   (_core_io_dmem_wen),
    .io_dmem_wdata (_core_io_dmem_wdata)
  );
endmodule