`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/12/28 11:28:52
// Design Name:
// Module Name: Regfile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

// VCS coverage exclude_file
module Memory(
  input         clock,
  input  [31:0] io_imem_addr,
  output [31:0] io_imem_inst,
  input  [31:0] io_dmem_addr,
  output [31:0] io_dmem_rdata,
  input         io_dmem_wen,
  input  [31:0] io_dmem_wdata
);


  reg [31:0] mem [0:63];


  initial begin
    mem[0] = 32'h20080001;  // addi $t0, $zero, 1
    mem[1] = 32'h20100000;  // addi $s0, $zero, 0
    mem[2] = 32'h20120065;  // addi $s2, $zero, 101
    mem[3] = 32'h02088020;  // add $s0, $s0, $t0
    mem[4] = 32'h21080001;  // addi $t0, $t0, 1
    mem[5] = 32'h0112502a;  // slt $t2, $t0, $s2
    mem[6] = 32'h1540fffc;  // bne $t2, $zero, -4
    mem[7] = 32'h00000000;  // nop
    mem[8] = 32'h00114514;  // exit
  end


  assign io_imem_inst = mem[io_imem_addr[7:2]];

  assign io_dmem_rdata = mem[io_dmem_addr[7:2]];


  always @(posedge clock) begin
    if (io_dmem_wen) begin
      mem[io_dmem_addr[7:2]] <= io_dmem_wdata;
    end
  end
endmodule