`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/28 11:28:52
// Design Name: 
// Module Name: Regfile
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module regfile_32x32(
        input  [4:0]  R0_addr,
        input         R0_en,
        R0_clk,
        output [31:0] R0_data,
        input  [4:0]  R1_addr,
        input         R1_en,
        R1_clk,
        output [31:0] R1_data,
        input  [4:0]  W0_addr,
        input         W0_en,
        W0_clk,
        input  [31:0] W0_data
    );

    reg [31:0] Memory[0:31];
    reg        _R0_en_d0;
    reg [4:0]  _R0_addr_d0;
    always @(posedge R0_clk) begin
        _R0_en_d0 <= R0_en;
        _R0_addr_d0 <= R0_addr;
    end // always @(posedge)
    reg        _R1_en_d0;
    reg [4:0]  _R1_addr_d0;
    always @(posedge R1_clk) begin
        _R1_en_d0 <= R1_en;
        _R1_addr_d0 <= R1_addr;
    end // always @(posedge)
    always @(posedge W0_clk) begin
        if (W0_en & 1'h1)
            Memory[W0_addr] <= W0_data;
    end // always @(posedge)
    assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
    assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;

endmodule