// Generated by CIRCT firtool-1.62.0 // Standard header to adapt well known macros for prints and assertions. // Users can define 'PRINTF_COND' to add an extra gate to prints. `ifndef PRINTF_COND_ `ifdef PRINTF_COND `define PRINTF_COND_ (`PRINTF_COND) `else // PRINTF_COND `define PRINTF_COND_ 1 `endif // PRINTF_COND `endif // not def PRINTF_COND_ // VCS coverage exclude_file module regfile_32x32( input [4:0] R0_addr, input R0_en, R0_clk, output [31:0] R0_data, input [4:0] R1_addr, input R1_en, R1_clk, output [31:0] R1_data, input [4:0] R2_addr, input R2_en, R2_clk, output [31:0] R2_data, input [4:0] W0_addr, input W0_en, W0_clk, input [31:0] W0_data ); reg [31:0] Memory[0:31]; always @(posedge W0_clk) begin if (W0_en & 1'h1) Memory[W0_addr] <= W0_data; end // always @(posedge) assign R0_data = R0_en ? Memory[R0_addr] : 32'bx; assign R1_data = R1_en ? Memory[R1_addr] : 32'bx; assign R2_data = R2_en ? Memory[R2_addr] : 32'bx; endmodule module Core( input clock, reset, output [31:0] io_imem_addr, input [31:0] io_imem_inst, output [31:0] io_dmem_addr, input [31:0] io_dmem_rdata, output io_dmem_wen, output [31:0] io_dmem_wdata, output io_exit, output [31:0] io_gp ); wire [31:0] mem_wb_data; wire exe_jmp_flg; wire exe_br_flg; wire [31:0] _regfile_ext_R1_data; wire [31:0] _regfile_ext_R2_data; reg [31:0] id_reg_pc; reg [31:0] id_reg_inst; reg [31:0] exe_reg_pc; reg [4:0] exe_reg_wb_addr; reg [31:0] exe_reg_op1_data; reg [31:0] exe_reg_op2_data; reg [31:0] exe_reg_rs2_data; reg [4:0] exe_reg_exe_fun; reg [1:0] exe_reg_mem_wen; reg [1:0] exe_reg_rf_wen; reg [2:0] exe_reg_wb_sel; reg [31:0] exe_reg_imm_b_sext; reg [31:0] mem_reg_pc; reg [4:0] mem_reg_wb_addr; reg [31:0] mem_reg_rs2_data; reg [1:0] mem_reg_mem_wen; reg [1:0] mem_reg_rf_wen; reg [2:0] mem_reg_wb_sel; reg [31:0] mem_reg_alu_out; reg [4:0] wb_reg_wb_addr; reg [1:0] wb_reg_rf_wen; reg [31:0] wb_reg_wb_data; reg [31:0] if_reg_pc; wire _id_inst_T = exe_br_flg | exe_jmp_flg; wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; wire stall_flg = _id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; wire _id_rs1_data_T = id_inst[25:21] == 5'h0; wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2; wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5; wire [31:0] id_rs2_data = id_inst[20:16] == 5'h0 ? 32'h0 : id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 ? mem_wb_data : id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 ? wb_reg_wb_data : _regfile_ext_R1_data; wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; wire _csignals_T_5 = _GEN == 17'h20; wire _csignals_T_7 = id_inst[31:28] == 4'h8; wire _csignals_T_9 = _GEN == 17'h22; wire _csignals_T_11 = _GEN == 17'h24; wire _csignals_T_13 = _GEN == 17'h25; wire _csignals_T_15 = _GEN == 17'h26; wire _csignals_T_17 = id_inst[31:28] == 4'hC; wire _csignals_T_19 = id_inst[31:28] == 4'hD; wire _csignals_T_21 = _GEN == 17'h2A; wire _csignals_T_23 = id_inst[31:28] == 4'h4; wire _csignals_T_25 = id_inst[31:28] == 4'h5; wire _csignals_T_27 = id_inst[31:28] == 4'h3; wire _csignals_T_29 = id_inst[31:23] == 9'h1E0; wire _GEN_0 = _csignals_T_27 | _csignals_T_29; wire [4:0] _csignals_T_31 = {4'h0, _GEN_0}; wire _GEN_1 = _csignals_T_5 | _csignals_T_7; wire _GEN_2 = _csignals_T_23 | _csignals_T_25; wire _GEN_3 = _csignals_T_21 | _GEN_2; wire [1:0] csignals_1 = _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 ? 2'h1 : _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29}; wire [2:0] _csignals_T_70 = _csignals_T_5 ? 3'h1 : _csignals_T_7 ? 3'h2 : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 ? 3'h1 : _csignals_T_17 | _csignals_T_19 ? 3'h2 : _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1}; wire [1:0] _csignals_T_87 = {1'h0, _GEN_0}; wire _GEN_4 = _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21; wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29}; wire _id_op1_data_T = csignals_1 == 2'h1; wire _id_op1_data_T_1 = csignals_1 == 2'h2; wire [35:0] id_op2_data = _csignals_T_70 == 3'h1 ? {4'h0, id_rs2_data} : _csignals_T_70 == 3'h2 ? {4'h0, {16{id_inst[15]}}, id_inst[15:0]} : _csignals_T_70 == 3'h3 ? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]} : _csignals_T_70 == 3'h4 ? {{6{id_inst[23]}}, id_inst[25:0], 4'h0} : {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0}; wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data; wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]}; wire [31:0] _exe_alu_out_T_46 = exe_reg_exe_fun == 5'h1 ? _exe_alu_out_T_30 : exe_reg_exe_fun == 5'h2 ? exe_reg_op1_data - exe_reg_op2_data : exe_reg_exe_fun == 5'h3 ? exe_reg_op1_data & exe_reg_op2_data : exe_reg_exe_fun == 5'h4 ? exe_reg_op1_data | exe_reg_op2_data : exe_reg_exe_fun == 5'h5 ? exe_reg_op1_data ^ exe_reg_op2_data : exe_reg_exe_fun == 5'h6 ? _exe_alu_out_T_14[31:0] : exe_reg_exe_fun == 5'h7 ? exe_reg_op1_data >> _GEN_5 : exe_reg_exe_fun == 5'h8 ? $signed($signed(exe_reg_op1_data) >>> _GEN_5) : exe_reg_exe_fun == 5'h9 ? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} : exe_reg_exe_fun == 5'hA ? {31'h0, exe_reg_op1_data < exe_reg_op2_data} : exe_reg_exe_fun == 5'h11 ? _exe_alu_out_T_30 & 32'hFFFFFFFE : exe_reg_exe_fun == 5'h12 ? exe_reg_op1_data : 32'h0; wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data; assign exe_br_flg = exe_reg_exe_fun == 5'hB ? _exe_br_flg_T_3 : exe_reg_exe_fun == 5'hC & ~_exe_br_flg_T_3; assign exe_jmp_flg = exe_reg_wb_sel == 3'h3; assign mem_wb_data = mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out; `ifndef SYNTHESIS always @(posedge clock) begin if ((`PRINTF_COND_) & ~reset) begin automatic logic [31:0] id_rs1_data = _id_rs1_data_T ? 32'h0 : _id_rs1_data_T_3 ? mem_wb_data : _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data; $fwrite(32'h80000002, "---------------------\n"); $fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc); $fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst); $fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst); $fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]); $fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]); $fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]); $fwrite(32'h80000002, "id_exe_fun: 0x%x\n", _GEN_1 ? 5'h1 : _csignals_T_9 ? 5'h2 : _csignals_T_11 ? 5'h3 : _csignals_T_13 ? 5'h4 : _csignals_T_15 ? 5'h5 : _csignals_T_17 ? 5'h3 : _csignals_T_19 ? 5'h4 : _csignals_T_21 ? 5'h9 : _csignals_T_23 ? 5'hB : _csignals_T_25 ? 5'hC : _csignals_T_31); $fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1); $fwrite(32'h80000002, "id_op1_data: 0x%x\n", _id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0); $fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70); $fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data); $fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0); $fwrite(32'h80000002, "id_rf_wen: 0x%x\n", _GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87); $fwrite(32'h80000002, "id_wb_sel: 0x%x\n", _GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100); $fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data); $fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data); $fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46); $fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc); $fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out); $fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data); $fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data); $fwrite(32'h80000002, "---------------------\n"); end end // always @(posedge) `endif // not def SYNTHESIS always @(posedge clock) begin if (reset) begin id_reg_pc <= 32'h0; id_reg_inst <= 32'h0; exe_reg_pc <= 32'h0; exe_reg_wb_addr <= 5'h0; exe_reg_op1_data <= 32'h0; exe_reg_op2_data <= 32'h0; exe_reg_rs2_data <= 32'h0; exe_reg_exe_fun <= 5'h0; exe_reg_mem_wen <= 2'h0; exe_reg_rf_wen <= 2'h0; exe_reg_wb_sel <= 3'h0; exe_reg_imm_b_sext <= 32'h0; mem_reg_pc <= 32'h0; mem_reg_wb_addr <= 5'h0; mem_reg_rs2_data <= 32'h0; mem_reg_mem_wen <= 2'h0; mem_reg_rf_wen <= 2'h0; mem_reg_wb_sel <= 3'h0; mem_reg_alu_out <= 32'h0; wb_reg_wb_addr <= 5'h0; wb_reg_rf_wen <= 2'h0; wb_reg_wb_data <= 32'h0; if_reg_pc <= 32'h400000; end else begin if (~stall_flg) id_reg_pc <= if_reg_pc; if (_id_inst_T) id_reg_inst <= 32'h0; else if (~stall_flg) id_reg_inst <= io_imem_inst; exe_reg_pc <= id_reg_pc; exe_reg_wb_addr <= id_inst[15:11]; if (_id_op1_data_T) begin if (_id_rs1_data_T) exe_reg_op1_data <= 32'h0; else if (_id_rs1_data_T_3) exe_reg_op1_data <= mem_wb_data; else if (_id_rs1_data_T_6) exe_reg_op1_data <= wb_reg_wb_data; else exe_reg_op1_data <= _regfile_ext_R2_data; end else if (_id_op1_data_T_1) exe_reg_op1_data <= id_reg_pc; else exe_reg_op1_data <= 32'h0; exe_reg_op2_data <= id_op2_data[31:0]; exe_reg_rs2_data <= id_rs2_data; if (_GEN_1) exe_reg_exe_fun <= 5'h1; else if (_csignals_T_9) exe_reg_exe_fun <= 5'h2; else if (_csignals_T_11) exe_reg_exe_fun <= 5'h3; else if (_csignals_T_13) exe_reg_exe_fun <= 5'h4; else if (_csignals_T_15) exe_reg_exe_fun <= 5'h5; else if (_csignals_T_17) exe_reg_exe_fun <= 5'h3; else if (_csignals_T_19) exe_reg_exe_fun <= 5'h4; else if (_csignals_T_21) exe_reg_exe_fun <= 5'h9; else if (_csignals_T_23) exe_reg_exe_fun <= 5'hB; else if (_csignals_T_25) exe_reg_exe_fun <= 5'hC; else exe_reg_exe_fun <= _csignals_T_31; exe_reg_mem_wen <= 2'h0; if (_GEN_4) begin exe_reg_rf_wen <= 2'h1; exe_reg_wb_sel <= 3'h1; end else if (_GEN_2) begin exe_reg_rf_wen <= 2'h0; exe_reg_wb_sel <= 3'h0; end else begin exe_reg_rf_wen <= _csignals_T_87; if (_csignals_T_27) exe_reg_wb_sel <= 3'h3; else exe_reg_wb_sel <= _csignals_T_100; end exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0}; mem_reg_pc <= exe_reg_pc; mem_reg_wb_addr <= exe_reg_wb_addr; mem_reg_rs2_data <= exe_reg_rs2_data; mem_reg_mem_wen <= exe_reg_mem_wen; mem_reg_rf_wen <= exe_reg_rf_wen; mem_reg_wb_sel <= exe_reg_wb_sel; mem_reg_alu_out <= _exe_alu_out_T_46; wb_reg_wb_addr <= mem_reg_wb_addr; wb_reg_rf_wen <= mem_reg_rf_wen; wb_reg_wb_data <= mem_wb_data; if (exe_br_flg) if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext; else if (exe_jmp_flg) if_reg_pc <= _exe_alu_out_T_46; else if (~stall_flg) if_reg_pc <= if_reg_pc + 32'h4; end end // always @(posedge) regfile_32x32 regfile_ext ( .R0_addr (5'h3), .R0_en (1'h1), .R0_clk (clock), .R0_data (io_gp), .R1_addr (id_inst[20:16]), .R1_en (1'h1), .R1_clk (clock), .R1_data (_regfile_ext_R1_data), .R2_addr (id_inst[25:21]), .R2_en (1'h1), .R2_clk (clock), .R2_data (_regfile_ext_R2_data), .W0_addr (wb_reg_wb_addr), .W0_en (_id_rs2_data_T_5), .W0_clk (clock), .W0_data (wb_reg_wb_data) ); assign io_imem_addr = if_reg_pc; assign io_dmem_addr = mem_reg_alu_out; assign io_dmem_wen = mem_reg_mem_wen[0]; assign io_dmem_wdata = mem_reg_rs2_data; assign io_exit = id_reg_inst == 32'h114514; endmodule // VCS coverage exclude_file module mem_4096x8( input [11:0] R0_addr, input R0_en, R0_clk, output [7:0] R0_data, input [11:0] R1_addr, input R1_en, R1_clk, output [7:0] R1_data, input [11:0] R2_addr, input R2_en, R2_clk, output [7:0] R2_data, input [11:0] R3_addr, input R3_en, R3_clk, output [7:0] R3_data, input [11:0] R4_addr, input R4_en, R4_clk, output [7:0] R4_data, input [11:0] R5_addr, input R5_en, R5_clk, output [7:0] R5_data, input [11:0] R6_addr, input R6_en, R6_clk, output [7:0] R6_data, input [11:0] R7_addr, input R7_en, R7_clk, output [7:0] R7_data, input [11:0] W0_addr, input W0_en, W0_clk, input [7:0] W0_data, input [11:0] W1_addr, input W1_en, W1_clk, input [7:0] W1_data, input [11:0] W2_addr, input W2_en, W2_clk, input [7:0] W2_data, input [11:0] W3_addr, input W3_en, W3_clk, input [7:0] W3_data ); reg [7:0] Memory[0:4095]; always @(posedge W0_clk) begin if (W0_en & 1'h1) Memory[W0_addr] <= W0_data; if (W1_en & 1'h1) Memory[W1_addr] <= W1_data; if (W2_en & 1'h1) Memory[W2_addr] <= W2_data; if (W3_en & 1'h1) Memory[W3_addr] <= W3_data; end // always @(posedge) `ifdef ENABLE_INITIAL_MEM_ initial $readmemh("src/hex/mem.hex", Memory); `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; assign R2_data = R2_en ? Memory[R2_addr] : 8'bx; assign R3_data = R3_en ? Memory[R3_addr] : 8'bx; assign R4_data = R4_en ? Memory[R4_addr] : 8'bx; assign R5_data = R5_en ? Memory[R5_addr] : 8'bx; assign R6_data = R6_en ? Memory[R6_addr] : 8'bx; assign R7_data = R7_en ? Memory[R7_addr] : 8'bx; endmodule module Memory( input clock, input [31:0] io_imem_addr, output [31:0] io_imem_inst, input [31:0] io_dmem_addr, output [31:0] io_dmem_rdata, input io_dmem_wen, input [31:0] io_dmem_wdata ); wire [7:0] _mem_ext_R0_data; wire [7:0] _mem_ext_R1_data; wire [7:0] _mem_ext_R2_data; wire [7:0] _mem_ext_R3_data; wire [7:0] _mem_ext_R4_data; wire [7:0] _mem_ext_R5_data; wire [7:0] _mem_ext_R6_data; wire [7:0] _mem_ext_R7_data; wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3; wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2; wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1; mem_4096x8 mem_ext ( .R0_addr (io_imem_addr[11:0]), .R0_en (1'h1), .R0_clk (clock), .R0_data (_mem_ext_R0_data), .R1_addr (io_imem_addr[11:0] + 12'h1), .R1_en (1'h1), .R1_clk (clock), .R1_data (_mem_ext_R1_data), .R2_addr (io_imem_addr[11:0] + 12'h2), .R2_en (1'h1), .R2_clk (clock), .R2_data (_mem_ext_R2_data), .R3_addr (io_imem_addr[11:0] + 12'h3), .R3_en (1'h1), .R3_clk (clock), .R3_data (_mem_ext_R3_data), .R4_addr (io_dmem_addr[11:0]), .R4_en (1'h1), .R4_clk (clock), .R4_data (_mem_ext_R4_data), .R5_addr (_io_dmem_rdata_T_6), .R5_en (1'h1), .R5_clk (clock), .R5_data (_mem_ext_R5_data), .R6_addr (_io_dmem_rdata_T_3), .R6_en (1'h1), .R6_clk (clock), .R6_data (_mem_ext_R6_data), .R7_addr (_io_dmem_rdata_T), .R7_en (1'h1), .R7_clk (clock), .R7_data (_mem_ext_R7_data), .W0_addr (_io_dmem_rdata_T), .W0_en (io_dmem_wen), .W0_clk (clock), .W0_data (io_dmem_wdata[31:24]), .W1_addr (_io_dmem_rdata_T_3), .W1_en (io_dmem_wen), .W1_clk (clock), .W1_data (io_dmem_wdata[23:16]), .W2_addr (_io_dmem_rdata_T_6), .W2_en (io_dmem_wen), .W2_clk (clock), .W2_data (io_dmem_wdata[15:8]), .W3_addr (io_dmem_addr[11:0]), .W3_en (io_dmem_wen), .W3_clk (clock), .W3_data (io_dmem_wdata[7:0]) ); assign io_imem_inst = {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data}; assign io_dmem_rdata = {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data}; endmodule module TopOrigin( input clock, reset, output io_exit, output [31:0] io_gp ); wire [31:0] _memory_io_imem_inst; wire [31:0] _memory_io_dmem_rdata; wire [31:0] _core_io_imem_addr; wire [31:0] _core_io_dmem_addr; wire _core_io_dmem_wen; wire [31:0] _core_io_dmem_wdata; Core core ( .clock (clock), .reset (reset), .io_imem_addr (_core_io_imem_addr), .io_imem_inst (_memory_io_imem_inst), .io_dmem_addr (_core_io_dmem_addr), .io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_wen (_core_io_dmem_wen), .io_dmem_wdata (_core_io_dmem_wdata), .io_exit (io_exit), .io_gp (io_gp) ); Memory memory ( .clock (clock), .io_imem_addr (_core_io_imem_addr), .io_imem_inst (_memory_io_imem_inst), .io_dmem_addr (_core_io_dmem_addr), .io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_wen (_core_io_dmem_wen), .io_dmem_wdata (_core_io_dmem_wdata) ); endmodule