117 lines
4.1 KiB
Systemverilog
Executable File
117 lines
4.1 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:36:13
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// Design Name:
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// Module Name: testbench
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_Top();
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reg clock;
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reg reset;
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wire io_exit;
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wire [3:0] io_anodes;
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wire [6:0] io_segments;
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Top uut (
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.clock(clock),
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.reset(reset),
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.io_exit(io_exit),
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.io_anodes(io_anodes),
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.io_segments(io_segments)
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);
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initial begin
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clock = 0;
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forever
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#5 clock = ~clock; // 10ns周期，50MHz时钟
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end
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initial begin
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reset = 1;
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#20;
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reset = 0;
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#1000;
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$display("Simulation finished.");
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$finish;
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end
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always @(posedge clock) begin
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if (!reset) begin
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// 打印当前PC值和指令
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if (uut.core.io_imem_inst !== 32'hx) begin
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$display("Time: %0t | PC: %h | Instruction: %h", $time, uut.core.if_reg_pc, uut.core.io_imem_inst);
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end
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// 打印ALU输入操作数和计算结果
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if (uut.core.exe_alu_out !== 32'hx) begin
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$display("Time: %0t | ALU Op1: %h | ALU Op2: %h | ALU Result: %h | ALU Fun: %h",
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$time, uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data,
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uut.core.exe_alu_out, uut.core.exe_reg_exe_fun);
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end
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// 打印寄存器文件读写操作
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if (uut.core.regfile_ext.W0_en && uut.core.regfile_ext.W0_addr !== 5'hx) begin
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$display("Time: %0t | RegFile Write | Addr: %h | Data: %h",
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$time, uut.core.regfile_ext.W0_addr, uut.core.regfile_ext.W0_data);
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end
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if (uut.core.regfile_ext.R0_en && uut.core.regfile_ext.R0_addr !== 5'hx) begin
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$display("Time: %0t | RegFile Read R0 | Addr: %h | Data: %h",
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$time, uut.core.regfile_ext.R0_addr, uut.core.regfile_ext.R0_data);
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end
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if (uut.core.regfile_ext.R1_en && uut.core.regfile_ext.R1_addr !== 5'hx) begin
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$display("Time: %0t | RegFile Read R1 | Addr: %h | Data: %h",
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$time, uut.core.regfile_ext.R1_addr, uut.core.regfile_ext.R1_data);
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end
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// 打印内存读写操作
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if (uut.memory.io_dmem_wen) begin
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$display("Time: %0t | Memory Write | Addr: %h | Data: %h",
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$time, uut.memory.io_dmem_addr, uut.memory.io_dmem_wdata);
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end
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if (uut.memory.io_dmem_rdata !== 32'hx) begin
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$display("Time: %0t | Memory Read | Addr: %h | Data: %h",
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$time, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
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end
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// 打印流水线各阶段的状态
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$display("Time: %0t | IF Stage | PC: %h | Instruction: %h",
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$time, uut.core.if_reg_pc, uut.core.io_imem_inst);
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$display("Time: %0t | ID Stage | PC: %h | Instruction: %h | Op1: %h | Op2: %h",
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$time, uut.core.id_reg_pc, uut.core.id_reg_inst,
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uut.core.exe_reg_op1_data, uut.core.exe_reg_op2_data);
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$display("Time: %0t | EXE Stage | PC: %h | ALU Result: %h",
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$time, uut.core.exe_reg_pc, uut.core.exe_alu_out);
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$display("Time: %0t | MEM Stage | PC: %h | Mem Addr: %h | Mem Data: %h",
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$time, uut.core.mem_reg_pc, uut.memory.io_dmem_addr, uut.memory.io_dmem_rdata);
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$display("Time: %0t | WB Stage | PC: %h | WB Addr: %h | WB Data: %h",
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$time, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_addr, uut.core.wb_reg_wb_data);
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end
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end
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initial begin
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$dumpfile("waveform.vcd");
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$dumpvars(0, tb_Top); // 记录所有信号
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end
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endmodule
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