60 lines
1.4 KiB
Systemverilog
Executable File
60 lines
1.4 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/28 11:28:52
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// Design Name:
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// Module Name: Regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// VCS coverage exclude_file
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module Memory(
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input clock,
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input [31:0] io_imem_addr,
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output [31:0] io_imem_inst,
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input [31:0] io_dmem_addr,
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output [31:0] io_dmem_rdata,
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input io_dmem_wen,
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input [31:0] io_dmem_wdata
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);
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reg [31:0] mem [0:63];
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initial begin
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mem[0] = 32'h20080001; // addi $t0, $zero, 1
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mem[1] = 32'h20100000; // addi $s0, $zero, 0
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mem[2] = 32'h20120065; // addi $s2, $zero, 101
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mem[3] = 32'h02088020; // add $s0, $s0, $t0
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mem[4] = 32'h21080001; // addi $t0, $t0, 1
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mem[5] = 32'h0112502a; // slt $t2, $t0, $s2
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mem[6] = 32'h1540fffc; // bne $t2, $zero, -4
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mem[7] = 32'h00000000; // nop
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mem[8] = 32'h00114514; // exit
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end
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assign io_imem_inst = mem[io_imem_addr[7:2]];
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assign io_dmem_rdata = mem[io_dmem_addr[7:2]];
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always @(posedge clock) begin
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if (io_dmem_wen) begin
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mem[io_dmem_addr[7:2]] <= io_dmem_wdata;
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end
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end
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endmodule |