67 lines
2.0 KiB
Systemverilog
Executable File
67 lines
2.0 KiB
Systemverilog
Executable File
module DynamicDisplay(
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input clock,
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reset,
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input [31:0] reg_result,
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output [3:0] io_anodes,
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output [6:0] io_segments
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);
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reg [6:0] digit_segments [0:9];
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initial begin
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digit_segments[0] = 7'b0000001;
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digit_segments[1] = 7'b1001111;
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digit_segments[2] = 7'b0010010;
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digit_segments[3] = 7'b0000110;
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digit_segments[4] = 7'b1001100;
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digit_segments[5] = 7'b0100100;
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digit_segments[6] = 7'b0100000;
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digit_segments[7] = 7'b0001111;
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digit_segments[8] = 7'b0000000;
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digit_segments[9] = 7'b0000100;
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end
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reg [3:0] anode_select [0:3];
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initial begin
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anode_select[0] = 4'b1110;
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anode_select[1] = 4'b1101;
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anode_select[2] = 4'b1011;
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anode_select[3] = 4'b0111;
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end
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// 扫描计数器和时钟分频
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reg [15:0] clkDiv; // 分频计数器
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reg [1:0] scanCounter; // 扫描计数器
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wire clk1kHz = (clkDiv == 16'd50_000);
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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clkDiv <= 16'd0;
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scanCounter <= 2'd0;
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end
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else begin
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if (clk1kHz) begin
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clkDiv <= 16'd0;
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scanCounter <= scanCounter + 2'd1;
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end
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else begin
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clkDiv <= clkDiv + 16'd1;
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end
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end
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end
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reg [3:0] digit_value;
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always @(*) begin
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case (scanCounter)
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2'b11: digit_value = reg_result / 1000; // 千位
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2'b10: digit_value = (reg_result / 100) % 10; // 百位
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2'b01: digit_value = (reg_result / 10) % 10; // 十位
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2'b00: digit_value = reg_result % 10; // 个位
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default:
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digit_value = 4'd0;
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endcase
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end
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assign io_segments = digit_segments[digit_value];
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assign io_anodes = anode_select[scanCounter];
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endmodule |