28 lines
564 B
Systemverilog
28 lines
564 B
Systemverilog
// Generated by CIRCT firtool-1.62.0
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module GCD(
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input clock,
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reset,
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input [15:0] io_value1,
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io_value2,
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input io_loadingValues,
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output [15:0] io_outputGCD,
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output io_outputValid
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);
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reg [15:0] x;
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reg [15:0] y;
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always @(posedge clock) begin
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if (io_loadingValues) begin
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x <= io_value1;
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y <= io_value2;
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end
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else if (x > y)
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x <= x - y;
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else
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y <= y - x;
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end // always @(posedge)
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assign io_outputGCD = x;
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assign io_outputValid = y == 16'h0;
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endmodule
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