426 lines
14 KiB
Systemverilog
Executable File
426 lines
14 KiB
Systemverilog
Executable File
// Generated by CIRCT firtool-1.62.0
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// VCS coverage exclude_file
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module regfile_32x32(
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input [4:0] R0_addr,
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input R0_en,
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R0_clk,
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output [31:0] R0_data,
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input [4:0] R1_addr,
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input R1_en,
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R1_clk,
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output [31:0] R1_data,
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input [4:0] W0_addr,
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input W0_en,
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W0_clk,
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input [31:0] W0_data
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);
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reg [31:0] Memory[0:31];
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reg _R0_en_d0;
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reg [4:0] _R0_addr_d0;
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always @(posedge R0_clk) begin
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_R0_en_d0 <= R0_en;
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_R0_addr_d0 <= R0_addr;
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end // always @(posedge)
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reg _R1_en_d0;
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reg [4:0] _R1_addr_d0;
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always @(posedge R1_clk) begin
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_R1_en_d0 <= R1_en;
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_R1_addr_d0 <= R1_addr;
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end // always @(posedge)
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
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assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
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endmodule
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module Core(
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input clock,
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reset,
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output [31:0] io_imem_addr,
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input [31:0] io_imem_inst,
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output [31:0] io_dmem_addr,
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input [31:0] io_dmem_rdata,
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output io_dmem_wen,
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output [31:0] io_dmem_wdata,
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output io_exit
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);
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wire [31:0] _regfile_ext_R0_data;
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wire [31:0] _regfile_ext_R1_data;
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reg [31:0] id_reg_pc;
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reg [31:0] id_reg_inst;
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reg [31:0] exe_reg_pc;
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reg [4:0] exe_reg_wb_addr;
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reg [31:0] exe_reg_op1_data;
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reg [31:0] exe_reg_op2_data;
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reg [31:0] exe_reg_rs2_data;
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reg [4:0] exe_reg_exe_fun;
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reg [1:0] exe_reg_mem_wen;
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reg [1:0] exe_reg_rf_wen;
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reg [2:0] exe_reg_wb_sel;
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reg [31:0] exe_reg_imm_b_sext;
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reg [31:0] mem_reg_pc;
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reg [4:0] mem_reg_wb_addr;
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reg [31:0] mem_reg_alu_out;
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reg [31:0] mem_reg_rs2_data;
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reg [1:0] mem_reg_rf_wen;
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reg [2:0] mem_reg_wb_sel;
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reg [1:0] mem_reg_mem_wen;
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reg [4:0] wb_reg_wb_addr;
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reg [1:0] wb_reg_rf_wen;
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reg [31:0] wb_reg_wb_data;
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reg [31:0] if_reg_pc;
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wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1;
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wire exe_br_flg =
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exe_reg_exe_fun == 5'hC
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? exe_reg_op1_data != exe_reg_op2_data
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: exe_reg_exe_fun == 5'hB & exe_reg_op1_data == exe_reg_op2_data;
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wire exe_jmp_flg = exe_reg_wb_sel == 3'h3;
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always @(posedge clock) begin
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automatic logic _id_inst_T = exe_br_flg | exe_jmp_flg;
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automatic logic _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1;
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automatic logic stall_flg;
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automatic logic [31:0] id_inst;
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automatic logic _id_rs2_data_T_2;
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automatic logic _id_rs2_data_T;
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automatic logic [31:0] _id_rs2_data_T_8;
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automatic logic [16:0] _GEN;
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automatic logic _csignals_T_5;
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automatic logic [19:0] _GEN_0;
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automatic logic _csignals_T_7;
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automatic logic _csignals_T_9;
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automatic logic _csignals_T_11;
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automatic logic _csignals_T_13;
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automatic logic _csignals_T_15;
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automatic logic _csignals_T_17;
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automatic logic _csignals_T_19;
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automatic logic [16:0] _GEN_1;
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automatic logic _csignals_T_21;
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automatic logic _csignals_T_23;
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automatic logic _csignals_T_25;
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automatic logic _csignals_T_27;
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automatic logic _csignals_T_29;
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automatic logic _csignals_T_31;
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automatic logic _csignals_T_33;
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automatic logic _csignals_T_35;
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automatic logic _csignals_T_37;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic [1:0] csignals_1;
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automatic logic [2:0] _csignals_T_90;
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automatic logic [31:0] _GEN_4 = {27'h0, exe_reg_op2_data[4:0]};
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automatic logic [62:0] _exe_alu_out_T_8 =
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{31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
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automatic logic [31:0] exe_alu_out;
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stall_flg =
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_id_rs2_data_hazard_T & (|(id_reg_inst[25:21]))
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& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T
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& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
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id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst;
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_id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1;
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_id_rs2_data_T = id_reg_inst[20:16] == 5'h0;
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_id_rs2_data_T_8 =
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id_reg_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R0_data;
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_GEN = {id_inst[31:26], id_inst[10:0]};
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_csignals_T_5 = _GEN == 17'h20;
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_GEN_0 = {id_inst[31:28], id_inst[15:0]};
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_csignals_T_7 = _GEN_0 == 20'h80000;
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_csignals_T_9 = _GEN == 17'h22;
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_csignals_T_11 = _GEN == 17'h24;
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_csignals_T_13 = _GEN == 17'h25;
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_csignals_T_15 = _GEN == 17'h26;
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_csignals_T_17 = _GEN_0 == 20'hC0000;
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_csignals_T_19 = _GEN_0 == 20'hD0000;
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_GEN_1 = {id_inst[30:20], id_inst[5:0]};
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_csignals_T_21 = _GEN_1 == 17'h0;
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_csignals_T_23 = _GEN_1 == 17'h2;
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_csignals_T_25 = _GEN_1 == 17'h3;
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_csignals_T_27 = _GEN == 17'h2A;
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_csignals_T_29 = _GEN_0 == 20'h40000;
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_csignals_T_31 = _GEN_0 == 20'h50000;
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_csignals_T_33 = id_inst == 32'hC000000;
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_csignals_T_35 = _GEN_0 == 20'h8;
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_csignals_T_37 = {id_inst[31:22], id_inst[9:0]} == 20'h78000;
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_GEN_2 = _csignals_T_29 | _csignals_T_31;
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_GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _csignals_T_27 | _GEN_2;
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csignals_1 =
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_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3
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? 2'h0
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: _csignals_T_33 ? 2'h1 : _csignals_T_35 ? 2'h0 : {_csignals_T_37, 1'h0};
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_csignals_T_90 =
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_csignals_T_5
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? 3'h1
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: _csignals_T_7
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? 3'h2
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: _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
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? 3'h1
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: _csignals_T_17 | _csignals_T_19
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? 3'h2
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: _GEN_3
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? 3'h1
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: _csignals_T_33
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? 3'h4
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: _csignals_T_35 ? 3'h0 : {_csignals_T_37, 2'h1};
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exe_alu_out =
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exe_reg_exe_fun == 5'hE
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? exe_reg_op1_data
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: exe_reg_exe_fun == 5'h9
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? {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)}
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: exe_reg_exe_fun == 5'h8
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? $signed($signed(exe_reg_op1_data) >>> _GEN_4)
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: exe_reg_exe_fun == 5'h7
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? exe_reg_op1_data >> _GEN_4
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: exe_reg_exe_fun == 5'h6
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? _exe_alu_out_T_8[31:0]
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: exe_reg_exe_fun == 5'h5
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? exe_reg_op1_data ^ exe_reg_op2_data
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: exe_reg_exe_fun == 5'h4
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? exe_reg_op1_data | exe_reg_op2_data
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: exe_reg_exe_fun == 5'h3
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? exe_reg_op1_data & exe_reg_op2_data
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: exe_reg_exe_fun == 5'h2
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? exe_reg_op1_data - exe_reg_op2_data
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: exe_reg_exe_fun == 5'h1
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? exe_reg_op1_data + exe_reg_op2_data
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: 32'h0;
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if (~stall_flg)
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id_reg_pc <= if_reg_pc;
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if (_id_inst_T)
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id_reg_inst <= 32'h0;
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else if (~stall_flg)
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id_reg_inst <= io_imem_inst;
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exe_reg_pc <= id_reg_pc;
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exe_reg_wb_addr <= id_reg_inst[15:11];
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if (csignals_1 == 2'h0)
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exe_reg_op1_data <=
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id_reg_inst[25:21] == 5'h0
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? 32'h0
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: id_reg_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2
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? mem_reg_alu_out
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: id_reg_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5
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? wb_reg_wb_data
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: _regfile_ext_R1_data;
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else if (csignals_1 == 2'h1)
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exe_reg_op1_data <= id_reg_pc;
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else
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exe_reg_op1_data <= 32'h0;
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if (_csignals_T_90 == 3'h5)
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exe_reg_op2_data <= {id_inst[15:0], 16'h0};
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else if (_csignals_T_90 == 3'h4)
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exe_reg_op2_data <= {{4{id_inst[25]}}, id_inst[25:0], 2'h0};
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else if (_csignals_T_90 == 3'h3 | _csignals_T_90 == 3'h2)
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exe_reg_op2_data <= {{16{id_inst[15]}}, id_inst[15:0]};
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else if (_csignals_T_90 != 3'h1 | _id_rs2_data_T)
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exe_reg_op2_data <= 32'h0;
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else
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exe_reg_op2_data <= _id_rs2_data_T_8;
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exe_reg_rs2_data <= _id_rs2_data_T ? 32'h0 : _id_rs2_data_T_8;
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if (_csignals_T_5 | _csignals_T_7)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_9)
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exe_reg_exe_fun <= 5'h2;
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else if (_csignals_T_11)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_13)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_15)
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exe_reg_exe_fun <= 5'h5;
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else if (_csignals_T_17)
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exe_reg_exe_fun <= 5'h3;
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else if (_csignals_T_19)
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exe_reg_exe_fun <= 5'h4;
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else if (_csignals_T_21)
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exe_reg_exe_fun <= 5'h6;
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else if (_csignals_T_23)
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exe_reg_exe_fun <= 5'h7;
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else if (_csignals_T_25)
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exe_reg_exe_fun <= 5'h8;
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else if (_csignals_T_27)
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exe_reg_exe_fun <= 5'h9;
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else if (_csignals_T_29)
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exe_reg_exe_fun <= 5'hB;
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else if (_csignals_T_31)
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exe_reg_exe_fun <= 5'hC;
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else if (_csignals_T_33)
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exe_reg_exe_fun <= 5'h1;
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else if (_csignals_T_35)
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exe_reg_exe_fun <= 5'hE;
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else
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exe_reg_exe_fun <= {4'h0, _csignals_T_37};
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exe_reg_mem_wen <= 2'h0;
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if (_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
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| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21
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| _csignals_T_23 | _csignals_T_25 | _csignals_T_27) begin
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exe_reg_rf_wen <= 2'h1;
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exe_reg_wb_sel <= 3'h1;
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end
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else if (_GEN_2) begin
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exe_reg_rf_wen <= 2'h0;
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exe_reg_wb_sel <= 3'h0;
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end
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else if (_csignals_T_33) begin
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exe_reg_rf_wen <= 2'h1;
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exe_reg_wb_sel <= 3'h3;
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end
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else if (_csignals_T_35) begin
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exe_reg_rf_wen <= 2'h0;
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exe_reg_wb_sel <= 3'h0;
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end
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else begin
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exe_reg_rf_wen <= {1'h0, _csignals_T_37};
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exe_reg_wb_sel <= {2'h0, _csignals_T_37};
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end
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exe_reg_imm_b_sext <= {{16{id_inst[15]}}, id_inst[15:0]};
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mem_reg_pc <= exe_reg_pc;
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mem_reg_wb_addr <= exe_reg_wb_addr;
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mem_reg_alu_out <= exe_alu_out;
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mem_reg_rs2_data <= exe_reg_rs2_data;
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mem_reg_rf_wen <= exe_reg_rf_wen;
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mem_reg_wb_sel <= exe_reg_wb_sel;
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mem_reg_mem_wen <= exe_reg_mem_wen;
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wb_reg_wb_addr <= mem_reg_wb_addr;
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wb_reg_rf_wen <= mem_reg_rf_wen;
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wb_reg_wb_data <=
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mem_reg_wb_sel == 3'h3
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? mem_reg_pc + 32'h4
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: mem_reg_wb_sel == 3'h2 ? io_dmem_rdata : mem_reg_alu_out;
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if (reset)
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if_reg_pc <= 32'h0;
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else if (exe_br_flg)
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if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
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else if (exe_jmp_flg)
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if_reg_pc <= exe_alu_out;
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else if (~stall_flg)
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if_reg_pc <= if_reg_pc + 32'h4;
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end // always @(posedge)
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regfile_32x32 regfile_ext (
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.R0_addr (id_reg_inst[20:16]),
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.R0_en (1'h1),
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.R0_clk (clock),
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.R0_data (_regfile_ext_R0_data),
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.R1_addr (id_reg_inst[25:21]),
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.R1_en (1'h1),
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.R1_clk (clock),
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.R1_data (_regfile_ext_R1_data),
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.W0_addr (wb_reg_wb_addr),
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.W0_en (_id_rs2_data_T_5),
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.W0_clk (clock),
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.W0_data (wb_reg_wb_data)
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);
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assign io_imem_addr = if_reg_pc;
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assign io_dmem_addr = mem_reg_alu_out;
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assign io_dmem_wen = mem_reg_mem_wen[0];
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assign io_dmem_wdata = mem_reg_rs2_data;
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assign io_exit = id_reg_inst == 32'hC0000000;
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endmodule
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// VCS coverage exclude_file
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module mem_512x32(
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input [8:0] R0_addr,
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input R0_en,
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R0_clk,
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output [31:0] R0_data,
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input [8:0] R1_addr,
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input R1_en,
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R1_clk,
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output [31:0] R1_data,
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input [8:0] W0_addr,
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input W0_en,
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W0_clk,
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input [31:0] W0_data
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);
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reg [31:0] Memory[0:511];
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reg _R0_en_d0;
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reg [8:0] _R0_addr_d0;
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always @(posedge R0_clk) begin
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_R0_en_d0 <= R0_en;
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_R0_addr_d0 <= R0_addr;
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end // always @(posedge)
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reg _R1_en_d0;
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reg [8:0] _R1_addr_d0;
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always @(posedge R1_clk) begin
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_R1_en_d0 <= R1_en;
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_R1_addr_d0 <= R1_addr;
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end // always @(posedge)
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always @(posedge W0_clk) begin
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if (W0_en & 1'h1)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_MEM_
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initial
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$readmemh("src/hex/mem.hex", Memory);
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`endif // ENABLE_INITIAL_MEM_
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assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;
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assign R1_data = _R1_en_d0 ? Memory[_R1_addr_d0] : 32'bx;
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endmodule
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module Memory(
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input clock,
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input [31:0] io_imem_addr,
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output [31:0] io_imem_inst,
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input [31:0] io_dmem_addr,
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output [31:0] io_dmem_rdata,
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input io_dmem_wen,
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input [31:0] io_dmem_wdata
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);
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mem_512x32 mem_ext (
|
|
.R0_addr (io_imem_addr[10:2]),
|
|
.R0_en (1'h1),
|
|
.R0_clk (clock),
|
|
.R0_data (io_imem_inst),
|
|
.R1_addr (io_dmem_addr[10:2]),
|
|
.R1_en (1'h1),
|
|
.R1_clk (clock),
|
|
.R1_data (io_dmem_rdata),
|
|
.W0_addr (io_dmem_addr[10:2]),
|
|
.W0_en (io_dmem_wen),
|
|
.W0_clk (clock),
|
|
.W0_data (io_dmem_wdata)
|
|
);
|
|
endmodule
|
|
|
|
module Top(
|
|
input clock,
|
|
reset,
|
|
output io_exit
|
|
);
|
|
|
|
wire [31:0] _memory_io_imem_inst;
|
|
wire [31:0] _memory_io_dmem_rdata;
|
|
wire [31:0] _core_io_imem_addr;
|
|
wire [31:0] _core_io_dmem_addr;
|
|
wire _core_io_dmem_wen;
|
|
wire [31:0] _core_io_dmem_wdata;
|
|
Core core (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_imem_addr (_core_io_imem_addr),
|
|
.io_imem_inst (_memory_io_imem_inst),
|
|
.io_dmem_addr (_core_io_dmem_addr),
|
|
.io_dmem_rdata (_memory_io_dmem_rdata),
|
|
.io_dmem_wen (_core_io_dmem_wen),
|
|
.io_dmem_wdata (_core_io_dmem_wdata),
|
|
.io_exit (io_exit)
|
|
);
|
|
Memory memory (
|
|
.clock (clock),
|
|
.io_imem_addr (_core_io_imem_addr),
|
|
.io_imem_inst (_memory_io_imem_inst),
|
|
.io_dmem_addr (_core_io_dmem_addr),
|
|
.io_dmem_rdata (_memory_io_dmem_rdata),
|
|
.io_dmem_wen (_core_io_dmem_wen),
|
|
.io_dmem_wdata (_core_io_dmem_wdata)
|
|
);
|
|
endmodule
|
|
|